NVParamDef.h 48 KB

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  1. /** @file
  2. The non-volatile parameter layout in SPI-NOR is shown below. There is
  3. two copies. The master copy is changeable by the user. The Last Known
  4. copy is handled by the fail safe future. It is a last know bootable copy.
  5. ---------------------------
  6. | Master Copy | 16KB
  7. | Pre-boot parameters |
  8. ---------------------------
  9. | Master Copy | 16KB
  10. | Pre-boot parameters |
  11. | w/o failsafe support |
  12. ---------------------------
  13. | Master Copy |
  14. | Manufactory & | 32KB
  15. | Users parameters |
  16. ---------------------------
  17. | Last Known Copy | 16KB
  18. | Pre-boot parameters |
  19. ---------------------------
  20. | | 16KB
  21. ---------------------------
  22. | Last Known Copy |
  23. | Manufactory & | 32KB
  24. | Users parameters |
  25. ---------------------------
  26. As each non-volatile parameter requires 8 bytes, there is a total of 8K
  27. parameters.
  28. Copyright (c) 2020 - 2023, Ampere Computing LLC. All rights reserved.<BR>
  29. SPDX-License-Identifier: BSD-2-Clause-Patent
  30. **/
  31. #ifndef NVPARAMDEF_H_
  32. #define NVPARAMDEF_H_
  33. //
  34. // SoC validation pre-boot non-volatile setting
  35. //
  36. // These parameters will reset to default value on failsafe.
  37. // They are not used in production life cycle.
  38. //
  39. #define NV_PREBOOT_PARAM_START (0x000000)
  40. #define NV_SI_PCP_VDMC ((1 * 8) + NV_PREBOOT_PARAM_START)
  41. #define NV_SI_FAILSAFE_RETRY ((2 * 8) + NV_PREBOOT_PARAM_START)
  42. #define NV_SI_DDR_PPR_EN ((3 * 8) + NV_PREBOOT_PARAM_START)
  43. #define NV_SI_DDR_RESERVED0 ((4 * 8) + NV_PREBOOT_PARAM_START)
  44. #define NV_SI_DDR_RESERVED1 ((5 * 8) + NV_PREBOOT_PARAM_START)
  45. #define NV_SI_DDR_LOG_LEVEL ((6 * 8) + NV_PREBOOT_PARAM_START)
  46. #define NV_SI_DDR_RESERVED2 ((7 * 8) + NV_PREBOOT_PARAM_START)
  47. #define NV_SI_DDR_RD_DBI_EN ((8 * 8) + NV_PREBOOT_PARAM_START)
  48. #define NV_SI_DDR_WR_DBI_EN ((9 * 8) + NV_PREBOOT_PARAM_START)
  49. #define NV_SI_DDR_RETRY_EN ((10 * 8) + NV_PREBOOT_PARAM_START)
  50. #define NV_SI_DDR_BANK_HASH_EN ((11 * 8) + NV_PREBOOT_PARAM_START)
  51. #define NV_SI_DDR_RESERVED3 ((12 * 8) + NV_PREBOOT_PARAM_START)
  52. #define NV_SI_DDR_RCD_PARITY_EN ((13 * 8) + NV_PREBOOT_PARAM_START)
  53. #define NV_SI_DDR_WRPATH_CLK_GATE_EN ((14 * 8) + NV_PREBOOT_PARAM_START)
  54. #define NV_SI_DDR_IOCAL_MARGIN ((15 * 8) + NV_PREBOOT_PARAM_START)
  55. #define NV_SI_DDR_RTR_S_MARGIN ((16 * 8) + NV_PREBOOT_PARAM_START)
  56. #define NV_SI_DDR_RTR_L_MARGIN ((17 * 8) + NV_PREBOOT_PARAM_START)
  57. #define NV_SI_DDR_RTR_CS_MARGIN ((18 * 8) + NV_PREBOOT_PARAM_START)
  58. #define NV_SI_DDR_WTW_S_MARGIN ((19 * 8) + NV_PREBOOT_PARAM_START)
  59. #define NV_SI_DDR_WTW_L_MARGIN ((20 * 8) + NV_PREBOOT_PARAM_START)
  60. #define NV_SI_DDR_WTW_CS_MARGIN ((21 * 8) + NV_PREBOOT_PARAM_START)
  61. #define NV_SI_DDR_RTW_S_MARGIN ((22 * 8) + NV_PREBOOT_PARAM_START)
  62. #define NV_SI_DDR_RTW_L_MARGIN ((23 * 8) + NV_PREBOOT_PARAM_START)
  63. #define NV_SI_DDR_RTW_CS_MARGIN ((24 * 8) + NV_PREBOOT_PARAM_START)
  64. #define NV_SI_DDR_WTR_S_MARGIN ((25 * 8) + NV_PREBOOT_PARAM_START)
  65. #define NV_SI_DDR_WTR_L_MARGIN ((26 * 8) + NV_PREBOOT_PARAM_START)
  66. #define NV_SI_DDR_WTR_CS_MARGIN ((27 * 8) + NV_PREBOOT_PARAM_START)
  67. #define NV_SI_DDR_PARITY_EN ((28 * 8) + NV_PREBOOT_PARAM_START)
  68. #define NV_SI_SLC_DISABLE ((29 * 8) + NV_PREBOOT_PARAM_START)
  69. #define NV_SI_SLC_SIZE ((30 * 8) + NV_PREBOOT_PARAM_START)
  70. #define NV_SI_SLC_SCRUB ((31 * 8) + NV_PREBOOT_PARAM_START)
  71. #define NV_SI_CCIX_DISABLE ((32 * 8) + NV_PREBOOT_PARAM_START)
  72. #define NV_SI_ESM_RESERVED ((33 * 8) + NV_PREBOOT_PARAM_START)
  73. #define NV_SI_DDR_PHY_CAL_MODE ((34 * 8) + NV_PREBOOT_PARAM_START)
  74. #define NV_SI_RAS_TEST_EN ((35 * 8) + NV_PREBOOT_PARAM_START)
  75. #define NV_SI_DDR_EYE_SCREEN_TEST_EN ((36 * 8) + NV_PREBOOT_PARAM_START)
  76. #define NV_SI_DDR_EYE_MASK_RD_MARGIN ((37 * 8) + NV_PREBOOT_PARAM_START)
  77. #define NV_SI_DDR_EYE_MASK_WR_MARGIN ((38 * 8) + NV_PREBOOT_PARAM_START)
  78. #define NV_SI_DDR_RDODT_ON_MARGIN ((39 * 8) + NV_PREBOOT_PARAM_START)
  79. #define NV_SI_DDR_RDODT_OFF_MARGIN ((40 * 8) + NV_PREBOOT_PARAM_START)
  80. #define NV_SI_DDR_WRODT_ON_MARGIN ((41 * 8) + NV_PREBOOT_PARAM_START)
  81. #define NV_SI_DDR_WRODT_OFF_MARGIN ((42 * 8) + NV_PREBOOT_PARAM_START)
  82. #define NV_SI_SLC_OCM_EN ((43 * 8) + NV_PREBOOT_PARAM_START)
  83. #define NV_SI_ESM_WIDTH ((44 * 8) + NV_PREBOOT_PARAM_START)
  84. #define NV_SI_TM2_DISABLE ((45 * 8) + NV_PREBOOT_PARAM_START)
  85. #define NV_SI_CPUPLL_FREQ_MHZ ((46 * 8) + NV_PREBOOT_PARAM_START)
  86. #define NV_SI_DDR_ERR_INJECT_MASK_SK0 ((47 * 8) + NV_PREBOOT_PARAM_START)
  87. #define NV_SI_DDR_ERR_INJECT_MASK_SK1 ((48 * 8) + NV_PREBOOT_PARAM_START)
  88. #define NV_SI_CXG_DISABLE_EARLY_COMPACK ((49 * 8) + NV_PREBOOT_PARAM_START)
  89. #define NV_SI_CXG_ENABLE_SAME_ADDR_COMP_ORDER ((50 * 8) + NV_PREBOOT_PARAM_START)
  90. #define NV_SI_DDR_TURNAROUND_CONTROL ((51 * 8) + NV_PREBOOT_PARAM_START)
  91. #define NV_SI_DDR_HIT_TURNAROUND_CONTROL ((52 * 8) + NV_PREBOOT_PARAM_START)
  92. #define NV_SI_DDR_QOS_CLASS_CONTROL ((53 * 8) + NV_PREBOOT_PARAM_START)
  93. #define NV_SI_DDR_ESCALATION_CONTROL ((54 * 8) + NV_PREBOOT_PARAM_START)
  94. #define NV_SI_DDR_QV_CONTROL_31_00 ((55 * 8) + NV_PREBOOT_PARAM_START)
  95. #define NV_SI_DDR_QV_CONTROL_63_32 ((56 * 8) + NV_PREBOOT_PARAM_START)
  96. #define NV_SI_DDR_CREDIT_CONTROL ((57 * 8) + NV_PREBOOT_PARAM_START)
  97. #define NV_SI_DDR_WRITE_PRIORITY_CONTROL_31_00 ((58 * 8) + NV_PREBOOT_PARAM_START)
  98. #define NV_SI_DDR_WRITE_PRIORITY_CONTROL_63_32 ((59 * 8) + NV_PREBOOT_PARAM_START)
  99. #define NV_SI_DDR_QUEUE_THRESHOLD_CONTROL_31_00 ((60 * 8) + NV_PREBOOT_PARAM_START)
  100. #define NV_SI_DDR_QUEUE_THRESHOLD_CONTROL_63_32 ((61 * 8) + NV_PREBOOT_PARAM_START)
  101. #define NV_SI_ATF_FAILURE_FAILSAFE ((62 * 8) + NV_PREBOOT_PARAM_START)
  102. #define NV_SI_UEFI_FAILURE_FAILSAFE ((63 * 8) + NV_PREBOOT_PARAM_START)
  103. #define NV_SI_DDR_STRIPE_DECODE ((64 * 8) + NV_PREBOOT_PARAM_START)
  104. #define NV_SI_DDR_DEBUG_CTRL ((65 * 8) + NV_PREBOOT_PARAM_START)
  105. #define NV_SI_CXG_RA_DEVNR_ORD_WFC_DIS ((66 * 8) + NV_PREBOOT_PARAM_START)
  106. #define NV_SI_DDR_PHY_DLL_TRACK_UPD_THRESHOLD ((67 * 8) + NV_PREBOOT_PARAM_START)
  107. #define NV_SI_DDR_PHY_DLL_TRACK_UPD_THRESHOLD_AC ((68 * 8) + NV_PREBOOT_PARAM_START)
  108. #define NV_SI_DDR_PHY_INIT_UPDATE_CONFIG ((69 * 8) + NV_PREBOOT_PARAM_START)
  109. #define NV_SI_DDR_PHY_UPDATE_CONTROL ((70 * 8) + NV_PREBOOT_PARAM_START)
  110. #define NV_SI_PROFILE_EN ((71 * 8) + NV_PREBOOT_PARAM_START)
  111. #define NV_SI_PCIE_PHY_SETTING ((72 * 8) + NV_PREBOOT_PARAM_START)
  112. #define NV_SI_DDR_PHY_CAL_THRESHOLD ((73 * 8) + NV_PREBOOT_PARAM_START)
  113. #define NV_SI_DDR_PHY_CAL_INTERVAL_CNT ((74 * 8) + NV_PREBOOT_PARAM_START)
  114. #define NV_SI_RESERVED ((75 * 8) + NV_PREBOOT_PARAM_START)
  115. #define NV_SI_S0_RHS_RCA_EN ((76 * 8) + NV_PREBOOT_PARAM_START)
  116. #define NV_SI_S1_RHS_RCA_EN ((77 * 8) + NV_PREBOOT_PARAM_START)
  117. #define NV_SI_2P_DPLL ((78 * 8) + NV_PREBOOT_PARAM_START)
  118. #define NV_SI_2P_ALI_CFG ((79 * 8) + NV_PREBOOT_PARAM_START)
  119. #define NV_SI_2P_ALI_CFG_LINK_RETRAIN ((80 * 8) + NV_PREBOOT_PARAM_START)
  120. #define NV_SI_2P_ALI_CFG_CRC ((81 * 8) + NV_PREBOOT_PARAM_START)
  121. #define NV_SI_DDR_RT_CONTROL_31_00 ((82 * 8) + NV_PREBOOT_PARAM_START)
  122. #define NV_SI_DDR_RT_CONTROL_63_32 ((83 * 8) + NV_PREBOOT_PARAM_START)
  123. #define NV_SI_DDR_TIMEOUT_CONTROL ((84 * 8) + NV_PREBOOT_PARAM_START)
  124. #define NV_SI_CPU_LPI_FREQ_DISABLE ((85 * 8) + NV_PREBOOT_PARAM_START)
  125. #define NV_SI_CPU_LPI_FREQ_ENERGY_THRSHLD ((86 * 8) + NV_PREBOOT_PARAM_START)
  126. #define NV_PMPRO_REGION1_LOAD_START (NV_SI_SLC_DISABLE)
  127. #define NV_PMPRO_REGION1_LOAD_END (NV_SI_CPU_LPI_FREQ_ENERGY_THRSHLD)
  128. //
  129. // NOTE: Add before NV_PREBOOT_PARAM_MAX and increase its value
  130. //
  131. #define NV_PREBOOT_PARAM_MAX ((86 * 8) + NV_PREBOOT_PARAM_START)
  132. //
  133. // Manufactory non-volatile memory
  134. //
  135. // These parameters will reset to default value on failsafe.
  136. //
  137. #define NV_MANU_PARAM_START (0x004000)
  138. #define NV_SI_DDR_VMARGIN ((0 * 8) + NV_MANU_PARAM_START)
  139. #define NV_PMPRO_REGION2_LOAD_START (NV_SI_DDR_VMARGIN)
  140. #define NV_SI_SOC_VMARGIN ((1 * 8) + NV_MANU_PARAM_START)
  141. #define NV_SI_AVS_VMARGIN ((2 * 8) + NV_MANU_PARAM_START)
  142. #define NV_SI_TPC_TM1_MARGIN ((3 * 8) + NV_MANU_PARAM_START)
  143. #define NV_SI_TPC_TM2_MARGIN ((4 * 8) + NV_MANU_PARAM_START)
  144. #define NV_SI_TPC_FREQ_THROTTLE ((5 * 8) + NV_MANU_PARAM_START)
  145. #define NV_SI_T_LTLM_EN ((6 * 8) + NV_MANU_PARAM_START)
  146. #define NV_SI_T_LTLM_THRSHLD ((7 * 8) + NV_MANU_PARAM_START)
  147. #define NV_SI_T_GTLM_THRSHLD ((8 * 8) + NV_MANU_PARAM_START)
  148. #define NV_SI_P_LM_EN ((9 * 8) + NV_MANU_PARAM_START)
  149. #define NV_SI_P_LM_THRSHLD ((10 * 8) + NV_MANU_PARAM_START)
  150. #define NV_SI_TPC_OVERTEMP_ISR_DISABLE ((11 * 8) + NV_MANU_PARAM_START)
  151. #define NV_SI_VPP_VMARGIN ((12 * 8) + NV_MANU_PARAM_START)
  152. #define NV_SI_PMPRO_FAILURE_FAILSAFE ((13 * 8) + NV_MANU_PARAM_START)
  153. #define NV_SI_FAILSAFE_DISABLE ((14 * 8) + NV_MANU_PARAM_START)
  154. #define NV_SI_PLIMIT_APM_DS_PERCENTAGE ((15 * 8) + NV_MANU_PARAM_START)
  155. #define NV_SI_PLIMIT_APM_EP_MS ((16 * 8) + NV_MANU_PARAM_START)
  156. #define NV_SI_PLIMIT_APM_PM1_PERCENTAGE_TDP ((17 * 8) + NV_MANU_PARAM_START)
  157. #define NV_SI_CPU_LPI_RESERVED0 ((18 * 8) + NV_MANU_PARAM_START)
  158. #define NV_SI_CPU_LPI_RESERVED1 ((19 * 8) + NV_MANU_PARAM_START)
  159. #define NV_SI_CCIX_OPT_CONFIG ((20 * 8) + NV_MANU_PARAM_START)
  160. #define NV_SI_MESH_FREQ_MARGIN ((21 * 8) + NV_MANU_PARAM_START)
  161. #define NV_SI_MESH_TURBO_EN ((22 * 8) + NV_MANU_PARAM_START)
  162. #define NV_SI_PWR_HEADROOM_WATT ((23 * 8) + NV_MANU_PARAM_START)
  163. #define NV_SI_EXTRA_PCP_VOLT_MV ((24 * 8) + NV_MANU_PARAM_START)
  164. #define NV_SI_CPU_LPI_HYST_CNT ((25 * 8) + NV_MANU_PARAM_START)
  165. #define NV_SI_DVFS_VOLT_INC_STEP_MV ((26 * 8) + NV_MANU_PARAM_START)
  166. #define NV_SI_DVFS_VOLT_DEC_STEP_MV ((27 * 8) + NV_MANU_PARAM_START)
  167. #define NV_SI_PLIMIT_APM_TEMP_THLD ((28 * 8) + NV_MANU_PARAM_START)
  168. #define NV_SI_PLIMIT_APM_EN ((29 * 8) + NV_MANU_PARAM_START)
  169. #define NV_SI_VDM_EN ((30 * 8) + NV_MANU_PARAM_START)
  170. #define NV_SI_VDM_VMARGIN_MV ((31 * 8) + NV_MANU_PARAM_START)
  171. #define NV_SI_PLT_EN ((32 * 8) + NV_MANU_PARAM_START)
  172. #define NV_SI_PLT_SOCKET ((33 * 8) + NV_MANU_PARAM_START)
  173. #define NV_SI_PLT_MCU_MASK ((34 * 8) + NV_MANU_PARAM_START)
  174. #define NV_SI_PLT_RANK_MASK ((35 * 8) + NV_MANU_PARAM_START)
  175. #define NV_SI_PLT_SLICE_MASK ((36 * 8) + NV_MANU_PARAM_START)
  176. #define NV_SI_PLT_BIT_MASK ((37 * 8) + NV_MANU_PARAM_START)
  177. #define NV_SI_PLT_X_PARAM ((38 * 8) + NV_MANU_PARAM_START)
  178. #define NV_SI_PLT_Y_PARAM ((39 * 8) + NV_MANU_PARAM_START)
  179. #define NV_SI_PLT_X_LEFT ((40 * 8) + NV_MANU_PARAM_START)
  180. #define NV_SI_PLT_X_RIGHT ((41 * 8) + NV_MANU_PARAM_START)
  181. #define NV_SI_PLT_X_STEP ((42 * 8) + NV_MANU_PARAM_START)
  182. #define NV_SI_PLT_Y_BOTTOM ((43 * 8) + NV_MANU_PARAM_START)
  183. #define NV_SI_PLT_Y_TOP ((44 * 8) + NV_MANU_PARAM_START)
  184. #define NV_SI_PLT_Y_STEP ((45 * 8) + NV_MANU_PARAM_START)
  185. #define NV_SI_PLT_START_ADDR_LO ((46 * 8) + NV_MANU_PARAM_START)
  186. #define NV_SI_PLT_START_ADDR_UP ((47 * 8) + NV_MANU_PARAM_START)
  187. #define NV_SI_PLT_SIZE ((48 * 8) + NV_MANU_PARAM_START)
  188. #define NV_SI_PLT_THREAD_CNT ((49 * 8) + NV_MANU_PARAM_START)
  189. #define NV_SI_PLT_SCREEN ((50 * 8) + NV_MANU_PARAM_START)
  190. #define NV_SI_PLT_RSVD ((51 * 8) + NV_MANU_PARAM_START)
  191. #define NV_SI_DVFS_VOLT_CHANGE_BY_STEP_EN ((52 * 8) + NV_MANU_PARAM_START)
  192. #define NS_SI_DVFS_TCAL_F_LIMIT ((53 * 8) + NV_MANU_PARAM_START)
  193. #define NS_SI_DVFS_TCAL_T_LIMIT ((54 * 8) + NV_MANU_PARAM_START)
  194. #define NV_SI_CCIX_DIAG_CTRL1 ((55 * 8) + NV_MANU_PARAM_START)
  195. #define NV_SI_CCIX_DIAG_CTRL2 ((56 * 8) + NV_MANU_PARAM_START)
  196. #define NV_SI_DDR_TCAL_EN ((57 * 8) + NV_MANU_PARAM_START)
  197. #define NV_SI_DDR_TCAL_DIMM_LOW_TEMP_THRESHOLD ((58 * 8) + NV_MANU_PARAM_START)
  198. #define NV_SI_DDR_TCAL_DIMM_HIGH_TEMP_THRESHOLD ((59 * 8) + NV_MANU_PARAM_START)
  199. #define NV_SI_DDR_TCAL_MCU_LOW_TEMP_THRESHOLD ((60 * 8) + NV_MANU_PARAM_START)
  200. #define NV_SI_DDR_TCAL_MCU_HIGH_TEMP_THRESHOLD ((61 * 8) + NV_MANU_PARAM_START)
  201. #define NV_SI_DDR_TCAL_LOW_TEMP_VOLT_OFF_MV ((62 * 8) + NV_MANU_PARAM_START)
  202. #define NV_SI_DDR_TCAL_PERIOD_SEC ((63 * 8) + NV_MANU_PARAM_START)
  203. #define NV_SI_DDR_TCAL_SOC_VOLT_CAP_MV ((64 * 8) + NV_MANU_PARAM_START)
  204. #define NV_SI_ALTRAMAX_ICCMAX_EN ((65 * 8) + NV_MANU_PARAM_START)
  205. #define NV_SI_MESH_TURBO_ACTIVITY_THRESHOLD ((66 * 8) + NV_MANU_PARAM_START)
  206. #define NV_PMPRO_REGION2_LOAD_END (NV_SI_MESH_TURBO_ACTIVITY_THRESHOLD)
  207. //
  208. // NOTE: Add before NV_MANU_PARAM_MAX and increase its value
  209. //
  210. #define NV_MANU_PARAM_MAX ((66 * 8) + NV_MANU_PARAM_START)
  211. //
  212. // User non-volatile memory
  213. //
  214. // These parameters will reset to default value on failsafe.
  215. //
  216. #define NV_USER_PARAM_START (0x008000)
  217. #define NV_SI_S0_PCP_ACTIVECPM_0_31 ((0 * 8) + NV_USER_PARAM_START)
  218. #define NV_SI_S0_PCP_ACTIVECPM_32_63 ((1 * 8) + NV_USER_PARAM_START)
  219. #define NV_SI_S1_PCP_ACTIVECPM_0_31 ((2 * 8) + NV_USER_PARAM_START)
  220. #define NV_SI_S1_PCP_ACTIVECPM_32_63 ((3 * 8) + NV_USER_PARAM_START)
  221. #define NV_SI_WDT_BIOS_EXP_MINS ((4 * 8) + NV_USER_PARAM_START)
  222. #define NV_SI_DDR_CE_RAS_THRESHOLD ((5 * 8) + NV_USER_PARAM_START)
  223. #define NV_SI_DDR_CE_RAS_INTERVAL ((6 * 8) + NV_USER_PARAM_START)
  224. #define NV_SI_DDR_SPEED ((7 * 8) + NV_USER_PARAM_START)
  225. #define NV_SI_DDR_SCRUB_EN ((8 * 8) + NV_USER_PARAM_START)
  226. #define NV_SI_DDR_ECC_MODE ((9 * 8) + NV_USER_PARAM_START)
  227. #define NV_SI_S0_RCA_PCI_DEVMAP ((10 * 8) + NV_USER_PARAM_START)
  228. #define NV_SI_S0_RCB_PCI_DEVMAP ((11 * 8) + NV_USER_PARAM_START)
  229. #define NV_SI_S1_RCA_PCI_DEVMAP ((12 * 8) + NV_USER_PARAM_START)
  230. #define NV_SI_S1_RCB_PCI_DEVMAP ((13 * 8) + NV_USER_PARAM_START)
  231. #define NV_SI_DDR_ERRCTRL ((14 * 8) + NV_USER_PARAM_START)
  232. #define NV_SI_DDR_REFRESH_GRANULARITY ((15 * 8) + NV_USER_PARAM_START)
  233. #define NV_SI_SUBNUMA_MODE ((16 * 8) + NV_USER_PARAM_START)
  234. #define NV_SI_ERRATUM_1542419_WA ((17 * 8) + NV_USER_PARAM_START)
  235. #define NV_SI_NEAR_ATOMIC_DISABLE ((18 * 8) + NV_USER_PARAM_START)
  236. #define NV_SI_DDR_SLAVE_32BIT_MEM_EN ((19 * 8) + NV_USER_PARAM_START)
  237. #define NV_SI_CPUECTLR_EL1_0_31 ((20 * 8) + NV_USER_PARAM_START)
  238. #define NV_SI_CPUECTLR_EL1_32_63 ((21 * 8) + NV_USER_PARAM_START)
  239. #define NV_SI_HARDWARE_EINJ ((22 * 8) + NV_USER_PARAM_START)
  240. #define NV_SI_2P_CE_RAS_THRESHOLD ((23 * 8) + NV_USER_PARAM_START)
  241. #define NV_SI_2P_CE_RAS_INTERVAL ((24 * 8) + NV_USER_PARAM_START)
  242. #define NV_SI_RAS_BERT_ENABLED ((25 * 8) + NV_USER_PARAM_START)
  243. #define NV_SI_HNF_AUX_CTL_0_31 ((26 * 8) + NV_USER_PARAM_START)
  244. #define NV_SI_HNF_AUX_CTL_32_63 ((27 * 8) + NV_USER_PARAM_START)
  245. #define NV_SI_CPM_CE_RAS_THRESHOLD ((28 * 8) + NV_USER_PARAM_START)
  246. #define NV_SI_CPM_CE_RAS_INTERVAL ((29 * 8) + NV_USER_PARAM_START)
  247. #define NV_SI_HNF_AUX_CTL_0_31_WR_EN_MASK ((30 * 8) + NV_USER_PARAM_START)
  248. #define NV_SI_HNF_AUX_CTL_32_63_WR_EN_MASK ((31 * 8) + NV_USER_PARAM_START)
  249. #define NV_SI_DDR_WR_BACK_EN ((32 * 8) + NV_USER_PARAM_START)
  250. #define NV_SI_CPUECTLR_EL1_0_31_WR_EN_MASK ((33 * 8) + NV_USER_PARAM_START)
  251. #define NV_SI_CPUECTLR_EL1_32_63_WR_EN_MASK ((34 * 8) + NV_USER_PARAM_START)
  252. #define NV_SI_LINK_ERR_THRESHOLD ((35 * 8) + NV_USER_PARAM_START)
  253. #define NV_SI_SEC_WDT_BIOS_EXP_MINS ((36 * 8) + NV_USER_PARAM_START)
  254. #define NV_SI_NVDIMM_MODE ((37 * 8) + NV_USER_PARAM_START)
  255. #define NV_SI_RAS_SDEI_ENABLED ((38 * 8) + NV_USER_PARAM_START)
  256. #define NV_SI_NVDIMM_PROV_MASK_S0 ((39 * 8) + NV_USER_PARAM_START)
  257. #define NV_SI_NVDIMM_PROV_MASK_S1 ((40 * 8) + NV_USER_PARAM_START)
  258. #define NV_SI_DDR_ZQCS_EN ((41 * 8) + NV_USER_PARAM_START)
  259. #define NV_SI_DDR_CRC_MODE ((42 * 8) + NV_USER_PARAM_START)
  260. #define NV_SI_CXG_RA_AUX_CTL_0_31 ((43 * 8) + NV_USER_PARAM_START)
  261. #define NV_SI_CXG_RA_AUX_CTL_32_63 ((44 * 8) + NV_USER_PARAM_START)
  262. #define NV_SI_CXG_RA_AUX_CTL_0_31_WR_EN_MASK ((45 * 8) + NV_USER_PARAM_START)
  263. #define NV_SI_CXG_RA_AUX_CTL_32_63_WR_EN_MASK ((46 * 8) + NV_USER_PARAM_START)
  264. #define NV_SI_CXLA_AUX_CTL_0_31 ((47 * 8) + NV_USER_PARAM_START)
  265. #define NV_SI_CXLA_AUX_CTL_32_63 ((48 * 8) + NV_USER_PARAM_START)
  266. #define NV_SI_CXLA_AUX_CTL_0_31_WR_EN_MASK ((49 * 8) + NV_USER_PARAM_START)
  267. #define NV_SI_CXLA_AUX_CTL_32_63_WR_EN_MASK ((50 * 8) + NV_USER_PARAM_START)
  268. #define NV_SI_DDR_LOW_POWER_CFG ((51 * 8) + NV_USER_PARAM_START)
  269. #define NV_SI_ALERT_DIMM_SHUTDOWN_EN ((52 * 8) + NV_USER_PARAM_START)
  270. #define NV_SI_DFS_EN ((53 * 8) + NV_USER_PARAM_START)
  271. #define NV_SI_RAS_PCIE_AER_FW_FIRST ((54 * 8) + NV_USER_PARAM_START)
  272. #define NV_SI_RAS_DRAM_EINJ_NOTRIGGER ((55 * 8) + NV_USER_PARAM_START)
  273. #define NV_SI_RAS_AEST_PROC_EN ((56 * 8) + NV_USER_PARAM_START)
  274. #define NV_SI_MESH_S0_CXG_RC_STRONG_ORDERING_EN ((57 * 8) + NV_USER_PARAM_START)
  275. #define NV_SI_MESH_S1_CXG_RC_STRONG_ORDERING_EN ((58 * 8) + NV_USER_PARAM_START)
  276. #define NV_SI_2P_RESERVED0 ((59 * 8) + NV_USER_PARAM_START)
  277. #define NV_SI_2P_RESERVED1 ((60 * 8) + NV_USER_PARAM_START)
  278. #define NV_SI_2P_RESERVED2 ((61 * 8) + NV_USER_PARAM_START)
  279. #define NV_SI_HCR_EL2_CTL_LOW ((62 * 8) + NV_USER_PARAM_START)
  280. #define NV_SI_HCR_EL2_CTL_HIGH ((63 * 8) + NV_USER_PARAM_START)
  281. #define NV_SI_ESM_SPEED ((64 * 8) + NV_USER_PARAM_START)
  282. //
  283. // NOTE: Add before NV_USER_PARAM_MAX and increase its value
  284. //
  285. #define NV_USER_PARAM_MAX ((64 * 8) + NV_USER_PARAM_START)
  286. #define NV_PMPRO_REGION3_LOAD_START (NV_USER_PARAM_START)
  287. #define NV_PMPRO_REGION3_LOAD_END (NV_USER_PARAM_MAX)
  288. //
  289. // Non-volatile board read-only setting
  290. //
  291. // These parameters do not support failsafe and will always read
  292. // from its location. Please note that the physical base address
  293. // location for board setting is not the same as above region. This
  294. // allows packaging these board setting along with the firmware
  295. // image itself. See SPI-NOR flash layout design for more info.
  296. //
  297. // Please note that script will parse these and generate
  298. // board setting. The keyword "Default: " is used to provide
  299. // the default value.
  300. //
  301. #define NV_BOARD_PARAM_START (0x00C000)
  302. #define NV_SI_RO_BOARD_VENDOR ((0 * 8) + NV_BOARD_PARAM_START) /* Default: 0x0000CD3A - Follow BMC FRU format */
  303. #define NV_PMPRO_REGION4_LOAD_START (NV_SI_RO_BOARD_VENDOR)
  304. #define NV_SI_RO_BOARD_TYPE ((1 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 - Follow BMC FRU format */
  305. #define NV_SI_RO_BOARD_REV ((2 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 Follow BMC FRU format */
  306. #define NV_SI_RO_BOARD_CFG ((3 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 Follow BMC FRU format */
  307. #define NV_SI_RO_BOARD_S0_DIMM_AVAIL ((4 * 8) + NV_BOARD_PARAM_START) /* Default: 0x0000FFFF */
  308. #define NV_SI_RO_BOARD_S1_DIMM_AVAIL ((5 * 8) + NV_BOARD_PARAM_START) /* Default: 0x0000FFFF */
  309. #define NV_SI_RO_BOARD_SPI0CS0_FREQ_KHZ ((6 * 8) + NV_BOARD_PARAM_START) /* Default: 33000 */
  310. #define NV_SI_RO_BOARD_SPI0CS1_FREQ_KHZ ((7 * 8) + NV_BOARD_PARAM_START) /* Default: 33000 */
  311. #define NV_SI_RO_BOARD_SPI1CS0_FREQ_KHZ ((8 * 8) + NV_BOARD_PARAM_START) /* Default: 10000 */
  312. #define NV_SI_RO_BOARD_SPI1CS1_FREQ_KHZ ((9 * 8) + NV_BOARD_PARAM_START) /* Default: 10000 */
  313. #define NV_SI_RO_BOARD_TPM_LOC ((10 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 */
  314. #define NV_SI_RO_BOARD_I2C0_FREQ_KHZ ((11 * 8) + NV_BOARD_PARAM_START) /* Default: 400 */
  315. #define NV_SI_RO_BOARD_I2C1_FREQ_KHZ ((12 * 8) + NV_BOARD_PARAM_START) /* Default: 400 */
  316. #define NV_SI_RO_BOARD_I2C2_10_FREQ_KHZ ((13 * 8) + NV_BOARD_PARAM_START) /* Default: 400 */
  317. #define NV_SI_RO_BOARD_I2C3_FREQ_KHZ ((14 * 8) + NV_BOARD_PARAM_START) /* Default: 400 */
  318. #define NV_SI_RO_BOARD_I2C9_FREQ_KHZ ((15 * 8) + NV_BOARD_PARAM_START) /* Default: 400 */
  319. #define NV_SI_RO_BOARD_2P_CFG ((16 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFF01 */
  320. #define NV_SI_RO_BOARD_S0_RCA0_CFG ((17 * 8) + NV_BOARD_PARAM_START)
  321. #define NV_SI_RO_BOARD_S0_RCA1_CFG ((18 * 8) + NV_BOARD_PARAM_START)
  322. #define NV_SI_RO_BOARD_S0_RCA2_CFG ((19 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000004 */
  323. #define NV_SI_RO_BOARD_S0_RCA3_CFG ((20 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000004 */
  324. #define NV_SI_RO_BOARD_S0_RCB0_LO_CFG ((21 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
  325. #define NV_SI_RO_BOARD_S0_RCB0_HI_CFG ((22 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
  326. #define NV_SI_RO_BOARD_S0_RCB1_LO_CFG ((23 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
  327. #define NV_SI_RO_BOARD_S0_RCB1_HI_CFG ((24 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
  328. #define NV_SI_RO_BOARD_S0_RCB2_LO_CFG ((25 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
  329. #define NV_SI_RO_BOARD_S0_RCB2_HI_CFG ((26 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000003 */
  330. #define NV_SI_RO_BOARD_S0_RCB3_LO_CFG ((27 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000003 */
  331. #define NV_SI_RO_BOARD_S0_RCB3_HI_CFG ((28 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
  332. #define NV_SI_RO_BOARD_S1_RCA0_CFG ((29 * 8) + NV_BOARD_PARAM_START)
  333. #define NV_SI_RO_BOARD_S1_RCA1_CFG ((30 * 8) + NV_BOARD_PARAM_START)
  334. #define NV_SI_RO_BOARD_S1_RCA2_CFG ((31 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02020202 */
  335. #define NV_SI_RO_BOARD_S1_RCA3_CFG ((32 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00030003 */
  336. #define NV_SI_RO_BOARD_S1_RCB0_LO_CFG ((33 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000003 */
  337. #define NV_SI_RO_BOARD_S1_RCB0_HI_CFG ((34 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
  338. #define NV_SI_RO_BOARD_S1_RCB1_LO_CFG ((35 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
  339. #define NV_SI_RO_BOARD_S1_RCB1_HI_CFG ((36 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000003 */
  340. #define NV_SI_RO_BOARD_S1_RCB2_LO_CFG ((37 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
  341. #define NV_SI_RO_BOARD_S1_RCB2_HI_CFG ((38 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
  342. #define NV_SI_RO_BOARD_S1_RCB3_LO_CFG ((39 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
  343. #define NV_SI_RO_BOARD_S1_RCB3_HI_CFG ((40 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00020002 */
  344. #define NV_SI_RO_BOARD_T_LTLM_DELTA_P0 ((41 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000001 */
  345. #define NV_SI_RO_BOARD_T_LTLM_DELTA_P1 ((42 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000002 */
  346. #define NV_SI_RO_BOARD_T_LTLM_DELTA_P2 ((43 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000003 */
  347. #define NV_SI_RO_BOARD_T_LTLM_DELTA_P3 ((44 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000004 */
  348. #define NV_SI_RO_BOARD_T_LTLM_DELTA_M1 ((45 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFF */
  349. #define NV_SI_RO_BOARD_T_LTLM_DELTA_M2 ((46 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFE */
  350. #define NV_SI_RO_BOARD_T_LTLM_DELTA_M3 ((47 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFD */
  351. #define NV_SI_RO_BOARD_P_LM_PID_P ((48 * 8) + NV_BOARD_PARAM_START)
  352. #define NV_SI_RO_BOARD_P_LM_PID_I ((49 * 8) + NV_BOARD_PARAM_START)
  353. #define NV_SI_RO_BOARD_P_LM_PID_I_L_THOLD ((50 * 8) + NV_BOARD_PARAM_START)
  354. #define NV_SI_RO_BOARD_P_LM_PID_I_H_THOLD ((51 * 8) + NV_BOARD_PARAM_START)
  355. #define NV_SI_RO_BOARD_P_LM_PID_D ((52 * 8) + NV_BOARD_PARAM_START)
  356. #define NV_SI_RO_BOARD_P_LM_EXP_SMOOTH_CONST ((53 * 8) + NV_BOARD_PARAM_START)
  357. //
  358. // NV_SI_RO_BOARD_TPM_ALG_ID: 0=Default to SHA256, 1=SHA1, 2=SHA256
  359. // Any other value will lead to default digest.
  360. //
  361. #define NV_SI_RO_BOARD_TPM_ALG_ID ((54 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000002 */
  362. #define NV_SI_RO_BOARD_DDR_SPEED_GRADE ((55 * 8) + NV_BOARD_PARAM_START) /* Default: 3200 */
  363. #define NV_SI_RO_BOARD_DDR_S0_RTT_WR ((56 * 8) + NV_BOARD_PARAM_START) /* Default: 0x20020000 */
  364. #define NV_SI_RO_BOARD_DDR_S1_RTT_WR ((57 * 8) + NV_BOARD_PARAM_START) /* Default: 0x20020000 */
  365. #define NV_SI_RO_BOARD_DDR_S0_RTT_NOM ((58 * 8) + NV_BOARD_PARAM_START) /* Default: 0x31060177 */
  366. #define NV_SI_RO_BOARD_DDR_S1_RTT_NOM ((59 * 8) + NV_BOARD_PARAM_START) /* Default: 0x31060177 */
  367. #define NV_SI_RO_BOARD_DDR_S0_RTT_PARK ((60 * 8) + NV_BOARD_PARAM_START) /* Default: 0x30060070 */
  368. #define NV_SI_RO_BOARD_DDR_S1_RTT_PARK ((61 * 8) + NV_BOARD_PARAM_START) /* Default: 0x30060070 */
  369. #define NV_SI_RO_BOARD_DDR_CS0_RDODT_MASK_1DPC ((62 * 8) + NV_BOARD_PARAM_START) /* Default: 0x000000 */
  370. #define NV_SI_RO_BOARD_DDR_CS1_RDODT_MASK_1DPC ((63 * 8) + NV_BOARD_PARAM_START) /* Default: 0x000000 */
  371. #define NV_SI_RO_BOARD_DDR_CS2_RDODT_MASK_1DPC ((64 * 8) + NV_BOARD_PARAM_START) /* Default: 0x000000 */
  372. #define NV_SI_RO_BOARD_DDR_CS3_RDODT_MASK_1DPC ((65 * 8) + NV_BOARD_PARAM_START) /* Default: 0x000000 */
  373. #define NV_SI_RO_BOARD_DDR_CS0_RDODT_MASK_2DPC ((66 * 8) + NV_BOARD_PARAM_START) /* Default: 0x044C0CCC */
  374. #define NV_SI_RO_BOARD_DDR_CS1_RDODT_MASK_2DPC ((67 * 8) + NV_BOARD_PARAM_START) /* Default: 0x084C0CCC */
  375. #define NV_SI_RO_BOARD_DDR_CS2_RDODT_MASK_2DPC ((68 * 8) + NV_BOARD_PARAM_START) /* Default: 0x04130333 */
  376. #define NV_SI_RO_BOARD_DDR_CS3_RDODT_MASK_2DPC ((69 * 8) + NV_BOARD_PARAM_START) /* Default: 0x08130333 */
  377. #define NV_SI_RO_BOARD_DDR_CS0_WRODT_MASK_1DPC ((70 * 8) + NV_BOARD_PARAM_START) /* Default: 0x01130333 */
  378. #define NV_SI_RO_BOARD_DDR_CS1_WRODT_MASK_1DPC ((71 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02230333 */
  379. #define NV_SI_RO_BOARD_DDR_CS2_WRODT_MASK_1DPC ((72 * 8) + NV_BOARD_PARAM_START) /* Default: 0x01430333 */
  380. #define NV_SI_RO_BOARD_DDR_CS3_WRODT_MASK_1DPC ((73 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02830333 */
  381. #define NV_SI_RO_BOARD_DDR_CS0_WRODT_MASK_2DPC ((74 * 8) + NV_BOARD_PARAM_START) /* Default: 0x055EDEED */
  382. #define NV_SI_RO_BOARD_DDR_CS1_WRODT_MASK_2DPC ((75 * 8) + NV_BOARD_PARAM_START) /* Default: 0x0A5DEDDE */
  383. #define NV_SI_RO_BOARD_DDR_CS2_WRODT_MASK_2DPC ((76 * 8) + NV_BOARD_PARAM_START) /* Default: 0x055B7BB7 */
  384. #define NV_SI_RO_BOARD_DDR_CS3_WRODT_MASK_2DPC ((77 * 8) + NV_BOARD_PARAM_START) /* Default: 0x0A57B77B */
  385. #define NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_CTRL_1DPC ((78 * 8) + NV_BOARD_PARAM_START) /* Default: 0x5 */
  386. #define NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_VAL_1DPC ((79 * 8) + NV_BOARD_PARAM_START) /* Default: 0x90DD90 */
  387. #define NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_CTRL_1DPC ((80 * 8) + NV_BOARD_PARAM_START) /* Default: 0x5 */
  388. #define NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_VAL_1DPC ((81 * 8) + NV_BOARD_PARAM_START) /* Default: 0x90DD90 */
  389. #define NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_CTRL_2DPC ((82 * 8) + NV_BOARD_PARAM_START) /* Default: 0x5 */
  390. #define NV_SI_RO_BOARD_DDR_PHY_TERM_DQ_VAL_2DPC ((83 * 8) + NV_BOARD_PARAM_START) /* Default: 0x90DD90 */
  391. #define NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_CTRL_2DPC ((84 * 8) + NV_BOARD_PARAM_START) /* Default: 0x5 */
  392. #define NV_SI_RO_BOARD_DDR_PHY_TERM_DQS_VAL_2DPC ((85 * 8) + NV_BOARD_PARAM_START) /* Default: 0x90DD90 */
  393. #define NV_SI_RO_BOARD_DDR_PHY_VREFDQ_RANGE_VAL_1DPC ((86 * 8) + NV_BOARD_PARAM_START) /* Default: 0x24 */
  394. #define NV_SI_RO_BOARD_DDR_DRAM_VREFDQ_RANGE_VAL_1DPC ((87 * 8) + NV_BOARD_PARAM_START) /* Default: 0x001A001A */
  395. #define NV_SI_RO_BOARD_DDR_PHY_VREFDQ_RANGE_VAL_2DPC ((88 * 8) + NV_BOARD_PARAM_START) /* Default: 0x50 */
  396. #define NV_SI_RO_BOARD_DDR_DRAM_VREFDQ_RANGE_VAL_2DPC ((89 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00240020 */
  397. #define NV_SI_RO_BOARD_DDR_CLK_WRDQ_DLY_DEFAULT ((90 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02800280 */
  398. #define NV_SI_RO_BOARD_DDR_RDDQS_DQ_DLY_DEFAULT ((91 * 8) + NV_BOARD_PARAM_START) /* Default: 0x90909090 */
  399. #define NV_SI_RO_BOARD_DDR_WRDQS_SHIFT_DEFAULT ((92 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 */
  400. #define NV_SI_RO_BOARD_DDR_ADCMD_DLY_DEFAULT ((93 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00C000C0 */
  401. #define NV_SI_RO_BOARD_DDR_CLK_WRDQ_DLY_ADJ ((94 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 */
  402. #define NV_SI_RO_BOARD_DDR_RDDQS_DQ_DLY_ADJ ((95 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 */
  403. #define NV_SI_RO_BOARD_DDR_PHY_VREF_ADJ ((96 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 */
  404. #define NV_SI_RO_BOARD_DDR_DRAM_VREF_ADJ ((97 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 */
  405. #define NV_SI_RO_BOARD_DDR_WR_PREAMBLE_CYCLE ((98 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02010201 */
  406. #define NV_SI_RO_BOARD_DDR_ADCMD_2T_MODE ((99 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 */
  407. #define NV_SI_RO_BOARD_I2C_VRD_CONFIG_INFO ((100 * 8) + NV_BOARD_PARAM_START)
  408. #define NV_SI_RO_BOARD_DDR_PHY_FEATURE_CTRL ((101 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 */
  409. #define NV_SI_RO_BOARD_BMC_HANDSHAKE_SPI_ACCESS ((102 * 8) + NV_BOARD_PARAM_START) /* Default: 0x01050106 */
  410. #define NV_SI_RO_BOARD_DIMM_TEMP_THRESHOLD ((103 * 8) + NV_BOARD_PARAM_START) /* Default: 0x5F4 */
  411. #define NV_SI_RO_BOARD_DIMM_SPD_COMPARE_DISABLE ((104 * 8) + NV_BOARD_PARAM_START) /* Default: 0x0 */
  412. #define NV_SI_RO_BOARD_S0_PCIE_CLK_CFG ((105 * 8) + NV_BOARD_PARAM_START)
  413. #define NV_SI_RO_BOARD_S0_RCA4_CFG ((106 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02020202 */
  414. #define NV_SI_RO_BOARD_S0_RCA5_CFG ((107 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02020202 */
  415. #define NV_SI_RO_BOARD_S0_RCA6_CFG ((108 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02020202 */
  416. #define NV_SI_RO_BOARD_S0_RCA7_CFG ((109 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02020003 */
  417. #define NV_SI_RO_BOARD_S0_RCA0_TXRX_G3PRESET ((110 * 8) + NV_BOARD_PARAM_START)
  418. #define NV_SI_RO_BOARD_S0_RCA1_TXRX_G3PRESET ((111 * 8) + NV_BOARD_PARAM_START)
  419. #define NV_SI_RO_BOARD_S0_RCA2_TXRX_G3PRESET ((112 * 8) + NV_BOARD_PARAM_START)
  420. #define NV_SI_RO_BOARD_S0_RCA3_TXRX_G3PRESET ((113 * 8) + NV_BOARD_PARAM_START)
  421. #define NV_SI_RO_BOARD_S0_RCB0A_TXRX_G3PRESET ((114 * 8) + NV_BOARD_PARAM_START)
  422. #define NV_SI_RO_BOARD_S0_RCB0B_TXRX_G3PRESET ((115 * 8) + NV_BOARD_PARAM_START)
  423. #define NV_SI_RO_BOARD_S0_RCB1A_TXRX_G3PRESET ((116 * 8) + NV_BOARD_PARAM_START)
  424. #define NV_SI_RO_BOARD_S0_RCB1B_TXRX_G3PRESET ((117 * 8) + NV_BOARD_PARAM_START)
  425. #define NV_SI_RO_BOARD_S0_RCB2A_TXRX_G3PRESET ((118 * 8) + NV_BOARD_PARAM_START)
  426. #define NV_SI_RO_BOARD_S0_RCB2B_TXRX_G3PRESET ((119 * 8) + NV_BOARD_PARAM_START)
  427. #define NV_SI_RO_BOARD_S0_RCB3A_TXRX_G3PRESET ((120 * 8) + NV_BOARD_PARAM_START)
  428. #define NV_SI_RO_BOARD_S0_RCB3B_TXRX_G3PRESET ((121 * 8) + NV_BOARD_PARAM_START)
  429. #define NV_SI_RO_BOARD_S0_RCA4_TXRX_G3PRESET ((122 * 8) + NV_BOARD_PARAM_START)
  430. #define NV_SI_RO_BOARD_S0_RCA5_TXRX_G3PRESET ((123 * 8) + NV_BOARD_PARAM_START)
  431. #define NV_SI_RO_BOARD_S0_RCA6_TXRX_G3PRESET ((124 * 8) + NV_BOARD_PARAM_START)
  432. #define NV_SI_RO_BOARD_S0_RCA7_TXRX_G3PRESET ((125 * 8) + NV_BOARD_PARAM_START)
  433. #define NV_SI_RO_BOARD_S0_RCA0_TXRX_G4PRESET ((126 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  434. #define NV_SI_RO_BOARD_S0_RCA1_TXRX_G4PRESET ((127 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  435. #define NV_SI_RO_BOARD_S0_RCA2_TXRX_G4PRESET ((128 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  436. #define NV_SI_RO_BOARD_S0_RCA3_TXRX_G4PRESET ((129 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  437. #define NV_SI_RO_BOARD_S0_RCB0A_TXRX_G4PRESET ((130 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  438. #define NV_SI_RO_BOARD_S0_RCB0B_TXRX_G4PRESET ((131 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  439. #define NV_SI_RO_BOARD_S0_RCB1A_TXRX_G4PRESET ((132 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  440. #define NV_SI_RO_BOARD_S0_RCB1B_TXRX_G4PRESET ((133 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  441. #define NV_SI_RO_BOARD_S0_RCB2A_TXRX_G4PRESET ((134 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  442. #define NV_SI_RO_BOARD_S0_RCB2B_TXRX_G4PRESET ((135 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  443. #define NV_SI_RO_BOARD_S0_RCB3A_TXRX_G4PRESET ((136 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  444. #define NV_SI_RO_BOARD_S0_RCB3B_TXRX_G4PRESET ((137 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  445. #define NV_SI_RO_BOARD_S0_RCA4_TXRX_G4PRESET ((138 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  446. #define NV_SI_RO_BOARD_S0_RCA5_TXRX_G4PRESET ((139 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  447. #define NV_SI_RO_BOARD_S0_RCA6_TXRX_G4PRESET ((140 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  448. #define NV_SI_RO_BOARD_S0_RCA7_TXRX_G4PRESET ((141 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  449. #define NV_SI_RO_BOARD_S1_PCIE_CLK_CFG ((142 * 8) + NV_BOARD_PARAM_START)
  450. #define NV_SI_RO_BOARD_S1_RCA4_CFG ((143 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02020202 */
  451. #define NV_SI_RO_BOARD_S1_RCA5_CFG ((144 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02020202 */
  452. #define NV_SI_RO_BOARD_S1_RCA6_CFG ((145 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02020202 */
  453. #define NV_SI_RO_BOARD_S1_RCA7_CFG ((146 * 8) + NV_BOARD_PARAM_START) /* Default: 0x02020003 */
  454. #define NV_SI_RO_BOARD_S1_RCA2_TXRX_G3PRESET ((147 * 8) + NV_BOARD_PARAM_START)
  455. #define NV_SI_RO_BOARD_S1_RCA3_TXRX_G3PRESET ((148 * 8) + NV_BOARD_PARAM_START)
  456. #define NV_SI_RO_BOARD_S1_RCB0A_TXRX_G3PRESET ((149 * 8) + NV_BOARD_PARAM_START)
  457. #define NV_SI_RO_BOARD_S1_RCB0B_TXRX_G3PRESET ((150 * 8) + NV_BOARD_PARAM_START)
  458. #define NV_SI_RO_BOARD_S1_RCB1A_TXRX_G3PRESET ((151 * 8) + NV_BOARD_PARAM_START)
  459. #define NV_SI_RO_BOARD_S1_RCB1B_TXRX_G3PRESET ((152 * 8) + NV_BOARD_PARAM_START)
  460. #define NV_SI_RO_BOARD_S1_RCB2A_TXRX_G3PRESET ((153 * 8) + NV_BOARD_PARAM_START)
  461. #define NV_SI_RO_BOARD_S1_RCB2B_TXRX_G3PRESET ((154 * 8) + NV_BOARD_PARAM_START)
  462. #define NV_SI_RO_BOARD_S1_RCB3A_TXRX_G3PRESET ((155 * 8) + NV_BOARD_PARAM_START)
  463. #define NV_SI_RO_BOARD_S1_RCB3B_TXRX_G3PRESET ((156 * 8) + NV_BOARD_PARAM_START)
  464. #define NV_SI_RO_BOARD_S1_RCA4_TXRX_G3PRESET ((157 * 8) + NV_BOARD_PARAM_START)
  465. #define NV_SI_RO_BOARD_S1_RCA5_TXRX_G3PRESET ((158 * 8) + NV_BOARD_PARAM_START)
  466. #define NV_SI_RO_BOARD_S1_RCA6_TXRX_G3PRESET ((159 * 8) + NV_BOARD_PARAM_START)
  467. #define NV_SI_RO_BOARD_S1_RCA7_TXRX_G3PRESET ((160 * 8) + NV_BOARD_PARAM_START)
  468. #define NV_SI_RO_BOARD_S1_RCA2_TXRX_G4PRESET ((161 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  469. #define NV_SI_RO_BOARD_S1_RCA3_TXRX_G4PRESET ((162 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  470. #define NV_SI_RO_BOARD_S1_RCB0A_TXRX_G4PRESET ((163 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  471. #define NV_SI_RO_BOARD_S1_RCB0B_TXRX_G4PRESET ((164 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  472. #define NV_SI_RO_BOARD_S1_RCB1A_TXRX_G4PRESET ((165 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  473. #define NV_SI_RO_BOARD_S1_RCB1B_TXRX_G4PRESET ((166 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  474. #define NV_SI_RO_BOARD_S1_RCB2A_TXRX_G4PRESET ((167 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  475. #define NV_SI_RO_BOARD_S1_RCB2B_TXRX_G4PRESET ((168 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  476. #define NV_SI_RO_BOARD_S1_RCB3A_TXRX_G4PRESET ((169 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  477. #define NV_SI_RO_BOARD_S1_RCB3B_TXRX_G4PRESET ((170 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  478. #define NV_SI_RO_BOARD_S1_RCA4_TXRX_G4PRESET ((171 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  479. #define NV_SI_RO_BOARD_S1_RCA5_TXRX_G4PRESET ((172 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  480. #define NV_SI_RO_BOARD_S1_RCA6_TXRX_G4PRESET ((173 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  481. #define NV_SI_RO_BOARD_S1_RCA7_TXRX_G4PRESET ((174 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  482. #define NV_SI_RO_BOARD_2P_CE_MASK_THRESHOLD ((175 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000003 */
  483. #define NV_SI_RO_BOARD_2P_CE_MASK_INTERVAL ((176 * 8) + NV_BOARD_PARAM_START) /* Default: 0x000001A4 */
  484. #define NV_SI_RO_BOARD_SX_PHY_CFG_SETTING ((177 * 8) + NV_BOARD_PARAM_START)
  485. #define NV_SI_RO_BOARD_DDR_PHY_DC_CLK ((178 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00018000 */
  486. #define NV_SI_RO_BOARD_DDR_PHY_DC_DATA ((179 * 8) + NV_BOARD_PARAM_START) /* Default: 0x80018000 */
  487. #define NV_SI_RO_BOARD_SX_RCA0_TXRX_20GPRESET ((180 * 8) + NV_BOARD_PARAM_START)
  488. #define NV_SI_RO_BOARD_SX_RCA1_TXRX_20GPRESET ((181 * 8) + NV_BOARD_PARAM_START)
  489. #define NV_SI_RO_BOARD_SX_RCA2_TXRX_20GPRESET ((182 * 8) + NV_BOARD_PARAM_START)
  490. #define NV_SI_RO_BOARD_SX_RCA3_TXRX_20GPRESET ((183 * 8) + NV_BOARD_PARAM_START)
  491. #define NV_SI_RO_BOARD_SX_RCA0_TXRX_25GPRESET ((184 * 8) + NV_BOARD_PARAM_START)
  492. #define NV_SI_RO_BOARD_SX_RCA1_TXRX_25GPRESET ((185 * 8) + NV_BOARD_PARAM_START)
  493. #define NV_SI_RO_BOARD_SX_RCA2_TXRX_25GPRESET ((186 * 8) + NV_BOARD_PARAM_START)
  494. #define NV_SI_RO_BOARD_SX_RCA3_TXRX_25GPRESET ((187 * 8) + NV_BOARD_PARAM_START)
  495. #define NV_SI_RO_BOARD_DDR_2X_REFRESH_TEMP_THRESHOLD ((188 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00550055 */
  496. #define NV_SI_RO_BOARD_PCP_VRD_VOUT_WAIT_US ((189 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000064 */
  497. #define NV_SI_RO_BOARD_PCP_VRD_VOUT_RESOLUTION_MV ((190 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000005 */
  498. #define NV_SI_RO_BOARD_DVFS_VOLT_READ_BACK_EN ((191 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000001 */
  499. #define NV_SI_RO_BOARD_DVFS_VOLT_READ_BACK_TIME ((192 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000002 */
  500. #define NV_SI_RO_BOARD_DVFS_VOUT_20MV_RAMP_TIME_US ((193 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000005 */
  501. #define NV_SI_RO_BOARD_PCIE_AER_FW_FIRST ((194 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 */
  502. #define NV_SI_RO_BOARD_RTC_GPI_LOCK_BYPASS ((195 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 */
  503. #define NV_SI_RO_BOARD_TPM_DISABLE ((196 * 8) + NV_BOARD_PARAM_START)
  504. #define NV_SI_RO_BOARD_MESH_S0_CXG_RC_STRONG_ORDERING_EN ((197 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 */
  505. #define NV_SI_RO_BOARD_MESH_S1_CXG_RC_STRONG_ORDERING_EN ((198 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 */
  506. #define NV_SI_RO_BOARD_GPIO_SW_WATCHDOG_EN ((199 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 */
  507. #define NV_SI_RO_BOARD_PCIE_HP_DISABLE ((200 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 */
  508. #define NV_SI_RO_BOARD_I2C_VRD_VOUT_FORMAT ((201 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 */
  509. #define NV_SI_RO_BOARD_I2C_VRD_SMBUS_CMD_FLAGS ((202 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 */
  510. #define NV_SI_RO_BOARD_CUST_SPM_LOCATION ((203 * 8) + NV_BOARD_PARAM_START)
  511. #define NV_SI_RO_BOARD_RAS_DDR_CE_WINDOW ((204 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 */
  512. #define NV_SI_RO_BOARD_RAS_DDR_CE_TH1 ((205 * 8) + NV_BOARD_PARAM_START) /* Default: 0x000001F4 */
  513. #define NV_SI_RO_BOARD_RAS_DDR_CE_TH2 ((206 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00001388 */
  514. #define NV_SI_RO_BOARD_RAS_DDR_CE_THC ((207 * 8) + NV_BOARD_PARAM_START) /* Default: 0x00000000 */
  515. #define NV_SI_RO_BOARD_MQ_SX_RCA0_TXRX_20GPRESET ((208 * 8) + NV_BOARD_PARAM_START)
  516. #define NV_SI_RO_BOARD_MQ_SX_RCA1_TXRX_20GPRESET ((209 * 8) + NV_BOARD_PARAM_START)
  517. #define NV_SI_RO_BOARD_MQ_SX_RCA0_TXRX_25GPRESET ((210 * 8) + NV_BOARD_PARAM_START)
  518. #define NV_SI_RO_BOARD_MQ_SX_RCA1_TXRX_25GPRESET ((211 * 8) + NV_BOARD_PARAM_START)
  519. #define NV_SI_RO_BOARD_MQ_S0_RCA0_TXRX_G3PRESET ((212 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFF */
  520. #define NV_SI_RO_BOARD_MQ_S0_RCA1_TXRX_G3PRESET ((213 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFF */
  521. #define NV_SI_RO_BOARD_MQ_S0_RCA2_TXRX_G3PRESET ((214 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFF */
  522. #define NV_SI_RO_BOARD_MQ_S0_RCA3_TXRX_G3PRESET ((215 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFF */
  523. #define NV_SI_RO_BOARD_MQ_S0_RCA4_TXRX_G3PRESET ((216 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFF */
  524. #define NV_SI_RO_BOARD_MQ_S0_RCA5_TXRX_G3PRESET ((217 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFF */
  525. #define NV_SI_RO_BOARD_MQ_S0_RCA6_TXRX_G3PRESET ((218 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFF */
  526. #define NV_SI_RO_BOARD_MQ_S0_RCA7_TXRX_G3PRESET ((219 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFF */
  527. #define NV_SI_RO_BOARD_MQ_S1_RCA2_TXRX_G3PRESET ((220 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFF */
  528. #define NV_SI_RO_BOARD_MQ_S1_RCA3_TXRX_G3PRESET ((221 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFF */
  529. #define NV_SI_RO_BOARD_MQ_S1_RCA4_TXRX_G3PRESET ((222 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFF */
  530. #define NV_SI_RO_BOARD_MQ_S1_RCA5_TXRX_G3PRESET ((223 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFF */
  531. #define NV_SI_RO_BOARD_MQ_S1_RCA6_TXRX_G3PRESET ((224 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFF */
  532. #define NV_SI_RO_BOARD_MQ_S1_RCA7_TXRX_G3PRESET ((225 * 8) + NV_BOARD_PARAM_START) /* Default: 0xFFFFFFFF */
  533. #define NV_SI_RO_BOARD_MQ_S0_RCA0_TXRX_G4PRESET ((226 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  534. #define NV_SI_RO_BOARD_MQ_S0_RCA1_TXRX_G4PRESET ((227 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  535. #define NV_SI_RO_BOARD_MQ_S0_RCA2_TXRX_G4PRESET ((228 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  536. #define NV_SI_RO_BOARD_MQ_S0_RCA3_TXRX_G4PRESET ((229 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  537. #define NV_SI_RO_BOARD_MQ_S0_RCA4_TXRX_G4PRESET ((230 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  538. #define NV_SI_RO_BOARD_MQ_S0_RCA5_TXRX_G4PRESET ((231 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  539. #define NV_SI_RO_BOARD_MQ_S0_RCA6_TXRX_G4PRESET ((232 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  540. #define NV_SI_RO_BOARD_MQ_S0_RCA7_TXRX_G4PRESET ((233 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  541. #define NV_SI_RO_BOARD_MQ_S1_RCA2_TXRX_G4PRESET ((234 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  542. #define NV_SI_RO_BOARD_MQ_S1_RCA3_TXRX_G4PRESET ((235 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  543. #define NV_SI_RO_BOARD_MQ_S1_RCA4_TXRX_G4PRESET ((236 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  544. #define NV_SI_RO_BOARD_MQ_S1_RCA5_TXRX_G4PRESET ((237 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  545. #define NV_SI_RO_BOARD_MQ_S1_RCA6_TXRX_G4PRESET ((238 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  546. #define NV_SI_RO_BOARD_MQ_S1_RCA7_TXRX_G4PRESET ((239 * 8) + NV_BOARD_PARAM_START) /* Default: 0x57575757 */
  547. #define NV_PMPRO_REGION4_LOAD_END (NV_SI_RO_BOARD_MQ_S1_RCA7_TXRX_G4PRESET)
  548. //
  549. // NOTE: Add before NV_BOARD_PARAM_MAX and increase its value
  550. //
  551. #define NV_BOARD_PARAM_MAX ((207 * 8) + NV_BOARD_PARAM_START)
  552. typedef UINT32 NVPARAM;
  553. #endif /* NVPARAMDEF_H_ */