Armada80x0McBinBoardDescLib.c 3.4 KB

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  1. /**
  2. *
  3. * Copyright (C) 2018, Marvell International Ltd. and its affiliates.
  4. *
  5. * SPDX-License-Identifier: BSD-2-Clause-Patent
  6. *
  7. **/
  8. #include <Uefi.h>
  9. #include <Library/ArmadaBoardDescLib.h>
  10. #include <Library/BaseMemoryLib.h>
  11. #include <Library/DebugLib.h>
  12. #include <Library/IoLib.h>
  13. #include <Library/MemoryAllocationLib.h>
  14. #include <Library/UefiBootServicesTableLib.h>
  15. //
  16. // General purpose routine for per-board initalization
  17. //
  18. EFI_STATUS
  19. ArmadaBoardInit (
  20. VOID
  21. )
  22. {
  23. return EFI_SUCCESS;
  24. }
  25. //
  26. // GPIO Expander
  27. //
  28. EFI_STATUS
  29. EFIAPI
  30. ArmadaBoardGpioExpanderGet (
  31. IN OUT MV_GPIO_EXPANDER **GpioExpanders,
  32. IN OUT UINTN *GpioExpanderCount
  33. )
  34. {
  35. /* No GPIO expanders on board */
  36. *GpioExpanders = NULL;
  37. *GpioExpanderCount = 0;
  38. return EFI_SUCCESS;
  39. }
  40. //
  41. // PCIE
  42. //
  43. STATIC
  44. MV_PCIE_CONTROLLER mPcieController[] = {
  45. { /* PCIE0 @0xF2600000 */
  46. .PcieDbiAddress = 0xF2600000,
  47. .ConfigSpaceAddress = 0xE0000000,
  48. .HaveResetGpio = TRUE,
  49. .PcieResetGpio =
  50. {
  51. MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER,
  52. MV_GPIO_CP0_CONTROLLER1,
  53. 20,
  54. FALSE
  55. },
  56. .PcieBusMin = 0,
  57. .PcieBusMax = 0xFE,
  58. .PcieIoTranslation = 0xEFF00000,
  59. .PcieIoWinBase = 0x0,
  60. .PcieIoWinSize = 0x10000,
  61. .PcieMmio32Translation = 0,
  62. .PcieMmio32WinBase = 0xC0000000,
  63. .PcieMmio32WinSize = 0x20000000,
  64. .PcieMmio64Translation = 0,
  65. .PcieMmio64WinBase = 0x800000000,
  66. .PcieMmio64WinSize = 0x100000000,
  67. }
  68. };
  69. /**
  70. Return the number and description of PCIE controllers used on the platform.
  71. @param[in out] **PcieControllers Array containing PCIE controllers'
  72. description.
  73. @param[in out] *PcieControllerCount Amount of used PCIE controllers.
  74. @retval EFI_SUCCESS The data were obtained successfully.
  75. @retval other Return error status.
  76. **/
  77. EFI_STATUS
  78. EFIAPI
  79. ArmadaBoardPcieControllerGet (
  80. IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers,
  81. IN OUT UINTN *PcieControllerCount
  82. )
  83. {
  84. *PcieControllers = mPcieController;
  85. *PcieControllerCount = ARRAY_SIZE (mPcieController);
  86. return EFI_SUCCESS;
  87. }
  88. //
  89. // Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDescLib
  90. //
  91. STATIC
  92. MV_BOARD_SDMMC_DESC mMcBinSdMmcDescTemplate[] = {
  93. { /* eMMC 0xF06E0000 */
  94. 0, /* SOC will be filled by MvBoardDescDxe */
  95. 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */
  96. FALSE, /* Xenon1v8Enabled */
  97. TRUE, /* Xenon8BitBusEnabled */
  98. TRUE, /* XenonSlowModeEnabled */
  99. 0x40, /* XenonTuningStepDivisor */
  100. EmbeddedSlot /* SlotType */
  101. },
  102. { /* SD/MMC 0xF2780000 */
  103. 0, /* SOC will be filled by MvBoardDescDxe */
  104. 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */
  105. FALSE, /* Xenon1v8Enabled */
  106. FALSE, /* Xenon8BitBusEnabled */
  107. FALSE, /* XenonSlowModeEnabled */
  108. 0x19, /* XenonTuningStepDivisor */
  109. EmbeddedSlot /* SlotType */
  110. }
  111. };
  112. EFI_STATUS
  113. EFIAPI
  114. ArmadaBoardDescSdMmcGet (
  115. OUT UINTN *SdMmcDevCount,
  116. OUT MV_BOARD_SDMMC_DESC **SdMmcDesc
  117. )
  118. {
  119. *SdMmcDesc = mMcBinSdMmcDescTemplate;
  120. *SdMmcDevCount = ARRAY_SIZE (mMcBinSdMmcDescTemplate);
  121. return EFI_SUCCESS;
  122. }