PlatformSecLib.c 5.8 KB

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  1. /** @file
  2. Platform SEC Library for Quark.
  3. Copyright (c) 2013-2015 Intel Corporation.
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <PiPei.h>
  7. #include <Ppi/SecPlatformInformation.h>
  8. #include <Ppi/TemporaryRamSupport.h>
  9. #include <Library/PcdLib.h>
  10. #include <Library/BaseLib.h>
  11. #include <Library/DebugLib.h>
  12. #include <Library/BaseMemoryLib.h>
  13. #include <Library/HobLib.h>
  14. #include <Library/MtrrLib.h>
  15. /**
  16. Entry point to the C language phase of SEC. After the SEC assembly
  17. code has initialized some temporary memory and set up the stack,
  18. the control is transferred to this function.
  19. @param SizeOfRam Size of the temporary memory available for use.
  20. @param TempRamBase Base address of temporary ram
  21. @param BootFirmwareVolume Base address of the Boot Firmware Volume.
  22. **/
  23. VOID
  24. EFIAPI
  25. SecStartup (
  26. IN UINT32 SizeOfRam,
  27. IN UINT32 TempRamBase,
  28. IN VOID *BootFirmwareVolume
  29. );
  30. /**
  31. Auto-generated function that calls the library constructors for all of the module's
  32. dependent libraries. This function must be called by the SEC Core once a stack has
  33. been established.
  34. **/
  35. VOID
  36. EFIAPI
  37. ProcessLibraryConstructorList (
  38. VOID
  39. );
  40. /**
  41. Entry point to the C language phase of PlatformSecLib. After the SEC assembly
  42. code has initialized some temporary memory and set up the stack, control is
  43. transferred to this function.
  44. **/
  45. VOID
  46. EFIAPI
  47. PlatformSecLibStartup (
  48. VOID
  49. )
  50. {
  51. //
  52. // Process all library constructor functions linked to SecCore.
  53. // This function must be called before any library functions are called
  54. //
  55. ProcessLibraryConstructorList ();
  56. //
  57. // Set write back cache attribute for SPI FLASH
  58. //
  59. MtrrSetMemoryAttribute (
  60. PcdGet32 (PcdFlashAreaBaseAddress),
  61. PcdGet32 (PcdFlashAreaSize),
  62. CacheWriteBack
  63. );
  64. //
  65. // Set write back cache attribute for 512KB Embedded SRAM
  66. //
  67. MtrrSetMemoryAttribute (
  68. PcdGet32 (PcdEsramStage1Base),
  69. SIZE_512KB,
  70. CacheWriteBack
  71. );
  72. //
  73. // Pass control to SecCore module passing in the size of the temporary RAM in
  74. // Embedded SRAM, the base address of the temporary RAM in Embedded SRAM, and
  75. // the base address of the boot firmware volume. The top 32KB of the 512 KB
  76. // embedded SRAM are used as temporary RAM.
  77. //
  78. SecStartup (
  79. SIZE_32KB,
  80. PcdGet32 (PcdEsramStage1Base) + SIZE_512KB - SIZE_32KB,
  81. (VOID *)(UINTN)PcdGet32 (PcdFlashFvRecoveryBase)
  82. );
  83. }
  84. /**
  85. A developer supplied function to perform platform specific operations.
  86. It's a developer supplied function to perform any operations appropriate to a
  87. given platform. It's invoked just before passing control to PEI core by SEC
  88. core. Platform developer may modify the SecCoreData and PPI list that is
  89. passed to PEI Core.
  90. @param SecCoreData The same parameter as passing to PEI core. It
  91. could be overridden by this function.
  92. @param PpiList The default PPI list passed from generic SEC
  93. part.
  94. @return The final PPI list that platform wishes to passed to PEI core.
  95. **/
  96. EFI_PEI_PPI_DESCRIPTOR *
  97. EFIAPI
  98. SecPlatformMain (
  99. IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData,
  100. IN EFI_PEI_PPI_DESCRIPTOR *PpiList
  101. )
  102. {
  103. return NULL;
  104. }
  105. /**
  106. This interface conveys state information out of the Security (SEC) phase into PEI.
  107. @param PeiServices Pointer to the PEI Services Table.
  108. @param StructureSize Pointer to the variable describing size of the input buffer.
  109. @param PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM_INFORMATION_RECORD.
  110. @retval EFI_SUCCESS The data was successfully returned.
  111. @retval EFI_BUFFER_TOO_SMALL The buffer was too small.
  112. **/
  113. EFI_STATUS
  114. EFIAPI
  115. SecPlatformInformation (
  116. IN CONST EFI_PEI_SERVICES **PeiServices,
  117. IN OUT UINT64 *StructureSize,
  118. OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord
  119. )
  120. {
  121. UINT32 *BIST;
  122. UINT32 Size;
  123. UINT32 Count;
  124. EFI_HOB_GUID_TYPE *GuidHob;
  125. UINT32 *TopOfStack;
  126. //
  127. // Top of the stack is the top of the 512KB Embedded SRAM region
  128. //
  129. TopOfStack = (UINT32 *)(UINTN)(PcdGet32 (PcdEsramStage1Base) + SIZE_512KB);
  130. GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformationPpiGuid);
  131. if (GuidHob != NULL) {
  132. Size = GET_GUID_HOB_DATA_SIZE (GuidHob);
  133. BIST = GET_GUID_HOB_DATA (GuidHob);
  134. } else {
  135. //
  136. // The entries of BIST information, together with the number of them,
  137. // reside in the bottom of stack, left untouched by normal stack operation.
  138. // This routine copies the BIST information to the buffer pointed by
  139. // PlatformInformationRecord for output.
  140. //
  141. Count = *(TopOfStack - 1);
  142. Size = Count * sizeof (IA32_HANDOFF_STATUS);
  143. BIST = (UINT32 *) ((UINT32) TopOfStack - sizeof (UINT32) - Size);
  144. //
  145. // Copy Data from Stack to Hob to avoid data is lost after memory is ready.
  146. //
  147. BuildGuidDataHob (
  148. &gEfiSecPlatformInformationPpiGuid,
  149. BIST,
  150. (UINTN)Size
  151. );
  152. GuidHob = GetFirstGuidHob (&gEfiSecPlatformInformationPpiGuid);
  153. Size = GET_GUID_HOB_DATA_SIZE (GuidHob);
  154. BIST = GET_GUID_HOB_DATA (GuidHob);
  155. }
  156. if ((*StructureSize) < (UINT64) Size) {
  157. *StructureSize = Size;
  158. return EFI_BUFFER_TOO_SMALL;
  159. }
  160. *StructureSize = Size;
  161. CopyMem (PlatformInformationRecord, BIST, Size);
  162. return EFI_SUCCESS;
  163. }
  164. /**
  165. This interface disables temporary memory in SEC Phase.
  166. **/
  167. VOID
  168. EFIAPI
  169. SecPlatformDisableTemporaryMemory (
  170. VOID
  171. )
  172. {
  173. }