Platform.inc 3.9 KB

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  1. ;
  2. ; Copyright (c) 2013-2015 Intel Corporation.
  3. ;
  4. ; SPDX-License-Identifier: BSD-2-Clause-Patent
  5. ;
  6. ;------------------------------------------------------------------------------
  7. ;
  8. ; Module Name:
  9. ;
  10. ; Platform.inc
  11. ;
  12. ; Abstract:
  13. ;
  14. ; Quark A0 Platform Specific Definitions
  15. ;
  16. ;------------------------------------------------------------------------------
  17. JMP32 MACRO FunctionName
  18. lea esp, @F
  19. jmp FunctionName
  20. @@:
  21. ENDM
  22. RET32 MACRO
  23. jmp esp
  24. ENDM
  25. ;
  26. ; ROM/SPI/MEMORY Definitions
  27. ;
  28. QUARK_DDR3_MEM_BASE_ADDRESS EQU 000000000h ; Memory Base Address = 0
  29. QUARK_MAX_DDR3_MEM_SIZE_BYTES EQU 080000000h ; DDR3 Memory Size = 2GB
  30. QUARK_ESRAM_MEM_SIZE_BYTES EQU 000080000h ; eSRAM Memory Size = 512K
  31. QUARK_STACK_SIZE_BYTES EQU 008000h ; Quark stack size = 32K
  32. ;
  33. ; RTC/CMOS definitions
  34. ;
  35. RTC_INDEX EQU 070h
  36. NMI_DISABLE EQU 080h ; Bit7=1 disables NMI
  37. NMI_ENABLE EQU 000h ; Bit7=0 disables NMI
  38. RTC_DATA EQU 071h
  39. ;
  40. ; PCI Configuration definitions
  41. ;
  42. PCI_CFG EQU 1 SHL 01Fh ; PCI configuration access mechanism
  43. PCI_ADDRESS_PORT EQU 0CF8h
  44. PCI_DATA_PORT EQU 0CFCh
  45. ;
  46. ; Quark PCI devices
  47. ;
  48. HOST_BRIDGE_PFA EQU 0000h ; B0:D0:F0 (Host Bridge)
  49. ILB_PFA EQU 00F8h ; B0:D31:F0 (Legacy Block)
  50. ;
  51. ; ILB PCI Config Registers
  52. ;
  53. BDE EQU 0D4h ; BIOS Decode Enable register
  54. DECODE_ALL_REGIONS_ENABLE EQU 0FF000000h ; Decode all BIOS decode ranges
  55. ;
  56. ; iLB Reset Register
  57. ;
  58. ILB_RESET_REG EQU 0CF9h
  59. CF9_WARM_RESET EQU 02h
  60. CF9_COLD_RESET EQU 08h
  61. ;
  62. ; Host Bridge PCI Config Registers
  63. ;
  64. MESSAGE_BUS_CONTROL_REG EQU 0D0h ; Message Bus Control Register
  65. SB_OPCODE_FIELD EQU 018h ; Bit location of Opcode field
  66. OPCODE_SIDEBAND_REG_READ EQU 010h ; Read opcode
  67. OPCODE_SIDEBAND_REG_WRITE EQU 011h ; Write opcode
  68. OPCODE_SIDEBAND_ALT_REG_READ EQU 06h ; Alternate Read opcode
  69. OPCODE_SIDEBAND_ALT_REG_WRITE EQU 07h ; Alternate Write opcode
  70. OPCODE_WARM_RESET_REQUEST EQU 0F4h ; Reset Warm
  71. OPCODE_COLD_RESET_REQUEST EQU 0F5h ; Reset Cold
  72. SB_PORT_FIELD EQU 010h ; Bit location of Port ID field
  73. MEMORY_ARBITER_PORT_ID EQU 00h
  74. HOST_BRIDGE_PORT_ID EQU 03h
  75. RMU_PORT_ID EQU 04h
  76. MEMORY_MANAGER_PORT_ID EQU 05h
  77. SOC_UNIT_PORT_ID EQU 031h
  78. SB_ADDR_FIELD EQU 008h ; Bit location of Register field
  79. SB_BE_FIELD EQU 004h ; Bit location of Byte Enables field
  80. ALL_BYTE_EN EQU 00Fh ; All Byte Enables
  81. MESSAGE_DATA_REG EQU 0D4h ; Message Data Register
  82. ;
  83. ; Memory Arbiter Config Registers
  84. ;
  85. AEC_CTRL_OFFSET EQU 00h
  86. ;
  87. ; Host Bridge Config Registers
  88. ;
  89. HMISC2_OFFSET EQU 03h
  90. OR_PM_FIELD EQU 010h
  91. SMI_EN EQU 1 SHL 13h
  92. HMBOUND_OFFSET EQU 08h
  93. HMBOUND_ADDRESS EQU (QUARK_DDR3_MEM_BASE_ADDRESS + QUARK_MAX_DDR3_MEM_SIZE_BYTES + QUARK_ESRAM_MEM_SIZE_BYTES)
  94. HMBOUND_LOCK EQU 00000001h
  95. HECREG_OFFSET EQU 09h
  96. EC_BASE EQU 0E0000000h
  97. EC_ENABLE EQU 01h
  98. HLEGACY_OFFSET EQU 0Ah
  99. NMI EQU 1 SHL 0Eh ; Pin 14
  100. SMI EQU 1 SHL 0Ch ; Pin 12
  101. INTR EQU 1 SHL 0Ah ; Pin 10
  102. ;
  103. ; Memory Manager Config Registers
  104. ;
  105. ESRAMPGCTRL_BLOCK_OFFSET EQU 082h
  106. BLOCK_ENABLE_PG EQU 010000000h
  107. BIMRVCTL_OFFSET EQU 019h
  108. ENABLE_IMR_INTERRUPT EQU 080000000h
  109. ;
  110. ; SOC UNIT Debug Registers
  111. ;
  112. CFGSTICKY_W1_OFFSET EQU 050h
  113. FORCE_COLD_RESET EQU 00000001h
  114. CFGSTICKY_RW_OFFSET EQU 051h
  115. RESET_FOR_ESRAM_LOCK EQU 00000020h
  116. RESET_FOR_HMBOUND_LOCK EQU 00000040h
  117. CFGNONSTICKY_W1_OFFSET EQU 052h
  118. FORCE_WARM_RESET EQU 00000001h