Flat32.asm 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685
  1. ;------------------------------------------------------------------------------
  2. ;
  3. ; Copyright (c) 2013-2015 Intel Corporation.
  4. ;
  5. ; SPDX-License-Identifier: BSD-2-Clause-Patent
  6. ;
  7. ; Module Name:
  8. ;
  9. ; Flat32.asm
  10. ;
  11. ; Abstract:
  12. ;
  13. ; This is the code that goes from real-mode to protected mode.
  14. ; It consumes the reset vector, configures the stack.
  15. ;
  16. ;
  17. ;------------------------------------------------------------------------------
  18. ;
  19. ; Define assembler characteristics
  20. ;
  21. .586p
  22. .model flat, c
  23. ;
  24. ; Include processor definitions
  25. ;
  26. INCLUDE Platform.inc
  27. ;
  28. ; CR0 cache control bit definition
  29. ;
  30. CR0_CACHE_DISABLE EQU 040000000h
  31. CR0_NO_WRITE EQU 020000000h
  32. ;
  33. ; External and public declarations
  34. ; TopOfStack is used by C code
  35. ; SecStartup is the entry point to the C code
  36. ; Neither of these names can be modified without
  37. ; updating the C code.
  38. ;
  39. EXTRN PlatformSecLibStartup: NEAR
  40. EXTERNDEF C PcdGet32 (PcdEsramStage1Base):DWORD
  41. ;
  42. ; Contrary to the name, this file contains 16 bit code as well.
  43. ;
  44. _TEXT_REALMODE SEGMENT PARA PUBLIC USE16 'CODE'
  45. ASSUME CS:_TEXT_REALMODE, DS:_TEXT_REALMODE
  46. ;----------------------------------------------------------------------------
  47. ;
  48. ; Procedure: _ModuleEntryPoint
  49. ;
  50. ; Input: None
  51. ;
  52. ; Output: None
  53. ;
  54. ; Destroys: Assume all registers
  55. ;
  56. ; Description:
  57. ;
  58. ; Transition to non-paged flat-model protected mode from a
  59. ; hard-coded GDT that provides exactly two descriptors.
  60. ; This is a bare bones transition to protected mode only
  61. ; used for a while in PEI and possibly DXE.
  62. ;
  63. ; After enabling protected mode, a far jump is executed to
  64. ; transfer to PEI using the newly loaded GDT.
  65. ;
  66. ; Return: None
  67. ;
  68. ;----------------------------------------------------------------------------
  69. align 16
  70. _ModuleEntryPoint PROC C PUBLIC
  71. ;
  72. ; Warm Reset (INIT#) check.
  73. ;
  74. mov si, 0F000h
  75. mov ds, si
  76. mov si, 0FFF0h
  77. cmp BYTE PTR [si], 0EAh ; Is it warm reset ?
  78. jne NotWarmReset ; JIf not.
  79. mov al, 08
  80. mov dx, 0cf9h
  81. out dx, al
  82. mov al, 055h
  83. out 080h, al;
  84. jmp $
  85. NotWarmReset:
  86. ;
  87. ; Load the GDT table in GdtDesc
  88. ;
  89. mov esi, OFFSET GdtDesc
  90. db 66h
  91. lgdt fword ptr cs:[si]
  92. ;
  93. ; Transition to 16 bit protected mode
  94. ;
  95. mov eax, cr0 ; Get control register 0
  96. or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #1)
  97. mov cr0, eax ; Activate protected mode
  98. ;
  99. ; Now we're in 16 bit protected mode
  100. ; Set up the selectors for 32 bit protected mode entry
  101. ;
  102. mov ax, SYS_DATA_SEL
  103. mov ds, ax
  104. mov es, ax
  105. mov fs, ax
  106. mov gs, ax
  107. mov ss, ax
  108. ;
  109. ; Transition to Flat 32 bit protected mode
  110. ; The jump to a far pointer causes the transition to 32 bit mode
  111. ;
  112. mov esi, offset ProtectedModeEntryLinearAddress
  113. jmp fword ptr cs:[si]
  114. _ModuleEntryPoint ENDP
  115. _TEXT_REALMODE ENDS
  116. .code
  117. ;
  118. ; Protected mode portion initializes stack, configures cache, and calls C entry point
  119. ;
  120. ;----------------------------------------------------------------------------
  121. ;
  122. ; Procedure: ProtectedModeEntryPoint
  123. ;
  124. ; Input: Executing in 32 Bit Protected (flat) mode
  125. ; cs: 0-4GB
  126. ; ds: 0-4GB
  127. ; es: 0-4GB
  128. ; fs: 0-4GB
  129. ; gs: 0-4GB
  130. ; ss: 0-4GB
  131. ;
  132. ; Output: This function never returns
  133. ;
  134. ; Destroys:
  135. ; ecx
  136. ; edi
  137. ; esi
  138. ; esp
  139. ;
  140. ; Description:
  141. ; Perform any essential early platform initilaisation
  142. ; Setup a stack
  143. ; Call the main EDKII Sec C code
  144. ;
  145. ;----------------------------------------------------------------------------
  146. ProtectedModeEntryPoint PROC NEAR C PUBLIC
  147. JMP32 stackless_EarlyPlatformInit
  148. ;
  149. ; Set up stack pointer
  150. ;
  151. mov esp, PcdGet32(PcdEsramStage1Base)
  152. mov esi, QUARK_ESRAM_MEM_SIZE_BYTES
  153. add esp, esi ; ESP = top of stack (stack grows downwards).
  154. ;
  155. ; Store the the BIST value in EBP
  156. ;
  157. mov ebp, 00h ; No processor BIST on Quark
  158. ;
  159. ; Push processor count to stack first, then BIST status (AP then BSP)
  160. ;
  161. mov eax, 1
  162. cpuid
  163. shr ebx, 16
  164. and ebx, 0000000FFh
  165. cmp bl, 1
  166. jae PushProcessorCount
  167. ;
  168. ; Some processors report 0 logical processors. Effectively 0 = 1.
  169. ; So we fix up the processor count
  170. ;
  171. inc ebx
  172. PushProcessorCount:
  173. push ebx
  174. ;
  175. ; We need to implement a long-term solution for BIST capture. For now, we just copy BSP BIST
  176. ; for all processor threads
  177. ;
  178. xor ecx, ecx
  179. mov cl, bl
  180. PushBist:
  181. push ebp
  182. loop PushBist
  183. ;
  184. ; Pass Control into the PEI Core
  185. ;
  186. call PlatformSecLibStartup
  187. ;
  188. ; PEI Core should never return to here, this is just to capture an invalid return.
  189. ;
  190. jmp $
  191. ProtectedModeEntryPoint ENDP
  192. ;----------------------------------------------------------------------------
  193. ;
  194. ; Procedure: stackless_EarlyPlatformInit
  195. ;
  196. ; Input: esp - Return address
  197. ;
  198. ; Output: None
  199. ;
  200. ; Destroys:
  201. ; eax
  202. ; ecx
  203. ; dx
  204. ; ebp
  205. ;
  206. ; Description:
  207. ; Any essential early platform initialisation required:
  208. ; (1) Disable Cache
  209. ; (2) Disable NMI's/SMI's
  210. ; (3) Setup HMBOUND (defines what memory accesses go to MMIO/RAM)
  211. ; (4) Setup eSRAM (provide early memory to the system)
  212. ; (5) Setup PCIEXBAR access mechanism
  213. ; (6) Open up full SPI flash decode
  214. ;
  215. ;----------------------------------------------------------------------------
  216. stackless_EarlyPlatformInit PROC NEAR C PUBLIC
  217. ;
  218. ; Save return address
  219. ;
  220. mov ebp, esp
  221. ;
  222. ; Ensure cache is disabled.
  223. ;
  224. mov eax, cr0
  225. or eax, CR0_CACHE_DISABLE + CR0_NO_WRITE
  226. invd
  227. mov cr0, eax
  228. ;
  229. ; Disable NMI
  230. ; Good convention suggests you should read back RTC data port after
  231. ; accessing the RTC index port.
  232. ;
  233. mov al, NMI_DISABLE
  234. mov dx, RTC_INDEX
  235. out dx, al
  236. mov dx, RTC_DATA
  237. in al, dx
  238. ;
  239. ; Disable SMI (Disables SMI wire, not SMI messages)
  240. ;
  241. mov ecx, (OPCODE_SIDEBAND_REG_READ SHL SB_OPCODE_FIELD) OR (HOST_BRIDGE_PORT_ID SHL SB_PORT_FIELD) OR (HMISC2_OFFSET SHL SB_ADDR_FIELD)
  242. JMP32 stackless_SideBand_Read
  243. and eax, NOT (SMI_EN)
  244. mov ecx, (OPCODE_SIDEBAND_REG_WRITE SHL SB_OPCODE_FIELD) OR (HOST_BRIDGE_PORT_ID SHL SB_PORT_FIELD) OR (HMISC2_OFFSET SHL SB_ADDR_FIELD)
  245. JMP32 stackless_SideBand_Write
  246. ;
  247. ; Before we get going, check SOC Unit Registers to see if we are required to issue a warm/cold reset
  248. ;
  249. mov ecx, (OPCODE_SIDEBAND_ALT_REG_READ SHL SB_OPCODE_FIELD) OR (SOC_UNIT_PORT_ID SHL SB_PORT_FIELD) OR (CFGNONSTICKY_W1_OFFSET SHL SB_ADDR_FIELD)
  250. JMP32 stackless_SideBand_Read
  251. and eax, FORCE_WARM_RESET
  252. jz TestForceColdReset ; Zero means bit clear, we're not requested to warm reset so continue as normal
  253. jmp IssueWarmReset
  254. TestForceColdReset:
  255. mov ecx, (OPCODE_SIDEBAND_ALT_REG_READ SHL SB_OPCODE_FIELD) OR (SOC_UNIT_PORT_ID SHL SB_PORT_FIELD) OR (CFGSTICKY_W1_OFFSET SHL SB_ADDR_FIELD)
  256. JMP32 stackless_SideBand_Read
  257. and eax, FORCE_COLD_RESET
  258. jz TestHmboundLock ; Zero means bit clear, we're not requested to cold reset so continue as normal
  259. jmp IssueColdReset
  260. ;
  261. ; Before setting HMBOUND, check it's not locked
  262. ;
  263. TestHmboundLock:
  264. mov ecx, (OPCODE_SIDEBAND_REG_READ SHL SB_OPCODE_FIELD) OR (HOST_BRIDGE_PORT_ID SHL SB_PORT_FIELD) OR (HMBOUND_OFFSET SHL SB_ADDR_FIELD)
  265. JMP32 stackless_SideBand_Read
  266. and eax, HMBOUND_LOCK
  267. jz ConfigHmbound ; Zero means bit clear, we have the config we want so continue as normal
  268. ;
  269. ; Failed to config - store sticky bit debug
  270. ;
  271. mov ecx, (OPCODE_SIDEBAND_ALT_REG_READ SHL SB_OPCODE_FIELD) OR (SOC_UNIT_PORT_ID SHL SB_PORT_FIELD) OR (CFGSTICKY_RW_OFFSET SHL SB_ADDR_FIELD)
  272. JMP32 stackless_SideBand_Read
  273. or eax, RESET_FOR_HMBOUND_LOCK ; Set the bit we're interested in
  274. mov ecx, (OPCODE_SIDEBAND_ALT_REG_WRITE SHL SB_OPCODE_FIELD) OR (SOC_UNIT_PORT_ID SHL SB_PORT_FIELD) OR (CFGSTICKY_RW_OFFSET SHL SB_ADDR_FIELD)
  275. JMP32 stackless_SideBand_Write
  276. jmp IssueWarmReset
  277. ;
  278. ; Set up the HMBOUND register
  279. ;
  280. ConfigHmbound:
  281. mov eax, HMBOUND_ADDRESS ; Data (Set HMBOUND location)
  282. mov ecx, (OPCODE_SIDEBAND_REG_WRITE SHL SB_OPCODE_FIELD) OR (HOST_BRIDGE_PORT_ID SHL SB_PORT_FIELD) OR (HMBOUND_OFFSET SHL SB_ADDR_FIELD)
  283. JMP32 stackless_SideBand_Write
  284. ;
  285. ; Enable interrupts to Remote Management Unit when a IMR/SMM/HMBOUND violation occurs.
  286. ;
  287. mov eax, ENABLE_IMR_INTERRUPT ; Data (Set interrupt enable mask)
  288. mov ecx, (OPCODE_SIDEBAND_REG_WRITE SHL SB_OPCODE_FIELD) OR (MEMORY_MANAGER_PORT_ID SHL SB_PORT_FIELD) OR (BIMRVCTL_OFFSET SHL SB_ADDR_FIELD)
  289. JMP32 stackless_SideBand_Write
  290. ;
  291. ; Set eSRAM address
  292. ;
  293. mov eax, PcdGet32 (PcdEsramStage1Base) ; Data (Set eSRAM location)
  294. shr eax, 18h ; Data (Set eSRAM location)
  295. add eax, BLOCK_ENABLE_PG
  296. mov ecx, (OPCODE_SIDEBAND_REG_WRITE SHL SB_OPCODE_FIELD) OR (MEMORY_MANAGER_PORT_ID SHL SB_PORT_FIELD) OR (ESRAMPGCTRL_BLOCK_OFFSET SHL SB_ADDR_FIELD)
  297. JMP32 stackless_SideBand_Write
  298. ;
  299. ; Check that we're not blocked from setting the config that we want.
  300. ;
  301. mov ecx, (OPCODE_SIDEBAND_REG_READ SHL SB_OPCODE_FIELD) OR (MEMORY_MANAGER_PORT_ID SHL SB_PORT_FIELD) OR (ESRAMPGCTRL_BLOCK_OFFSET SHL SB_ADDR_FIELD)
  302. JMP32 stackless_SideBand_Read
  303. and eax, BLOCK_ENABLE_PG
  304. jnz ConfigPci ; Non-zero means bit set, we have the config we want so continue as normal
  305. ;
  306. ; Failed to config - store sticky bit debug
  307. ;
  308. mov ecx, (OPCODE_SIDEBAND_ALT_REG_READ SHL SB_OPCODE_FIELD) OR (SOC_UNIT_PORT_ID SHL SB_PORT_FIELD) OR (CFGSTICKY_RW_OFFSET SHL SB_ADDR_FIELD)
  309. JMP32 stackless_SideBand_Read
  310. or eax, RESET_FOR_ESRAM_LOCK ; Set the bit we're interested in
  311. mov ecx, (OPCODE_SIDEBAND_ALT_REG_WRITE SHL SB_OPCODE_FIELD) OR (SOC_UNIT_PORT_ID SHL SB_PORT_FIELD) OR (CFGSTICKY_RW_OFFSET SHL SB_ADDR_FIELD)
  312. JMP32 stackless_SideBand_Write
  313. jmp IssueWarmReset
  314. ;
  315. ; Enable PCIEXBAR
  316. ;
  317. ConfigPci:
  318. mov eax, (EC_BASE + EC_ENABLE) ; Data
  319. mov ecx, (OPCODE_SIDEBAND_REG_WRITE SHL SB_OPCODE_FIELD) OR (MEMORY_ARBITER_PORT_ID SHL SB_PORT_FIELD) OR (AEC_CTRL_OFFSET SHL SB_ADDR_FIELD)
  320. JMP32 stackless_SideBand_Write
  321. mov eax, (EC_BASE + EC_ENABLE) ; Data
  322. mov ecx, (OPCODE_SIDEBAND_REG_WRITE SHL SB_OPCODE_FIELD) OR (HOST_BRIDGE_PORT_ID SHL SB_PORT_FIELD) OR (HECREG_OFFSET SHL SB_ADDR_FIELD)
  323. JMP32 stackless_SideBand_Write
  324. ;
  325. ; Open up full 8MB SPI decode
  326. ;
  327. mov ebx, PCI_CFG OR (ILB_PFA SHL 8) OR BDE ; PCI Configuration address
  328. mov eax, DECODE_ALL_REGIONS_ENABLE
  329. JMP32 stackless_PCIConfig_Write
  330. ;
  331. ; Enable NMI operation
  332. ; Good convention suggests you should read back RTC data port after
  333. ; accessing the RTC index port.
  334. ;
  335. mov al, NMI_ENABLE
  336. mov dx, RTC_INDEX
  337. out dx, al
  338. mov dx, RTC_DATA
  339. in al, dx
  340. ;
  341. ; Clear Host Bridge SMI, NMI, INTR fields
  342. ;
  343. mov ecx, (OPCODE_SIDEBAND_REG_READ SHL SB_OPCODE_FIELD) OR (HOST_BRIDGE_PORT_ID SHL SB_PORT_FIELD) OR (HLEGACY_OFFSET SHL SB_ADDR_FIELD)
  344. JMP32 stackless_SideBand_Read
  345. and eax, NOT(NMI + SMI + INTR) ; Clear NMI, SMI, INTR fields
  346. mov ecx, (OPCODE_SIDEBAND_REG_WRITE SHL SB_OPCODE_FIELD) OR (HOST_BRIDGE_PORT_ID SHL SB_PORT_FIELD) OR (HLEGACY_OFFSET SHL SB_ADDR_FIELD)
  347. JMP32 stackless_SideBand_Write
  348. ;
  349. ; Restore return address
  350. ;
  351. mov esp, ebp
  352. RET32
  353. IssueWarmReset:
  354. ;
  355. ; Issue Warm Reset request to Remote Management Unit via iLB
  356. ;
  357. mov ax, CF9_WARM_RESET
  358. mov dx, ILB_RESET_REG
  359. out dx, ax
  360. jmp $ ; Stay here until we are reset.
  361. IssueColdReset:
  362. ;
  363. ; Issue Cold Reset request to Remote Management Unit via iLB
  364. ;
  365. mov ax, CF9_COLD_RESET
  366. mov dx, ILB_RESET_REG
  367. out dx, ax
  368. jmp $ ; Stay here until we are reset.
  369. stackless_EarlyPlatformInit ENDP
  370. ;----------------------------------------------------------------------------
  371. ;
  372. ; Procedure: stackless_SideBand_Read
  373. ;
  374. ; Input: esp - return address
  375. ; ecx[15:8] - Register offset
  376. ; ecx[23:16] - Port ID
  377. ; ecx[31:24] - Opcode
  378. ;
  379. ; Output: eax - Data read
  380. ;
  381. ; Destroys:
  382. ; eax
  383. ; ebx
  384. ; cl
  385. ; esi
  386. ;
  387. ; Description:
  388. ; Perform requested sideband read
  389. ;
  390. ;----------------------------------------------------------------------------
  391. stackless_SideBand_Read PROC NEAR C PUBLIC
  392. mov esi, esp ; Save the return address
  393. ;
  394. ; Load the SideBand Packet Register to generate the transaction
  395. ;
  396. mov ebx, PCI_CFG OR (HOST_BRIDGE_PFA SHL 8) OR MESSAGE_BUS_CONTROL_REG ; PCI Configuration address
  397. mov cl, (ALL_BYTE_EN SHL SB_BE_FIELD) ; Set all Byte Enable bits
  398. xchg eax, ecx
  399. JMP32 stackless_PCIConfig_Write
  400. xchg eax, ecx
  401. ;
  402. ; Read the SideBand Data Register
  403. ;
  404. mov ebx, PCI_CFG OR (HOST_BRIDGE_PFA SHL 8) OR MESSAGE_DATA_REG ; PCI Configuration address
  405. JMP32 stackless_PCIConfig_Read
  406. mov esp, esi ; Restore the return address
  407. RET32
  408. stackless_SideBand_Read ENDP
  409. ;----------------------------------------------------------------------------
  410. ;
  411. ; Procedure: stackless_SideBand_Write
  412. ;
  413. ; Input: esp - return address
  414. ; eax - Data
  415. ; ecx[15:8] - Register offset
  416. ; ecx[23:16] - Port ID
  417. ; ecx[31:24] - Opcode
  418. ;
  419. ; Output: None
  420. ;
  421. ; Destroys:
  422. ; ebx
  423. ; cl
  424. ; esi
  425. ;
  426. ; Description:
  427. ; Perform requested sideband write
  428. ;
  429. ;
  430. ;----------------------------------------------------------------------------
  431. stackless_SideBand_Write PROC NEAR C PUBLIC
  432. mov esi, esp ; Save the return address
  433. ;
  434. ; Load the SideBand Data Register with the data
  435. ;
  436. mov ebx, PCI_CFG OR (HOST_BRIDGE_PFA SHL 8) OR MESSAGE_DATA_REG ; PCI Configuration address
  437. JMP32 stackless_PCIConfig_Write
  438. ;
  439. ; Load the SideBand Packet Register to generate the transaction
  440. ;
  441. mov ebx, PCI_CFG OR (HOST_BRIDGE_PFA SHL 8) OR MESSAGE_BUS_CONTROL_REG ; PCI Configuration address
  442. mov cl, (ALL_BYTE_EN SHL SB_BE_FIELD) ; Set all Byte Enable bits
  443. xchg eax, ecx
  444. JMP32 stackless_PCIConfig_Write
  445. xchg eax, ecx
  446. mov esp, esi ; Restore the return address
  447. RET32
  448. stackless_SideBand_Write ENDP
  449. ;----------------------------------------------------------------------------
  450. ;
  451. ; Procedure: stackless_PCIConfig_Write
  452. ;
  453. ; Input: esp - return address
  454. ; eax - Data to write
  455. ; ebx - PCI Config Address
  456. ;
  457. ; Output: None
  458. ;
  459. ; Destroys:
  460. ; dx
  461. ;
  462. ; Description:
  463. ; Perform a DWORD PCI Configuration write
  464. ;
  465. ;----------------------------------------------------------------------------
  466. stackless_PCIConfig_Write PROC NEAR C PUBLIC
  467. ;
  468. ; Write the PCI Config Address to the address port
  469. ;
  470. xchg eax, ebx
  471. mov dx, PCI_ADDRESS_PORT
  472. out dx, eax
  473. xchg eax, ebx
  474. ;
  475. ; Write the PCI DWORD Data to the data port
  476. ;
  477. mov dx, PCI_DATA_PORT
  478. out dx, eax
  479. RET32
  480. stackless_PCIConfig_Write ENDP
  481. ;----------------------------------------------------------------------------
  482. ;
  483. ; Procedure: stackless_PCIConfig_Read
  484. ;
  485. ; Input: esp - return address
  486. ; ebx - PCI Config Address
  487. ;
  488. ; Output: eax - Data read
  489. ;
  490. ; Destroys:
  491. ; eax
  492. ; dx
  493. ;
  494. ; Description:
  495. ; Perform a DWORD PCI Configuration read
  496. ;
  497. ;----------------------------------------------------------------------------
  498. stackless_PCIConfig_Read PROC NEAR C PUBLIC
  499. ;
  500. ; Write the PCI Config Address to the address port
  501. ;
  502. xchg eax, ebx
  503. mov dx, PCI_ADDRESS_PORT
  504. out dx, eax
  505. xchg eax, ebx
  506. ;
  507. ; Read the PCI DWORD Data from the data port
  508. ;
  509. mov dx, PCI_DATA_PORT
  510. in eax, dx
  511. RET32
  512. stackless_PCIConfig_Read ENDP
  513. ;
  514. ; ROM-based Global-Descriptor Table for the Tiano PEI Phase
  515. ;
  516. align 16
  517. PUBLIC BootGdtTable
  518. ;
  519. ; GDT[0]: 0x00: Null entry, never used.
  520. ;
  521. NULL_SEL equ $ - GDT_BASE ; Selector [0]
  522. GDT_BASE:
  523. BootGdtTable DD 0
  524. DD 0
  525. ;
  526. ; Linear data segment descriptor
  527. ;
  528. LINEAR_SEL equ $ - GDT_BASE ; Selector [0x8]
  529. DW 0FFFFh ; limit 0xFFFF
  530. DW 0 ; base 0
  531. DB 0
  532. DB 092h ; present, ring 0, data, expand-up, writable
  533. DB 0CFh ; page-granular, 32-bit
  534. DB 0
  535. ;
  536. ; Linear code segment descriptor
  537. ;
  538. LINEAR_CODE_SEL equ $ - GDT_BASE ; Selector [0x10]
  539. DW 0FFFFh ; limit 0xFFFF
  540. DW 0 ; base 0
  541. DB 0
  542. DB 09Bh ; present, ring 0, data, expand-up, not-writable
  543. DB 0CFh ; page-granular, 32-bit
  544. DB 0
  545. ;
  546. ; System data segment descriptor
  547. ;
  548. SYS_DATA_SEL equ $ - GDT_BASE ; Selector [0x18]
  549. DW 0FFFFh ; limit 0xFFFF
  550. DW 0 ; base 0
  551. DB 0
  552. DB 093h ; present, ring 0, data, expand-up, not-writable
  553. DB 0CFh ; page-granular, 32-bit
  554. DB 0
  555. ;
  556. ; System code segment descriptor
  557. ;
  558. SYS_CODE_SEL equ $ - GDT_BASE ; Selector [0x20]
  559. DW 0FFFFh ; limit 0xFFFF
  560. DW 0 ; base 0
  561. DB 0
  562. DB 09Ah ; present, ring 0, data, expand-up, writable
  563. DB 0CFh ; page-granular, 32-bit
  564. DB 0
  565. ;
  566. ; Spare segment descriptor
  567. ;
  568. SYS16_CODE_SEL equ $ - GDT_BASE ; Selector [0x28]
  569. DW 0FFFFh ; limit 0xFFFF
  570. DW 0 ; base 0
  571. DB 0Fh
  572. DB 09Bh ; present, ring 0, code, expand-up, writable
  573. DB 00h ; byte-granular, 16-bit
  574. DB 0
  575. ;
  576. ; Spare segment descriptor
  577. ;
  578. SYS16_DATA_SEL equ $ - GDT_BASE ; Selector [0x30]
  579. DW 0FFFFh ; limit 0xFFFF
  580. DW 0 ; base 0
  581. DB 0
  582. DB 093h ; present, ring 0, data, expand-up, not-writable
  583. DB 00h ; byte-granular, 16-bit
  584. DB 0
  585. ;
  586. ; Spare segment descriptor
  587. ;
  588. SPARE5_SEL equ $ - GDT_BASE ; Selector [0x38]
  589. DW 0 ; limit 0xFFFF
  590. DW 0 ; base 0
  591. DB 0
  592. DB 0 ; present, ring 0, data, expand-up, writable
  593. DB 0 ; page-granular, 32-bit
  594. DB 0
  595. GDT_SIZE EQU $ - BootGDTtable ; Size, in bytes
  596. ;
  597. ; GDT Descriptor
  598. ;
  599. GdtDesc: ; GDT descriptor
  600. DW GDT_SIZE - 1 ; GDT limit
  601. DD OFFSET BootGdtTable ; GDT base address
  602. ProtectedModeEntryLinearAddress LABEL FWORD
  603. ProtectedModeEntryLinearOffset LABEL DWORD
  604. DD OFFSET ProtectedModeEntryPoint ; Offset of our 32 bit code
  605. DW LINEAR_CODE_SEL
  606. END