SocUnit.c 3.4 KB

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  1. /** @file
  2. System On Chip Unit (SOCUnit) routines.
  3. Copyright (c) 2013-2015 Intel Corporation.
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include "CommonHeader.h"
  7. /** Early initialisation of the SOC Unit
  8. @retval EFI_SUCCESS Operation success.
  9. **/
  10. EFI_STATUS
  11. EFIAPI
  12. SocUnitEarlyInitialisation (
  13. VOID
  14. )
  15. {
  16. UINT32 NewValue;
  17. //
  18. // Set the mixer load resistance
  19. //
  20. NewValue = QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0);
  21. NewValue &= OCFGPIMIXLOAD_1_0_MASK;
  22. QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0, NewValue);
  23. NewValue = QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1);
  24. NewValue &= OCFGPIMIXLOAD_1_0_MASK;
  25. QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1, NewValue);
  26. return EFI_SUCCESS;
  27. }
  28. /** Tasks to release PCI controller from reset pre wait for PLL Lock.
  29. @retval EFI_SUCCESS Operation success.
  30. **/
  31. EFI_STATUS
  32. EFIAPI
  33. SocUnitReleasePcieControllerPreWaitPllLock (
  34. IN CONST EFI_PLATFORM_TYPE PlatformType
  35. )
  36. {
  37. UINT32 NewValue;
  38. //
  39. // Assert PERST# and validate time assertion time.
  40. //
  41. PlatformPERSTAssert (PlatformType);
  42. ASSERT (PCIEXP_PERST_MIN_ASSERT_US <= (PCIEXP_DELAY_US_POST_CMNRESET_RESET + PCIEXP_DELAY_US_WAIT_PLL_LOCK + PCIEXP_DELAY_US_POST_SBI_RESET));
  43. //
  44. // PHY Common lane reset.
  45. //
  46. NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);
  47. NewValue |= SOCCLKEN_CONFIG_PHY_I_CMNRESET_L;
  48. QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);
  49. //
  50. // Wait post common lane reset.
  51. //
  52. MicroSecondDelay (PCIEXP_DELAY_US_POST_CMNRESET_RESET);
  53. //
  54. // PHY Sideband interface reset.
  55. // Controller main reset
  56. //
  57. NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);
  58. NewValue |= (SOCCLKEN_CONFIG_SBI_RST_100_CORE_B | SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L);
  59. QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);
  60. return EFI_SUCCESS;
  61. }
  62. /** Tasks to release PCI controller from reset after PLL has locked
  63. @retval EFI_SUCCESS Operation success.
  64. **/
  65. EFI_STATUS
  66. EFIAPI
  67. SocUnitReleasePcieControllerPostPllLock (
  68. IN CONST EFI_PLATFORM_TYPE PlatformType
  69. )
  70. {
  71. UINT32 NewValue;
  72. //
  73. // Controller sideband interface reset.
  74. //
  75. NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);
  76. NewValue |= SOCCLKEN_CONFIG_SBI_BB_RST_B;
  77. QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);
  78. //
  79. // Wait post sideband interface reset.
  80. //
  81. MicroSecondDelay (PCIEXP_DELAY_US_POST_SBI_RESET);
  82. //
  83. // Deassert PERST#.
  84. //
  85. PlatformPERSTDeAssert (PlatformType);
  86. //
  87. // Wait post de assert PERST#.
  88. //
  89. MicroSecondDelay (PCIEXP_DELAY_US_POST_PERST_DEASSERT);
  90. //
  91. // Controller primary interface reset.
  92. //
  93. NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG);
  94. NewValue |= SOCCLKEN_CONFIG_BB_RST_B;
  95. QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue);
  96. return EFI_SUCCESS;
  97. }