Fadt2.0.aslc 5.5 KB

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  1. /** @file
  2. This file describes the contents of the ACPI Fixed ACPI Description Table
  3. (FADT). Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h.
  4. All changes to the FADT contents should be done in this file.
  5. Copyright (c) 2013-2015 Intel Corporation.
  6. SPDX-License-Identifier: BSD-2-Clause-Patent
  7. **/
  8. #include "Fadt.h"
  9. EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE FADT = {
  10. {
  11. EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
  12. sizeof (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE),
  13. EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
  14. 0, // to make sum of entire table == 0
  15. {EFI_ACPI_OEM_ID}, // OEMID is a 6 bytes long field
  16. EFI_ACPI_OEM_TABLE_ID,// OEM table identification(8 bytes long)
  17. EFI_ACPI_OEM_REVISION,// OEM revision number
  18. EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID
  19. EFI_ACPI_CREATOR_REVISION // ASL compiler revision number
  20. },
  21. 0, // Physical addesss of FACS
  22. 0, // Physical address of DSDT
  23. RESERVED, // reserved
  24. PM_PROFILE, // Preferred powermanagement profile
  25. SCI_INT_VECTOR, // System vector of SCI interrupt
  26. ACPI_RUNTIME_UPDATE, // Port address of SMI command port
  27. ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI
  28. ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI
  29. S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state
  30. RESERVED, // reserved - must be zero
  31. ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 1a Event Reg Blk
  32. PM1b_EVT_BLK_ADDRESS, // Port address of Power Mgt 1b Event Reg Blk
  33. ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 1a Ctrl Reg Blk
  34. PM1b_CNT_BLK_ADDRESS, // Port address of Power Mgt 1b Ctrl Reg Blk
  35. ACPI_RUNTIME_UPDATE, // Port address of Power Mgt 2 Ctrl Reg Blk
  36. ACPI_RUNTIME_UPDATE, // Port address of Power Mgt Timer Ctrl Reg Blk
  37. ACPI_RUNTIME_UPDATE, // Port addr of General Purpose Event 0 Reg Blk
  38. GPE1_BLK_ADDRESS, // Port addr of General Purpose Event 1 Reg Blk
  39. PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk
  40. PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk
  41. PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk
  42. PM_TM_LEN, // Byte Length of ports at pm_tm_blk
  43. GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk
  44. GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk
  45. GPE1_BASE, // offset in gpe model where gpe1 events start
  46. RESERVED, // reserved
  47. P_LVL2_LAT, // worst case HW latency to enter/exit C2 state
  48. P_LVL3_LAT, // worst case HW latency to enter/exit C3 state
  49. FLUSH_SIZE, // Size of area read to flush caches
  50. FLUSH_STRIDE, // Stride used in flushing caches
  51. DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg
  52. DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg
  53. DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM
  54. MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM
  55. CENTURY, // index to century in RTC CMOS RAM
  56. IAPC_BOOT_ARCH, // IA-PC Boot Architecture Flags
  57. RESERVED, // reserved
  58. FLAG2, // Fixed feature flags
  59. {
  60. RESET_REG_ADDRESS_SPACE_ID, // Address of the reset register
  61. RESET_REG_BIT_WIDTH,
  62. RESET_REG_BIT_OFFSET,
  63. RESERVED,
  64. RESET_REG_ADDRESS
  65. },
  66. RESET_VALUE, // Value to write to the RESET_REG port
  67. {
  68. RESERVED,
  69. RESERVED,
  70. RESERVED
  71. },
  72. 0, // 64Bit physical addesss of FACS
  73. 0, // 64Bit physical address of DSDT
  74. {
  75. PM1a_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Event Reg Blk
  76. PM1a_EVT_BLK_BIT_WIDTH,
  77. PM1a_EVT_BLK_BIT_OFFSET,
  78. RESERVED,
  79. ACPI_RUNTIME_UPDATE
  80. },
  81. {
  82. PM1b_EVT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Event Reg Blk
  83. PM1b_EVT_BLK_BIT_WIDTH,
  84. PM1b_EVT_BLK_BIT_OFFSET,
  85. RESERVED,
  86. PM1b_EVT_BLK_ADDRESS
  87. },
  88. {
  89. PM1a_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1a Ctrl Reg Blk
  90. PM1a_CNT_BLK_BIT_WIDTH,
  91. PM1a_CNT_BLK_BIT_OFFSET,
  92. RESERVED,
  93. ACPI_RUNTIME_UPDATE
  94. },
  95. {
  96. PM1b_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 1b Ctrl Reg Blk
  97. PM1b_CNT_BLK_BIT_WIDTH,
  98. PM1b_CNT_BLK_BIT_OFFSET,
  99. RESERVED,
  100. PM1b_CNT_BLK_ADDRESS
  101. },
  102. {
  103. PM2_CNT_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt 2 Ctrl Reg Blk
  104. PM2_CNT_BLK_BIT_WIDTH,
  105. PM2_CNT_BLK_BIT_OFFSET,
  106. RESERVED,
  107. ACPI_RUNTIME_UPDATE
  108. },
  109. {
  110. PM_TMR_BLK_ADDRESS_SPACE_ID, // Extended Port address of Power Mgt Timer Ctrl Reg Blk
  111. PM_TMR_BLK_BIT_WIDTH,
  112. PM_TMR_BLK_BIT_OFFSET,
  113. RESERVED,
  114. ACPI_RUNTIME_UPDATE
  115. },
  116. {
  117. GPE0_BLK_ADDRESS_SPACE_ID, // Extended Port address of General Purpose Event 0 Reg Blk
  118. GPE0_BLK_BIT_WIDTH,
  119. GPE0_BLK_BIT_OFFSET,
  120. RESERVED,
  121. ACPI_RUNTIME_UPDATE
  122. },
  123. {
  124. GPE1_BLK_ADDRESS_SPACE_ID, // Extended Port address of General Purpose Event 1 Reg Blk
  125. GPE1_BLK_BIT_WIDTH,
  126. GPE1_BLK_BIT_OFFSET,
  127. RESERVED,
  128. GPE1_BLK_ADDRESS
  129. }
  130. };
  131. VOID*
  132. ReferenceAcpiTable (
  133. VOID
  134. )
  135. {
  136. //
  137. // Reference the table being generated to prevent the optimizer from removing the
  138. // data structure from the exeutable
  139. //
  140. return (VOID*)&FADT;
  141. }