Fadt1.0.aslc 3.5 KB

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  1. /** @file
  2. This file describes the contents of the ACPI Fixed ACPI Description Table
  3. (FADT). Some additional ACPI values are defined in Acpi1_0.h and Acpi2_0.h.
  4. All changes to the FADT contents should be done in this file.
  5. Copyright (c) 2013-2015 Intel Corporation.
  6. SPDX-License-Identifier: BSD-2-Clause-Patent
  7. **/
  8. #include "Fadt.h"
  9. EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FADT = {
  10. EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
  11. sizeof (EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE),
  12. EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
  13. 0, // to make sum of entire table == 0
  14. EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field
  15. EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)
  16. EFI_ACPI_OEM_REVISION, // OEM revision number
  17. EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID
  18. EFI_ACPI_CREATOR_REVISION, // ASL compiler revision number
  19. 0, // Physical addesss of FACS
  20. 0, // Physical address of DSDT
  21. INT_MODEL, // System Interrupt Model
  22. RESERVED, // reserved
  23. SCI_INT_VECTOR, // System vector of SCI interrupt
  24. SMI_CMD_IO_PORT, // Port address of SMI command port
  25. ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI
  26. ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI
  27. S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state
  28. RESERVED, // reserved - must be zero
  29. PM1a_EVT_BLK_ADDRESS, // Port address of Power Mgt 1a Event Reg Blk
  30. PM1b_EVT_BLK_ADDRESS, // Port address of Power Mgt 1b Event Reg Blk
  31. PM1a_CNT_BLK_ADDRESS, // Port address of Power Mgt 1a Ctrl Reg Blk
  32. PM1b_CNT_BLK_ADDRESS, // Port address of Power Mgt 1b Ctrl Reg Blk
  33. PM2_CNT_BLK_ADDRESS, // Port address of Power Mgt 2 Ctrl Reg Blk
  34. PM_TMR_BLK_ADDRESS, // Port address of Power Mgt Timer Ctrl Reg Blk
  35. GPE0_BLK_ADDRESS, // Port addr of General Purpose Event 0 Reg Blk
  36. GPE1_BLK_ADDRESS, // Port addr of General Purpose Event 1 Reg Blk
  37. PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk
  38. PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk
  39. PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk
  40. PM_TM_LEN, // Byte Length of ports at pm_tm_blk
  41. GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk
  42. GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk
  43. GPE1_BASE, // offset in gpe model where gpe1 events start
  44. RESERVED, // reserved
  45. P_LVL2_LAT, // worst case HW latency to enter/exit C2 state
  46. P_LVL3_LAT, // worst case HW latency to enter/exit C3 state
  47. FLUSH_SIZE, // Size of area read to flush caches
  48. FLUSH_STRIDE, // Stride used in flushing caches
  49. DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg
  50. DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg
  51. DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM
  52. MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM
  53. CENTURY, // index to century in RTC CMOS RAM
  54. RESERVED, // reserved
  55. RESERVED, // reserved
  56. RESERVED, // reserved
  57. FLAG
  58. };
  59. VOID*
  60. ReferenceAcpiTable (
  61. VOID
  62. )
  63. {
  64. //
  65. // Reference the table being generated to prevent the optimizer from removing the
  66. // data structure from the exeutable
  67. //
  68. return (VOID*)&FADT;
  69. }