Platform.asl 9.6 KB

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  1. /** @file
  2. Contains root level name space objects for the platform
  3. Copyright (c) 2013-2019 Intel Corporation.
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. //
  7. // OS TYPE DEFINITION
  8. //
  9. #define WINDOWS_XP 0x01
  10. #define WINDOWS_XP_SP1 0x02
  11. #define WINDOWS_XP_SP2 0x04
  12. #define WINDOWS_2003 0x08
  13. #define WINDOWS_Vista 0x10
  14. #define WINDOWS_WIN7 0x11
  15. #define WINDOWS_WIN8 0x12
  16. #define WINDOWS_WIN8_1 0x13
  17. #define LINUX 0xF0
  18. //
  19. // GPIO Interrupt Connection Resource Descriptor (GpioInt) usage.
  20. // GpioInt() descriptors maybe used in this file and included .asi files.
  21. //
  22. // The mapping below was provided by the first OS user that requested
  23. // GpioInt() support.
  24. // Other OS users that need GpioInt() support must use the following mapping.
  25. //
  26. #define QUARK_GPIO8_MAPPING 0x00
  27. #define QUARK_GPIO9_MAPPING 0x01
  28. #define QUARK_GPIO_SUS0_MAPPING 0x02
  29. #define QUARK_GPIO_SUS1_MAPPING 0x03
  30. #define QUARK_GPIO_SUS2_MAPPING 0x04
  31. #define QUARK_GPIO_SUS3_MAPPING 0x05
  32. #define QUARK_GPIO_SUS4_MAPPING 0x06
  33. #define QUARK_GPIO_SUS5_MAPPING 0x07
  34. #define QUARK_GPIO0_MAPPING 0x08
  35. #define QUARK_GPIO1_MAPPING 0x09
  36. #define QUARK_GPIO2_MAPPING 0x0A
  37. #define QUARK_GPIO3_MAPPING 0x0B
  38. #define QUARK_GPIO4_MAPPING 0x0C
  39. #define QUARK_GPIO5_MAPPING 0x0D
  40. #define QUARK_GPIO6_MAPPING 0x0E
  41. #define QUARK_GPIO7_MAPPING 0x0F
  42. DefinitionBlock (
  43. "Platform.aml",
  44. "DSDT",
  45. 1,
  46. "INTEL ",
  47. "QuarkNcS",
  48. 3)
  49. {
  50. //
  51. // Global Variables
  52. //
  53. Name(\GPIC, 0x0)
  54. //
  55. // Port 80
  56. //
  57. OperationRegion (DBG0, SystemIO, 0x80, 1)
  58. Field (DBG0, ByteAcc, NoLock, Preserve)
  59. { IO80,8 }
  60. //
  61. // Access CMOS range
  62. //
  63. OperationRegion (ACMS, SystemIO, 0x72, 2)
  64. Field (ACMS, ByteAcc, NoLock, Preserve)
  65. { INDX, 8, DATA, 8 }
  66. //
  67. // Global NVS Memory Block
  68. //
  69. OperationRegion (MNVS, SystemMemory, 0xFFFF0000, 512)
  70. Field (MNVS, ByteAcc, NoLock, Preserve)
  71. {
  72. OSTP, 32,
  73. CFGD, 32,
  74. HPEA, 32, // HPET Enabled ?
  75. P1BB, 32, // Pm1blkIoBaseAddress;
  76. PBAB, 32, // PmbaIoBaseAddress;
  77. GP0B, 32, // Gpe0blkIoBaseAddress;
  78. GPAB, 32, // GbaIoBaseAddress;
  79. SMBB, 32, // SmbaIoBaseAddress;
  80. NRV1, 32, // GNVS reserved field 1.
  81. WDTB, 32, // WdtbaIoBaseAddress;
  82. HPTB, 32, // HpetBaseAddress;
  83. HPTS, 32, // HpetSize;
  84. PEXB, 32, // PciExpressBaseAddress;
  85. PEXS, 32, // PciExpressSize;
  86. RCBB, 32, // RcbaMmioBaseAddress;
  87. RCBS, 32, // RcbaMmioSize;
  88. APCB, 32, // IoApicBaseAddress;
  89. APCS, 32, // IoApicSize;
  90. TPMP, 32, // TpmPresent ?
  91. DBGP, 32, // DBG2 Present?
  92. PTYP, 32, // Set to one of EFI_PLATFORM_TYPE enums.
  93. ALTS, 32, // Use alternate I2c SLA addresses.
  94. }
  95. OperationRegion (GPEB, SystemIO, 0x1100, 0x40) //GPE Block
  96. Field (GPEB, AnyAcc, NoLock, Preserve)
  97. {
  98. Offset(0x10),
  99. SMIE, 32, // SMI Enable
  100. SMIS, 32, // SMI Status
  101. }
  102. //
  103. // Processor Objects
  104. //
  105. Scope(\_PR) {
  106. //
  107. // IO base will be updated at runtime with search key "PRIO"
  108. //
  109. Processor (CPU0, 0x01, 0x4F495250, 0x06) {}
  110. }
  111. //
  112. // System Sleep States
  113. //
  114. Name (\_S0,Package (){0,0,0,0})
  115. Name (\_S3,Package (){5,0,0,0})
  116. Name (\_S4,Package (){6,0,0,0})
  117. Name (\_S5,Package (){7,0,0,0})
  118. //
  119. // General Purpose Event
  120. //
  121. Scope(\_GPE)
  122. {
  123. //
  124. // EGPE generated GPE
  125. //
  126. Method(_L0D, 0x0, NotSerialized)
  127. {
  128. //
  129. // Check EGPE for this wake event
  130. //
  131. Notify (\_SB.SLPB, 0x02)
  132. }
  133. //
  134. // GPIO generated GPE
  135. //
  136. Method(_L0E, 0x0, NotSerialized)
  137. {
  138. //
  139. // Check GPIO for this wake event
  140. //
  141. Notify (\_SB.PWRB, 0x02)
  142. }
  143. //
  144. // SCLT generated GPE
  145. //
  146. Method(_L0F, 0x0, NotSerialized)
  147. {
  148. //
  149. // Check SCLT for this wake event
  150. //
  151. Notify (\_SB.PCI0.SDIO, 0x02)
  152. Notify (\_SB.PCI0.URT0, 0x02)
  153. Notify (\_SB.PCI0.USBD, 0x02)
  154. Notify (\_SB.PCI0.EHCI, 0x02)
  155. Notify (\_SB.PCI0.OHCI, 0x02)
  156. Notify (\_SB.PCI0.URT1, 0x02)
  157. Notify (\_SB.PCI0.ENT0, 0x02)
  158. Notify (\_SB.PCI0.ENT1, 0x02)
  159. Notify (\_SB.PCI0.SPI0, 0x02)
  160. Notify (\_SB.PCI0.SPI1, 0x02)
  161. Notify (\_SB.PCI0.GIP0, 0x02)
  162. }
  163. //
  164. // Remote Management Unit generated GPE
  165. //
  166. Method(_L10, 0x0, NotSerialized)
  167. {
  168. //
  169. // Check Remote Management Unit for this wake event.
  170. //
  171. }
  172. //
  173. // PCIE generated GPE
  174. //
  175. Method(_L11, 0x0, NotSerialized)
  176. {
  177. //
  178. // Check PCIE for this wake event
  179. //
  180. Notify (\_SB.PCI0.PEX0, 0x02)
  181. Notify (\_SB.PCI0.PEX1, 0x02)
  182. }
  183. }
  184. //
  185. // define Sleeping button as mentioned in ACPI spec 2.0
  186. //
  187. Device (\_SB.SLPB)
  188. {
  189. Name (_HID, EISAID ("PNP0C0E"))
  190. Method (_PRW, 0, NotSerialized)
  191. {
  192. Return (Package (0x02) {0x0D,0x04})
  193. }
  194. }
  195. //
  196. // define Power Button
  197. //
  198. Device (\_SB.PWRB)
  199. {
  200. Name (_HID, EISAID ("PNP0C0C"))
  201. Method (_PRW, 0, NotSerialized)
  202. {
  203. Return (Package (0x02) {0x0E,0x04})
  204. }
  205. }
  206. //
  207. // System Wake up
  208. //
  209. Method(_WAK, 1, Serialized)
  210. {
  211. // Do nothing here
  212. Return (0)
  213. }
  214. //
  215. // System sleep down
  216. //
  217. Method (_PTS, 1, NotSerialized)
  218. {
  219. // Get ready for S3 sleep
  220. if (Lequal(Arg0,3))
  221. {
  222. Store(0xffffffff,SMIS) // clear SMI status
  223. Store(SMIE, Local0) // SMI Enable
  224. Or(Local0,0x4,SMIE) // Generate SMI on sleep
  225. }
  226. }
  227. //
  228. // Determing PIC mode
  229. //
  230. Method(\_PIC, 1, NotSerialized)
  231. {
  232. Store(Arg0,\GPIC)
  233. }
  234. //
  235. // System Bus
  236. //
  237. Scope(\_SB)
  238. {
  239. Device(PCI0)
  240. {
  241. Name(_HID,EISAID ("PNP0A08")) // PCI Express Root Bridge
  242. Name(_CID,EISAID ("PNP0A03")) // Compatible PCI Root Bridge
  243. Name(_ADR,0x00000000) // Device (HI WORD)=0, Func (LO WORD)=0
  244. Method (_INI)
  245. {
  246. Store(LINUX, OSTP) // Set the default os is Linux
  247. If (CondRefOf (_OSI))
  248. {
  249. //
  250. //_OSI is supported, so it is WinXp or Win2003Server
  251. //
  252. If (\_OSI("Windows 2001"))
  253. {
  254. Store (WINDOWS_XP, OSTP)
  255. }
  256. If (\_OSI("Windows 2001 SP1"))
  257. {
  258. Store (WINDOWS_XP_SP1, OSTP)
  259. }
  260. If (\_OSI("Windows 2001 SP2"))
  261. {
  262. Store (WINDOWS_XP_SP2, OSTP)
  263. }
  264. If (\_OSI("Windows 2001.1"))
  265. {
  266. Store (WINDOWS_2003, OSTP)
  267. }
  268. If (\_OSI("Windows 2006"))
  269. {
  270. Store (WINDOWS_Vista, OSTP)
  271. }
  272. If (\_OSI("Windows 2009"))
  273. {
  274. Store (WINDOWS_WIN7, OSTP)
  275. }
  276. If (\_OSI("Windows 2012"))
  277. {
  278. Store (WINDOWS_WIN8, OSTP)
  279. }
  280. If (\_OSI("Windows 2013"))
  281. {
  282. Store (WINDOWS_WIN8_1, OSTP)
  283. }
  284. If (\_OSI("Linux"))
  285. {
  286. Store (LINUX, OSTP)
  287. }
  288. }
  289. }
  290. Include ("PciHostBridge.asi") // PCI0 Host bridge
  291. Include ("QNC.asi") // QNC miscellaneous
  292. Include ("PcieExpansionPrt.asi") // PCIe expansion bridges/devices
  293. Include ("QuarkSouthCluster.asi") // Quark South Cluster devices
  294. Include ("QNCLpc.asi") // LPC bridge device
  295. Include ("QNCApic.asi") // QNC I/O Apic device
  296. }
  297. //
  298. // Include asi files for I2C and SPI onboard devices.
  299. // Devices placed here instead of below relevant controllers.
  300. // Hardware topology information is maintained by the
  301. // ResourceSource arg to the I2CSerialBus/SPISerialBus macros
  302. // within the device asi files.
  303. //
  304. Include ("Tpm.asi") // TPM device.
  305. Include ("CY8C9540A.asi") // CY8C9540A 40Bit I/O Expander & EEPROM
  306. Include ("PCAL9555A.asi") // NXP PCAL9555A I/O expander.
  307. Include ("PCA9685.asi") // NXP PCA9685 PWM/LED controller.
  308. Include ("CAT24C08.asi") // ONSEMI CAT24C08 I2C 8KB EEPROM.
  309. Include ("AD7298.asi") // Analog devices AD7298 ADC.
  310. Include ("ADC108S102.asi") // TI ADC108S102 ADC.
  311. Include ("GpioClient.asi") // Software device to expose GPIO
  312. }
  313. }