PcieExpansionPrt.asi 4.5 KB

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  1. /** @file
  2. PCI express expansion ports
  3. Copyright (c) 2013-2015 Intel Corporation.
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #ifndef PcieExpansionPrt_asi
  7. #define PcieExpansionPrt_asi
  8. Device (PEX0) // PCI express bus bridged from [Bus 0, Device 23, Function 0]
  9. {
  10. Name(_ADR,0x00170000) // Device (HI WORD)=23, Func (LO WORD)=0
  11. Name(_PRW,Package(){0x11,0x03}) // GPE pin 0x11, Wake from S3 -- PCI PME#
  12. OperationRegion (PES0,PCI_Config,0x40,0xA0)
  13. Field (PES0, AnyAcc, NoLock, Preserve)
  14. {
  15. Offset(0x1A), // SLSTS - Slot Status Register
  16. ABP0, 1, // Bit 0, Attention Button Pressed
  17. , 2,
  18. PDC0, 1, // Bit 3, Presence Detect Changed
  19. , 2,
  20. PDS0, 1, // Bit 6, Presence Detect State
  21. , 1,
  22. LSC0, 1, // Bit 8, Link Active State Changed
  23. offset (0x20),
  24. , 16,
  25. PMS0, 1, // Bit 16, PME Status
  26. offset (0x98),
  27. , 30,
  28. HPE0, 1, // Bit 30, Hot Plug SCI Enable
  29. PCE0, 1, // Bit 31, Power Management SCI Enable.
  30. , 30,
  31. HPS0, 1, // Bit 30, Hot Plug SCI Status
  32. PCS0, 1, // Bit 31, Power Management SCI Status.
  33. }
  34. Method(_PRT,0,NotSerialized) {
  35. If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing
  36. {
  37. Return (
  38. Package()
  39. {
  40. // Port 0: INTA->PIRQE,INTB->PIRQF,INTC->PIRQG,INTD->PIRQH
  41. Package() {0x0000ffff, 0, \_SB_.PCI0.LPC.LNKE, 0}, // PCI Slot 1
  42. Package() {0x0000ffff, 1, \_SB_.PCI0.LPC.LNKF, 0},
  43. Package() {0x0000ffff, 2, \_SB_.PCI0.LPC.LNKG, 0},
  44. Package() {0x0000ffff, 3, \_SB_.PCI0.LPC.LNKH, 0},
  45. }
  46. )
  47. }
  48. else // IOAPIC Routing
  49. {
  50. Return (
  51. Package()
  52. {
  53. // Port 0: INTA->PIRQE,INTB->PIRQF,INTC->PIRQG,INTD->PIRQH
  54. Package() {0x0000ffff, 0, 0, 20}, // PCI Slot 1
  55. Package() {0x0000ffff, 1, 0, 21},
  56. Package() {0x0000ffff, 2, 0, 22},
  57. Package() {0x0000ffff, 3, 0, 23},
  58. }
  59. )
  60. }
  61. }
  62. }
  63. Device (PEX1) // PCI express bus bridged from [Bus 0, Device 23, Function 1]
  64. {
  65. Name(_ADR,0x00170001) // Device (HI WORD)=23, Func (LO WORD)=1
  66. Name(_PRW,Package(){0x11,0x03}) // GPE pin 0x11, Wake from S3 -- PCI PME#
  67. OperationRegion (PES1,PCI_Config,0x40,0xA0)
  68. Field (PES1, AnyAcc, NoLock, Preserve)
  69. {
  70. Offset(0x1A), // SLSTS - Slot Status Register
  71. ABP1, 1, // Bit 0, Attention Button Pressed
  72. , 2,
  73. PDC1, 1, // Bit 3, Presence Detect Changed
  74. , 2,
  75. PDS1, 1, // Bit 6, Presence Detect State
  76. , 1,
  77. LSC1, 1, // Bit 8, Link Active State Changed
  78. offset (0x20),
  79. , 16,
  80. PMS1, 1, // Bit 16, PME Status
  81. offset (0x98),
  82. , 30,
  83. HPE1, 1, // Bit 30, Hot Plug SCI Enable
  84. PCE1, 1, // Bit 31, Power Management SCI Enable.
  85. , 30,
  86. HPS1, 1, // Bit 30, Hot Plug SCI Status
  87. PCS1, 1, // Bit 31, Power Management SCI Status.
  88. }
  89. Method(_PRT,0,NotSerialized) {
  90. If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing
  91. {
  92. Return (
  93. Package()
  94. {
  95. // Port 1: INTA->PIRQF,INTB->PIRQG,INTC->PIRQH,INTD->PIRQE
  96. Package() {0x0000ffff, 0, \_SB_.PCI0.LPC.LNKF, 0},
  97. Package() {0x0000ffff, 1, \_SB_.PCI0.LPC.LNKG, 0},
  98. Package() {0x0000ffff, 2, \_SB_.PCI0.LPC.LNKH, 0},
  99. Package() {0x0000ffff, 3, \_SB_.PCI0.LPC.LNKE, 0},
  100. }
  101. )
  102. }
  103. else // IOAPIC Routing
  104. {
  105. Return (
  106. Package()
  107. {
  108. // Port 1: INTA->PIRQF,INTB->PIRQG,INTC->PIRQH,INTD->PIRQE
  109. Package() {0x0000ffff, 0, 0, 21},
  110. Package() {0x0000ffff, 1, 0, 22},
  111. Package() {0x0000ffff, 2, 0, 23},
  112. Package() {0x0000ffff, 3, 0, 20},
  113. }
  114. )
  115. }
  116. }
  117. }
  118. #endif