PciHostBridge.asi 6.3 KB

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  1. /** @file
  2. PCI Host Bridge Definitions
  3. Copyright (c) 2013-2015 Intel Corporation.
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. Name(PBRS, ResourceTemplate() {
  7. WORDBusNumber( //Bus number resource (0); the bridge produces bus numbers for its subsequent buses
  8. ResourceProducer, // bit 0 of general flags is 1
  9. MinFixed, // Range is fixed
  10. MaxFixed, // Range is fixed
  11. PosDecode, // PosDecode
  12. 0x0000, // Granularity
  13. 0x0000, // Min
  14. 0x001f, // Max
  15. 0x0000, // Translation
  16. 0x0020 // Range Length = Max-Min+1
  17. )
  18. WORDIO( //Consumed-and-produced resource (all I/O below CF8)
  19. ResourceProducer, // bit 0 of general flags is 0
  20. MinFixed, // Range is fixed
  21. MaxFixed, // Range is fixed
  22. PosDecode,
  23. EntireRange,
  24. 0x0000, // Granularity
  25. 0x0000, // Min
  26. 0x0cf7, // Max
  27. 0x0000, // Translation
  28. 0x0cf8 // Range Length
  29. )
  30. IO( //Consumed resource (CF8-CFF)
  31. Decode16,
  32. 0x0cf8,
  33. 0xcf8,
  34. 1,
  35. 8
  36. )
  37. WORDIO( //Consumed-and-produced resource (all I/O above CFF)
  38. ResourceProducer, // bit 0 of general flags is 0
  39. MinFixed, // Range is fixed
  40. MaxFixed, // Range is fixed
  41. PosDecode,
  42. EntireRange,
  43. 0x0000, // Granularity
  44. 0x0d00, // Min
  45. 0xffff, // Max
  46. 0x0000, // Translation
  47. 0xf300 // Range Length
  48. )
  49. DWORDMEMORY( // descriptor for dos area(0->0xa0000)
  50. ResourceProducer, // bit 0 of general flags is 0
  51. PosDecode,
  52. MinFixed, // Range is fixed
  53. MaxFixed, // Range is Fixed
  54. Cacheable,
  55. ReadWrite,
  56. 0x00000000, // Granularity
  57. 0x000a0000, // Min
  58. 0x000bffff, // Max
  59. 0x00000000, // Translation
  60. 0x00020000 // Range Length
  61. )
  62. DWORDMemory( // Consumed-and-produced resource for pci memory mapped memory
  63. ResourceProducer, // bit 0 of general flags is 0
  64. PosDecode, // positive Decode
  65. MinFixed, // Range is fixed
  66. MaxFixed, // Range is fixed
  67. Cacheable,
  68. ReadWrite,
  69. 0x00000000, // Granularity
  70. 0x00000000, // Min (calculated dynamically)
  71. 0xfebfffff, // Max = IO Apic base address - 1
  72. 0x00000000, // Translation
  73. 0xfec00000, // Range Length (calculated dynamically)
  74. , // Optional field left blank
  75. , // Optional field left blank
  76. MEM1 // Name declaration for this descriptor
  77. )
  78. }) // end of CRES Buffer
  79. Method(_CRS, 0x0, NotSerialized)
  80. {
  81. CreateDWordField(PBRS, \_SB.PCI0.MEM1._MIN, MMIN)
  82. CreateDWordField(PBRS, \_SB.PCI0.MEM1._MAX, MMAX)
  83. CreateDWordField(PBRS, \_SB.PCI0.MEM1._LEN, MLEN)
  84. // HMBOUND is PCI memory base
  85. And(MNRD(0x03, 0x08), 0xFFFFF000, MMIN)
  86. Add(Subtract(MMAX, MMIN), 1, MLEN)
  87. Return(PBRS)
  88. }
  89. // Message Nework Registers
  90. OperationRegion(MNR, PCI_Config, 0xD0, 0x10)
  91. Field(MNR, DWordAcc, NoLock, Preserve)
  92. {
  93. MCR, 32, // Message Control Register
  94. MDR, 32 // Message Data Register
  95. }
  96. // Message Nework Read Method
  97. // Arg0 = Port
  98. // Arg1 = RegAddress
  99. // return 32 bit register value
  100. Method(MNRD, 2, Serialized)
  101. {
  102. Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)
  103. Or(Local0, 0x100000F0, Local0)
  104. Store(Local0, MCR)
  105. Return(MDR)
  106. }
  107. // Message Nework Write Method
  108. // Arg0 = Port
  109. // Arg1 = RegAddress
  110. // Arg2 = 32 bit write value
  111. Method(MNWR, 3, Serialized)
  112. {
  113. Store(Arg2, MDR)
  114. Or(ShiftLeft(Arg0, 16), ShiftLeft(Arg1, 8), Local0)
  115. Or(Local0, 0x110000F0, Local0)
  116. Store(Local0, MCR)
  117. }
  118. Method(_PRT, 0, NotSerialized)
  119. {
  120. If (LEqual(\GPIC, Zero)) // 8259 Interrupt Routing
  121. {
  122. Return (
  123. Package()
  124. {
  125. // Bus 0, Device 20 - IOSFAHB Bridge
  126. Package() {0x0014ffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // INTA
  127. Package() {0x0014ffff, 1, \_SB.PCI0.LPC.LNKB, 0}, // INTB
  128. Package() {0x0014ffff, 2, \_SB.PCI0.LPC.LNKC, 0}, // INTC
  129. Package() {0x0014ffff, 3, \_SB.PCI0.LPC.LNKD, 0}, // INTD
  130. // Bus 0, Device 21 - IOSFAHB Bridge
  131. Package() {0x0015ffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // INTA
  132. Package() {0x0015ffff, 1, \_SB.PCI0.LPC.LNKB, 0}, // INTB
  133. Package() {0x0015ffff, 2, \_SB.PCI0.LPC.LNKC, 0}, // INTC
  134. Package() {0x0015ffff, 3, \_SB.PCI0.LPC.LNKD, 0}, // INTD
  135. // Bus 0, Device 23 - PCIe port 0
  136. Package() {0x0017ffff, 0, \_SB.PCI0.LPC.LNKE, 0}, // INTA
  137. Package() {0x0017ffff, 1, \_SB.PCI0.LPC.LNKF, 0}, // INTB
  138. Package() {0x0017ffff, 2, \_SB.PCI0.LPC.LNKG, 0}, // INTC
  139. Package() {0x0017ffff, 3, \_SB.PCI0.LPC.LNKH, 0}, // INTD
  140. // Bus 0, Device 31
  141. Package() {0x001fffff, 0, \_SB.PCI0.LPC.LNKA, 0}, // LPC Bridge
  142. }
  143. )
  144. }
  145. else {
  146. Return (
  147. Package()
  148. {
  149. // Bus 0, Device 20 - IOSFAHB Bridge
  150. Package() {0x0014ffff, 0, 0, 16}, // INTA
  151. Package() {0x0014ffff, 1, 0, 17}, // INTB
  152. Package() {0x0014ffff, 2, 0, 18}, // INTC
  153. Package() {0x0014ffff, 3, 0, 19}, // INTD
  154. // Bus 0, Device 21 - IOSFAHB Bridge
  155. Package() {0x0015ffff, 0, 0, 16}, // INTA
  156. Package() {0x0015ffff, 1, 0, 17}, // INTB
  157. Package() {0x0015ffff, 2, 0, 18}, // INTC
  158. Package() {0x0015ffff, 3, 0, 19}, // INTD
  159. // Bus 0, Device 23 - PCIe port 0
  160. Package() {0x0017ffff, 0, 0, 20}, // INTA
  161. Package() {0x0017ffff, 1, 0, 21}, // INTB
  162. Package() {0x0017ffff, 2, 0, 22}, // INTC
  163. Package() {0x0017ffff, 3, 0, 23}, // INTD
  164. // Bus 0, Device 31
  165. Package() {0x001fffff, 0, 0, 16}, // LPC Bridge
  166. }
  167. )
  168. }
  169. }