Cpu0Tst.asl 3.2 KB

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  1. /** @file
  2. CPU T-state control methods
  3. Copyright (c) 2013-2015 Intel Corporation.
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. DefinitionBlock (
  7. "CPU0TST.aml",
  8. "SSDT",
  9. 0x01,
  10. "SsgPmm",
  11. "Cpu0Tst",
  12. 0x0013
  13. )
  14. {
  15. External (PDC0, IntObj)
  16. External (CFGD, FieldUnitObj)
  17. External(\_PR.CPU0, DeviceObj)
  18. External(_PSS)
  19. Scope(\_PR.CPU0)
  20. {
  21. Method(_TPC,0)
  22. {
  23. Return(ZERO) // Return All States Available.
  24. }
  25. Name(TPTC, ResourceTemplate()
  26. {
  27. Memory32Fixed(ReadOnly, 0, 0, FIX1) // IO APIC
  28. })
  29. //
  30. // If OSPM is capable of direct access to on demand throttling MSR,
  31. // we use MSR method;otherwise we use IO method.
  32. //
  33. //
  34. // PDCx[2] = Indicates whether OSPM is capable of direct access to
  35. // on demand throttling MSR.
  36. //
  37. Method(_PTC, 0)
  38. {
  39. If(And(PDC0, 0x0004))
  40. {
  41. Return(Package() // MSR Method
  42. {
  43. ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},
  44. ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}
  45. }
  46. )
  47. }
  48. Return(Package() // IO Method
  49. {
  50. //
  51. // PM IO base ("PMBALVL0" will be updated at runtime)
  52. //
  53. ResourceTemplate(){Register(SystemIO, 4, 1, 0x304C564C41424D50)},
  54. ResourceTemplate(){Register(SystemIO, 4, 1, 0x304C564C41424D50)}
  55. }
  56. )
  57. }
  58. //
  59. // _TSS returned package for IO Method
  60. //
  61. Name(TSSI, Package()
  62. {
  63. Package(){100, 1000, 0, 0x00, 0}
  64. }
  65. )
  66. //
  67. // _TSS returned package for MSR Method
  68. //
  69. Name(TSSM, Package()
  70. {
  71. Package(){100, 1000, 0, 0x00, 0}
  72. }
  73. )
  74. Method(_TSS, 0)
  75. {
  76. //
  77. // If OSPM is capable of direct access to on demand throttling MSR,
  78. // we report TSSM;otherwise report TSSI.
  79. //
  80. If(And(PDC0, 0x0004))
  81. {
  82. Return(TSSM)
  83. }
  84. Return(TSSI)
  85. }
  86. Method(_TSD, 0)
  87. {
  88. //
  89. // If CMP is suppored, we report the dependency with two processors
  90. //
  91. If(LAnd(And(CFGD, 0x1000000), LNot(And(PDC0, 4))))
  92. {
  93. Return(Package()
  94. {
  95. Package()
  96. {
  97. 5, // # entries.
  98. 0, // Revision.
  99. 0, // Domain #.
  100. 0xFD, // Coord Type- SW_ANY
  101. 2 // # processors.
  102. }
  103. }
  104. )
  105. }
  106. //
  107. // Otherwise, we report the dependency with one processor
  108. //
  109. Return(Package()
  110. {
  111. Package()
  112. {
  113. 5, // # entries.
  114. 0, // Revision.
  115. 0, // Domain #.
  116. 0xFC, // Coord Type- SW_ALL
  117. 1 // # processors.
  118. }
  119. }
  120. )
  121. }
  122. }
  123. }