Armada80x0Db.dsc 7.4 KB

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  1. #Copyright (C) 2017 Marvell International Ltd.
  2. #
  3. #SPDX-License-Identifier: BSD-2-Clause-Patent
  4. #
  5. ################################################################################
  6. #
  7. # Defines Section - statements that will be processed to create a Makefile.
  8. #
  9. ################################################################################
  10. [Defines]
  11. PLATFORM_NAME = Armada80x0Db
  12. PLATFORM_GUID = 5cc803a0-9c42-498e-9086-e176d4a1f598
  13. PLATFORM_VERSION = 0.1
  14. DSC_SPECIFICATION = 0x0001001A
  15. OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH)
  16. SUPPORTED_ARCHITECTURES = AARCH64|ARM
  17. BUILD_TARGETS = DEBUG|RELEASE|NOOPT
  18. SKUID_IDENTIFIER = DEFAULT
  19. FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
  20. BOARD_DXE_FV_COMPONENTS = Platform/Marvell/Armada80x0Db/Armada80x0Db.fdf.inc
  21. #
  22. # Network definition
  23. #
  24. DEFINE NETWORK_IP6_ENABLE = FALSE
  25. DEFINE NETWORK_TLS_ENABLE = FALSE
  26. DEFINE NETWORK_HTTP_BOOT_ENABLE = FALSE
  27. DEFINE NETWORK_ISCSI_ENABLE = FALSE
  28. !include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
  29. !include MdePkg/MdeLibs.dsc.inc
  30. [Components.common]
  31. Silicon/Marvell/Armada7k8k/DeviceTree/Armada80x0Db.inf
  32. [Components.AARCH64]
  33. Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf
  34. [LibraryClasses.common]
  35. ArmadaBoardDescLib|Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoardDescLib.inf
  36. NonDiscoverableInitLib|Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
  37. ################################################################################
  38. #
  39. # Pcd Section - list of all EDK II PCD Entries defined by this Platform
  40. #
  41. ################################################################################
  42. [PcdsFixedAtBuild.common]
  43. #Platform description
  44. gMarvellTokenSpaceGuid.PcdProductPlatformName|"Armada 8040 DB"
  45. gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.4"
  46. #MPP
  47. gMarvellTokenSpaceGuid.PcdMppChipCount|3
  48. # APN806-A0 MPP SET
  49. gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
  50. gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
  51. gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
  52. gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
  53. gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
  54. # CP110 MPP SET - master
  55. gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
  56. gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
  57. gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
  58. gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
  59. gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
  60. gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
  61. gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0xFF, 0x7, 0x0, 0x7, 0xA, 0xA, 0x2, 0x2, 0x5 }
  62. gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x9, 0x9, 0x8, 0x8, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
  63. gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE }
  64. gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
  65. # CP110 MPP SET - slave
  66. gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
  67. gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
  68. gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
  69. gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 }
  70. gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0xFF, 0xFF, 0xFF }
  71. gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x8, 0x9, 0xA }
  72. gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0xA, 0x8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
  73. gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
  74. gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
  75. gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
  76. # I2C
  77. gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x50, 0x57, 0x21, 0x25 }
  78. gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x1, 0x1, 0x0, 0x0 }
  79. gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1, 0x0, 0x0, 0x1 }
  80. gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57, 0x50, 0x57 }
  81. gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0, 0x0, 0x1, 0x1 }
  82. gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000
  83. gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
  84. gMarvellTokenSpaceGuid.PcdI2cBusCount|2
  85. #SPI
  86. gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680
  87. gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
  88. gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
  89. gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
  90. gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
  91. #ComPhy
  92. gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
  93. # ComPhy0
  94. # 0: PCIE0 5 Gbps
  95. # 1: SATA0 5 Gbps
  96. # 2: SFI 10.31 Gbps
  97. # 3: SATA1 5 Gbps
  98. # 4: USB_HOST1 5 Gbps
  99. # 5: PCIE2 5 Gbps
  100. gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_SATA0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) }
  101. gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) }
  102. # ComPhy1
  103. # 0: PCIE0 5 Gbps
  104. # 1: SATA0 5 Gbps
  105. # 2: SFI 10.31 Gbps
  106. # 3: SATA1 5 Gbps
  107. # 4: PCIE1 5 Gbps
  108. # 5: PCIE2 5 Gbps
  109. gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_SATA2), $(CP_SFI), $(CP_SATA3), $(CP_PCIE1), $(CP_PCIE2) }
  110. gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) }
  111. #UtmiPhy
  112. gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 }
  113. gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
  114. #MDIO
  115. gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x1 }
  116. #PHY
  117. gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x1 }
  118. gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
  119. gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x1, 0x0 }
  120. gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
  121. #NET
  122. gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x3, 0x0, 0x2 }
  123. gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
  124. gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_1000) }
  125. gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_SFI), $(PHY_RGMII) }
  126. gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0x1 }
  127. gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x1, 0x1 }
  128. gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x2, 0x0, 0x1 }
  129. gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
  130. #PciEmulation
  131. gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 }
  132. gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
  133. gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
  134. #RTC
  135. gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF4284000