Cn9130DbA.dsc.inc 4.1 KB

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  1. ## @file
  2. # Component description file for the CN9130 Development Board (variant A)
  3. #
  4. # Copyright (c) 2019 Marvell International Ltd.<BR>
  5. #
  6. # SPDX-License-Identifier: BSD-2-Clause-Patent
  7. #
  8. ##
  9. ################################################################################
  10. #
  11. # Pcd Section - list of all EDK II PCD Entries defined by this Platform
  12. #
  13. ################################################################################
  14. [PcdsFixedAtBuild.common]
  15. # CP115 count
  16. gMarvellTokenSpaceGuid.PcdMaxCpCount|1
  17. # MPP
  18. gMarvellTokenSpaceGuid.PcdMppChipCount|2
  19. # APN807 MPP
  20. gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
  21. gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
  22. gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
  23. gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
  24. gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
  25. # CP115 #0 MPP
  26. gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
  27. gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
  28. gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
  29. gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 }
  30. gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x0, 0x3, 0x3, 0x3, 0x3, 0x1, 0x1, 0x1 }
  31. gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x3, 0xA }
  32. gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xA, 0x3, 0x7, 0x6, 0x7, 0x2, 0x2, 0x2, 0x2, 0x1 }
  33. gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
  34. gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE }
  35. gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
  36. # I2C
  37. gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x21 }
  38. gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }
  39. gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 }
  40. gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000
  41. gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
  42. # SPI
  43. gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680
  44. gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
  45. gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
  46. gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
  47. gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
  48. # ComPhy
  49. gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }
  50. # ComPhy0
  51. # 0: PCIE0 5 Gbps
  52. # 1: PCIE0 5 Gbps
  53. # 2: PCIE0 5 Gbps
  54. # 3: PCIE0 5 Gbps
  55. # 4: SFI 10.31 Gbps
  56. # 5: SATA1 5 Gbps
  57. gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
  58. gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
  59. # UtmiPhy
  60. gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }
  61. gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
  62. # MDIO
  63. gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
  64. # PHY
  65. gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x0 }
  66. gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
  67. gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0, 0x1 }
  68. gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
  69. # NET
  70. gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }
  71. gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0 }
  72. gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_1000) }
  73. gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_RGMII) }
  74. gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0x1 }
  75. gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 }
  76. gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }
  77. gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }
  78. # NonDiscoverableDevices
  79. gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 }
  80. gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 }
  81. gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
  82. # RTC
  83. gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000
  84. # Variable store
  85. gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|FALSE