PeiAspireVn7Dash572GInitPreMemLib.c 7.6 KB

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  1. /** @file
  2. Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #include <PiPei.h>
  6. #include <Library/DebugLib.h>
  7. #include <Library/IoLib.h>
  8. #include <Library/MemoryAllocationLib.h>
  9. #include <Library/PcdLib.h>
  10. #include <Library/PchCycleDecodingLib.h>
  11. #include <Library/PchResetLib.h>
  12. #include <Library/SiliconInitLib.h>
  13. #include <Library/TimerLib.h>
  14. #include <Library/PeiLib.h>
  15. #include <Library/GpioLib.h>
  16. #include <GpioPinsSklLp.h>
  17. #include <IndustryStandard/TpmPtp.h>
  18. #include <PchAccess.h>
  19. #include "PeiAspireVn7Dash572GInitLib.h"
  20. #include <ConfigBlock.h>
  21. #include <ConfigBlock/MemoryConfig.h>
  22. #ifndef STALL_ONE_MILLI_SECOND
  23. #define STALL_ONE_MILLI_SECOND 1000
  24. #endif
  25. //
  26. // Reference RCOMP resistors on motherboard - for Aspire VN7-572G
  27. //
  28. GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorAspireVn7Dash572G[SA_MRC_MAX_RCOMP] = { 121, 80, 100 };
  29. //
  30. // RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for Aspire VN7-572G
  31. //
  32. GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetAspireVn7Dash572G[SA_MRC_MAX_RCOMP_TARGETS] = { 100, 40, 40, 23, 40 };
  33. //
  34. // dGPU power GPIO definitions
  35. #define DGPU_PRESENT GPIO_SKL_LP_GPP_A20 /* Active low */
  36. #define DGPU_HOLD_RST GPIO_SKL_LP_GPP_B4 /* Active low */
  37. #define DGPU_PWR_EN GPIO_SKL_LP_GPP_B21 /* Active low */
  38. EFI_STATUS
  39. EFIAPI
  40. AspireVn7Dash572GBoardDetect (
  41. VOID
  42. );
  43. /**
  44. Aspire VN7-572G board configuration init function for PEI pre-memory phase.
  45. **/
  46. VOID
  47. AspireVn7Dash572GInitPreMem (
  48. VOID
  49. )
  50. {
  51. //
  52. // HSIO PTSS Table
  53. //
  54. PcdSet32S (PcdSpecificLpHsioPtssTable1, (UINTN) PchLpHsioPtss_AspireVn7Dash572G);
  55. PcdSet16S (PcdSpecificLpHsioPtssTable1Size, (UINTN) PchLpHsioPtss_AspireVn7Dash572G_Size);
  56. PcdSet32S (PcdSpecificLpHsioPtssTable2, (UINTN) PchLpHsioPtss_AspireVn7Dash572G);
  57. PcdSet16S (PcdSpecificLpHsioPtssTable2Size, (UINTN) PchLpHsioPtss_AspireVn7Dash572G_Size);
  58. //
  59. // DRAM related definition
  60. //
  61. PcdSet8S (PcdSaMiscUserBd, 5); // ULT/ULX/Mobile Halo
  62. PcdSet8S (PcdMrcCaVrefConfig, 2); // DDR4: "VREF_CA to CH_A and VREF_DQ_B to CH_B"
  63. // TODO: Clear Dq/Dqs?
  64. PcdSetBoolS (PcdMrcDqPinsInterleaved, TRUE);
  65. PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorAspireVn7Dash572G);
  66. PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetAspireVn7Dash572G);
  67. //
  68. // Example policy for DIMM slots implementation boards:
  69. // 1. Assign Smbus address of DIMMs and SpdData will be updated later
  70. // by reading from DIMM SPD.
  71. // 2. No need to apply hardcoded SpdData buffers here for such board.
  72. // Example:
  73. // PcdMrcSpdAddressTable0 = 0xA0
  74. // PcdMrcSpdAddressTable1 = 0xA2
  75. // PcdMrcSpdAddressTable2 = 0xA4
  76. // PcdMrcSpdAddressTable3 = 0xA6
  77. // PcdMrcSpdData = 0
  78. // PcdMrcSpdDataSize = 0
  79. //
  80. PcdSet8S (PcdMrcSpdAddressTable0, 0xA0);
  81. PcdSet8S (PcdMrcSpdAddressTable1, 0);
  82. PcdSet8S (PcdMrcSpdAddressTable2, 0xA4);
  83. PcdSet8S (PcdMrcSpdAddressTable3, 0);
  84. PcdSet32S (PcdMrcSpdData, 0);
  85. PcdSet16S (PcdMrcSpdDataSize, 0);
  86. }
  87. /**
  88. Configures GPIO before memory is ready.
  89. **/
  90. EFI_STATUS
  91. EFIAPI
  92. GpioInitPreMem (
  93. VOID
  94. )
  95. {
  96. EFI_STATUS Status;
  97. DEBUG ((DEBUG_INFO, "GpioInitPreMem() Start\n"));
  98. Status = GpioConfigurePads (mGpioTableAspireVn7Dash572G_earlySize, mGpioTableAspireVn7Dash572G_early);
  99. if (EFI_ERROR (Status)) {
  100. DEBUG ((DEBUG_ERROR, "Failed to configure early GPIOs!\n"));
  101. return EFI_DEVICE_ERROR;
  102. }
  103. DEBUG ((DEBUG_INFO, "GpioInitPreMem() End\n"));
  104. return EFI_SUCCESS;
  105. }
  106. /**
  107. Initialises the dGPU.
  108. **/
  109. VOID
  110. DgpuPowerOn (
  111. VOID
  112. )
  113. {
  114. UINT32 OutputVal;
  115. DEBUG ((DEBUG_INFO, "DgpuPowerOn() Start\n"));
  116. GpioGetOutputValue (DGPU_PRESENT, &OutputVal);
  117. if (!OutputVal) {
  118. DEBUG ((DEBUG_INFO, "dGPU present, enable power...\n"));
  119. GpioSetOutputValue (DGPU_HOLD_RST, 0); // Assert dGPU_HOLD_RST#
  120. MicroSecondDelay (2 * STALL_ONE_MILLI_SECOND);
  121. GpioSetOutputValue (DGPU_PWR_EN, 0); // Assert dGPU_PWR_EN#
  122. MicroSecondDelay (7 * STALL_ONE_MILLI_SECOND);
  123. GpioSetOutputValue (DGPU_HOLD_RST, 1); // Deassert dGPU_HOLD_RST#
  124. MicroSecondDelay (30 * STALL_ONE_MILLI_SECOND);
  125. } else {
  126. DEBUG ((DEBUG_INFO, "dGPU not present, disable power...\n"));
  127. GpioSetOutputValue (DGPU_HOLD_RST, 0); // Assert dGPU_HOLD_RST#
  128. GpioSetOutputValue (DGPU_PWR_EN, 1); // Deassert dGPU_PWR_EN#
  129. }
  130. DEBUG ((DEBUG_INFO, "DgpuPowerOn() End\n"));
  131. }
  132. /**
  133. Configure LPC.
  134. **/
  135. VOID
  136. LpcInit (
  137. VOID
  138. )
  139. {
  140. //
  141. // Program and Enable EC (sideband) Port Addresses and range
  142. //
  143. PchLpcGenIoRangeSet (0x68, 0x08);
  144. //
  145. // Program and Enable EC (index) Port Addresses and range
  146. //
  147. PchLpcGenIoRangeSet (0x1200, 0x10);
  148. }
  149. /**
  150. Configure GPIO and SIO before memory ready.
  151. @retval EFI_SUCCESS Operation success.
  152. **/
  153. EFI_STATUS
  154. EFIAPI
  155. AspireVn7Dash572GBoardInitBeforeMemoryInit (
  156. VOID
  157. )
  158. {
  159. EFI_STATUS Status;
  160. Status = GpioInitPreMem ();
  161. if (!EFI_ERROR (Status)) {
  162. DgpuPowerOn ();
  163. }
  164. AspireVn7Dash572GInitPreMem ();
  165. ///
  166. /// Do basic PCH init
  167. ///
  168. SiliconInit ();
  169. //
  170. // Fix-up LPC configuration
  171. // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2Eh/2Fh, 4Eh/4Fh, 60h/64h and 62h/66h.
  172. //
  173. PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange));
  174. PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding));
  175. //
  176. // Install PCH RESET PPI and EFI RESET2 PeiService
  177. //
  178. Status = PchInitializeReset ();
  179. ASSERT_EFI_ERROR (Status);
  180. return EFI_SUCCESS;
  181. }
  182. /**
  183. Configure GPIO and SIO before memory ready.
  184. @retval EFI_SUCCESS Operation success.
  185. **/
  186. EFI_STATUS
  187. EFIAPI
  188. AspireVn7Dash572GBoardInitAfterMemoryInit (
  189. VOID
  190. )
  191. {
  192. EFI_STATUS Status;
  193. // BUGBUG: Workaround for a misbehaving system firmware not setting goIdle
  194. // - Based on prior investigation for coreboot, I suspect FSP
  195. if ((MmioRead32 (0xFED40044) & PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE) == 0) {
  196. DEBUG ((DEBUG_WARN, "TPM no-IdleBypass bug: workaround enabled\n"));
  197. MmioWrite32 (0xFED40040, PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE);
  198. }
  199. // Program the same 64K range of EC memory as vendor FW
  200. Status = PchLpcMemRangeSet (0xFE800000);
  201. if (EFI_ERROR (Status)) {
  202. DEBUG ((DEBUG_WARN, "Failed to enable LGMR. Were ACPI tables built for LGMR memory map?\n"));
  203. }
  204. return EFI_SUCCESS;
  205. }
  206. EFI_STATUS
  207. EFIAPI
  208. AspireVn7Dash572GBoardDebugInit (
  209. VOID
  210. )
  211. {
  212. ///
  213. /// Do Early PCH init
  214. ///
  215. EarlySiliconInit ();
  216. LpcInit ();
  217. // NB: MinPlatform specification defines platform initialisation flow.
  218. // Therefore, we defer board detection until we can program LPC.
  219. // - Alternatively, move the preceding calls to BoardDetect()
  220. AspireVn7Dash572GBoardDetect ();
  221. return EFI_SUCCESS;
  222. }
  223. EFI_BOOT_MODE
  224. EFIAPI
  225. AspireVn7Dash572GBoardBootModeDetect (
  226. VOID
  227. )
  228. {
  229. UINT16 ABase;
  230. UINT32 SleepType;
  231. DEBUG ((DEBUG_INFO, "Performing boot mode detection\n"));
  232. // TODO: Perform advanced detection (recovery/capsule)
  233. // FIXME: This violates PI specification? But BOOT_WITH* would always take precedence
  234. // over BOOT_ON_S{4,5}...
  235. PchAcpiBaseGet (&ABase);
  236. SleepType = IoRead32 (ABase + R_PCH_ACPI_PM1_CNT) & B_PCH_ACPI_PM1_CNT_SLP_TYP;
  237. switch (SleepType) {
  238. case V_PCH_ACPI_PM1_CNT_S3:
  239. return BOOT_ON_S3_RESUME;
  240. case V_PCH_ACPI_PM1_CNT_S4:
  241. return BOOT_ON_S4_RESUME;
  242. // case V_PCH_ACPI_PM1_CNT_S5:
  243. // return BOOT_ON_S5_RESUME;
  244. default:
  245. return BOOT_WITH_FULL_CONFIGURATION;
  246. }
  247. }