OpenBoardPkg.fdf 27 KB

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  1. ## @file
  2. # FDF file of Platform.
  3. #
  4. #
  5. # Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
  6. #
  7. # SPDX-License-Identifier: BSD-2-Clause-Patent
  8. #
  9. #
  10. ##
  11. [Defines]
  12. !include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf
  13. ################################################################################
  14. #
  15. # FD Section
  16. # The [FD] Section is made up of the definition statements and a
  17. # description of what goes into the Flash Device Image. Each FD section
  18. # defines one flash "device" image. A flash device image may be one of
  19. # the following: Removable media bootable image (like a boot floppy
  20. # image,) an Option ROM image (that would be "flashed" into an add-in
  21. # card,) a System "Flash" image (that would be burned into a system's
  22. # flash) or an Update ("Capsule") image that will be used to update and
  23. # existing system flash.
  24. #
  25. ################################################################################
  26. [FD.WhiskeylakeURvp]
  27. #
  28. # FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks, cannot be
  29. # assigned with PCD values. Instead, it uses the definitions for its variety, which
  30. # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS.
  31. #
  32. BaseAddress = $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress #The base address of the FLASH Device.
  33. Size = $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdBiosSize #The size in bytes of the FLASH Device
  34. ErasePolarity = 1
  35. BlockSize = $(FLASH_BLOCK_SIZE)
  36. NumBlocks = $(FLASH_NUM_BLOCKS)
  37. DEFINE SIPKG_DXE_SMM_BIN = INF
  38. DEFINE SIPKG_PEI_BIN = INF
  39. # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macro expression is not supported.
  40. # So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase to get the real CodeCache base address.
  41. SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase = $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset)
  42. SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
  43. SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
  44. SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
  45. SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
  46. SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
  47. SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
  48. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset = 0x60
  49. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
  50. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
  51. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
  52. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
  53. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize = gSiPkgTokenSpaceGuid.PcdBiosSize
  54. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
  55. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
  56. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = $(gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
  57. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
  58. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = gSiPkgTokenSpaceGuid.PcdBiosSize
  59. ################################################################################
  60. #
  61. # Following are lists of FD Region layout which correspond to the locations of different
  62. # images within the flash device.
  63. #
  64. # Regions must be defined in ascending order and may not overlap.
  65. #
  66. # A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
  67. # the pipe "|" character, followed by the size of the region, also in hex with the leading
  68. # "0x" characters. Like:
  69. # Offset|Size
  70. # PcdOffsetCName|PcdSizeCName
  71. # RegionType <FV, DATA, or FILE>
  72. # Fv Size can be adjusted
  73. #
  74. ################################################################################
  75. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  76. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  77. #NV_VARIABLE_STORE
  78. DATA = {
  79. ## This is the EFI_FIRMWARE_VOLUME_HEADER
  80. # ZeroVector []
  81. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  82. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  83. # FileSystemGuid
  84. 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
  85. 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
  86. # FvLength: 0x40000
  87. 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
  88. #Signature "_FVH" #Attributes
  89. 0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00,
  90. #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
  91. #
  92. # Be careful on CheckSum field.
  93. #
  94. 0x48, 0x00, 0x32, 0x09, 0x00, 0x00, 0x00, 0x02,
  95. #Blockmap[0]: 4 Blocks 0x10000 Bytes / Block
  96. 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
  97. #Blockmap[1]: End
  98. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  99. ## This is the VARIABLE_STORE_HEADER
  100. !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE
  101. # Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
  102. 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
  103. 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
  104. !else
  105. # Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
  106. 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
  107. 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
  108. !endif
  109. #Size: 0x1E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x1DFB8
  110. # This can speed up the Variable Dispatch a bit.
  111. 0xB8, 0xDF, 0x01, 0x00,
  112. #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
  113. 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  114. }
  115. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  116. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  117. #NV_FTW_WORKING
  118. DATA = {
  119. # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
  120. # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
  121. 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
  122. 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
  123. # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
  124. 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
  125. # WriteQueueSize: UINT64
  126. 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  127. }
  128. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
  129. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
  130. #NV_FTW_SPARE
  131. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  132. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  133. FV = FvAdvanced
  134. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  135. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  136. FV = FvSecurity
  137. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  138. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  139. FV = FvOsBoot
  140. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
  141. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
  142. FV = FvUefiBoot
  143. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  144. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  145. FV = FvPostMemory
  146. gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
  147. gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
  148. #Microcode
  149. FV = FvMicrocode
  150. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  151. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  152. # FSP_S Section
  153. FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd
  154. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  155. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  156. # FSP_M Section
  157. FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd
  158. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  159. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  160. # FSP_T Section
  161. FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd
  162. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
  163. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
  164. FV = FvPreMemory
  165. ################################################################################
  166. #
  167. # FV Section
  168. #
  169. # [FV] section is used to define what components or modules are placed within a flash
  170. # device file. This section also defines order the components and modules are positioned
  171. # within the image. The [FV] section consists of define statements, set statements and
  172. # module statements.
  173. #
  174. ################################################################################
  175. [FV.FvMicrocode]
  176. BlockSize = $(FLASH_BLOCK_SIZE)
  177. FvAlignment = 16
  178. ERASE_POLARITY = 1
  179. MEMORY_MAPPED = TRUE
  180. STICKY_WRITE = TRUE
  181. LOCK_CAP = TRUE
  182. LOCK_STATUS = FALSE
  183. WRITE_DISABLED_CAP = TRUE
  184. WRITE_ENABLED_CAP = TRUE
  185. WRITE_STATUS = TRUE
  186. WRITE_LOCK_CAP = TRUE
  187. WRITE_LOCK_STATUS = TRUE
  188. READ_DISABLED_CAP = TRUE
  189. READ_ENABLED_CAP = TRUE
  190. READ_STATUS = FALSE
  191. READ_LOCK_CAP = TRUE
  192. READ_LOCK_STATUS = TRUE
  193. FILE RAW = 197DB236-F856-4924-90F8-CDF12FB875F3 {
  194. $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/X64/MicrocodeUpdates.bin
  195. }
  196. [FV.FvPreMemory]
  197. BlockSize = $(FLASH_BLOCK_SIZE)
  198. FvAlignment = 16
  199. ERASE_POLARITY = 1
  200. MEMORY_MAPPED = TRUE
  201. STICKY_WRITE = TRUE
  202. LOCK_CAP = TRUE
  203. LOCK_STATUS = TRUE
  204. WRITE_DISABLED_CAP = TRUE
  205. WRITE_ENABLED_CAP = TRUE
  206. WRITE_STATUS = TRUE
  207. WRITE_LOCK_CAP = TRUE
  208. WRITE_LOCK_STATUS = TRUE
  209. READ_DISABLED_CAP = TRUE
  210. READ_ENABLED_CAP = TRUE
  211. READ_STATUS = TRUE
  212. READ_LOCK_CAP = TRUE
  213. READ_LOCK_STATUS = TRUE
  214. FvNameGuid = FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D
  215. INF UefiCpuPkg/SecCore/SecCore.inf
  216. INF MdeModulePkg/Core/Pei/PeiMain.inf
  217. !include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf
  218. INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
  219. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
  220. INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
  221. INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
  222. INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf
  223. [FV.FvPostMemoryUncompact]
  224. BlockSize = $(FLASH_BLOCK_SIZE)
  225. FvAlignment = 16
  226. ERASE_POLARITY = 1
  227. MEMORY_MAPPED = TRUE
  228. STICKY_WRITE = TRUE
  229. LOCK_CAP = TRUE
  230. LOCK_STATUS = TRUE
  231. WRITE_DISABLED_CAP = TRUE
  232. WRITE_ENABLED_CAP = TRUE
  233. WRITE_STATUS = TRUE
  234. WRITE_LOCK_CAP = TRUE
  235. WRITE_LOCK_STATUS = TRUE
  236. READ_DISABLED_CAP = TRUE
  237. READ_ENABLED_CAP = TRUE
  238. READ_STATUS = TRUE
  239. READ_LOCK_CAP = TRUE
  240. READ_LOCK_STATUS = TRUE
  241. FvNameGuid = 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7
  242. !include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf
  243. # Init Board Config PCD
  244. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
  245. INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
  246. INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf
  247. FILE RAW = C9505BC0-AA3D-4056-9995-870C8DE8594E {
  248. $(PLATFORM_SI_BIN_PACKAGE)/ChipsetInit/CnlPchLpChipsetInitTable_Dx.bin
  249. }
  250. !if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable == TRUE
  251. FILE FREEFORM =PCD(gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid) {
  252. SECTION RAW = $(PLATFORM_FSP_BIN_PACKAGE)/SampleCode/Vbt/Vbt.bin
  253. SECTION UI = "Vbt"
  254. }
  255. FILE FREEFORM = 7BB28B99-61BB-11D5-9A5D-0090273FC14D {
  256. SECTION RAW = MdeModulePkg/Logo/Logo.bmp
  257. }
  258. !endif # PcdPeiDisplayEnable
  259. [FV.FvPostMemory]
  260. BlockSize = $(FLASH_BLOCK_SIZE)
  261. FvAlignment = 16
  262. ERASE_POLARITY = 1
  263. MEMORY_MAPPED = TRUE
  264. STICKY_WRITE = TRUE
  265. LOCK_CAP = TRUE
  266. LOCK_STATUS = TRUE
  267. WRITE_DISABLED_CAP = TRUE
  268. WRITE_ENABLED_CAP = TRUE
  269. WRITE_STATUS = TRUE
  270. WRITE_LOCK_CAP = TRUE
  271. WRITE_LOCK_STATUS = TRUE
  272. READ_DISABLED_CAP = TRUE
  273. READ_ENABLED_CAP = TRUE
  274. READ_STATUS = TRUE
  275. READ_LOCK_CAP = TRUE
  276. READ_LOCK_STATUS = TRUE
  277. FvNameGuid = 9DFE49DB-8EF0-4D9C-B273-0036144DE917
  278. FILE FV_IMAGE = 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 {
  279. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  280. SECTION FV_IMAGE = FvPostMemoryUncompact
  281. }
  282. }
  283. [FV.FvUefiBootUncompact]
  284. BlockSize = $(FLASH_BLOCK_SIZE)
  285. FvAlignment = 16
  286. ERASE_POLARITY = 1
  287. MEMORY_MAPPED = TRUE
  288. STICKY_WRITE = TRUE
  289. LOCK_CAP = TRUE
  290. LOCK_STATUS = TRUE
  291. WRITE_DISABLED_CAP = TRUE
  292. WRITE_ENABLED_CAP = TRUE
  293. WRITE_STATUS = TRUE
  294. WRITE_LOCK_CAP = TRUE
  295. WRITE_LOCK_STATUS = TRUE
  296. READ_DISABLED_CAP = TRUE
  297. READ_ENABLED_CAP = TRUE
  298. READ_STATUS = TRUE
  299. READ_LOCK_CAP = TRUE
  300. READ_LOCK_STATUS = TRUE
  301. FvNameGuid = A881D567-6CB0-4eee-8435-2E72D33E45B5
  302. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf
  303. INF $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxeCnl.inf
  304. INF UefiCpuPkg/CpuDxe/CpuDxe.inf
  305. INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
  306. INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
  307. INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
  308. INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
  309. INF MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf
  310. INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
  311. INF ShellPkg/Application/Shell/Shell.inf
  312. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
  313. INF $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf
  314. INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf
  315. INF IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf
  316. INF $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf
  317. [FV.FvUefiBoot]
  318. BlockSize = $(FLASH_BLOCK_SIZE)
  319. FvAlignment = 16
  320. ERASE_POLARITY = 1
  321. MEMORY_MAPPED = TRUE
  322. STICKY_WRITE = TRUE
  323. LOCK_CAP = TRUE
  324. LOCK_STATUS = TRUE
  325. WRITE_DISABLED_CAP = TRUE
  326. WRITE_ENABLED_CAP = TRUE
  327. WRITE_STATUS = TRUE
  328. WRITE_LOCK_CAP = TRUE
  329. WRITE_LOCK_STATUS = TRUE
  330. READ_DISABLED_CAP = TRUE
  331. READ_ENABLED_CAP = TRUE
  332. READ_STATUS = TRUE
  333. READ_LOCK_CAP = TRUE
  334. READ_LOCK_STATUS = TRUE
  335. FvNameGuid = 0496D33D-EA79-495C-B65D-ABF607184E3B
  336. FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
  337. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  338. SECTION FV_IMAGE = FvUefiBootUncompact
  339. }
  340. }
  341. [FV.FvOsBootUncompact]
  342. BlockSize = $(FLASH_BLOCK_SIZE)
  343. FvAlignment = 16
  344. ERASE_POLARITY = 1
  345. MEMORY_MAPPED = TRUE
  346. STICKY_WRITE = TRUE
  347. LOCK_CAP = TRUE
  348. LOCK_STATUS = TRUE
  349. WRITE_DISABLED_CAP = TRUE
  350. WRITE_ENABLED_CAP = TRUE
  351. WRITE_STATUS = TRUE
  352. WRITE_LOCK_CAP = TRUE
  353. WRITE_LOCK_STATUS = TRUE
  354. READ_DISABLED_CAP = TRUE
  355. READ_ENABLED_CAP = TRUE
  356. READ_STATUS = TRUE
  357. READ_LOCK_CAP = TRUE
  358. READ_LOCK_STATUS = TRUE
  359. FvNameGuid = A0F04529-B715-44C6-BCA4-2DEBDD01EEEC
  360. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf
  361. !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
  362. INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
  363. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
  364. INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
  365. INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
  366. INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf
  367. INF RuleOverride = DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
  368. INF $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
  369. !endif
  370. [FV.FvLateSilicon]
  371. BlockSize = $(FLASH_BLOCK_SIZE)
  372. FvAlignment = 16
  373. ERASE_POLARITY = 1
  374. MEMORY_MAPPED = TRUE
  375. STICKY_WRITE = TRUE
  376. LOCK_CAP = TRUE
  377. LOCK_STATUS = TRUE
  378. WRITE_DISABLED_CAP = TRUE
  379. WRITE_ENABLED_CAP = TRUE
  380. WRITE_STATUS = TRUE
  381. WRITE_LOCK_CAP = TRUE
  382. WRITE_LOCK_STATUS = TRUE
  383. READ_DISABLED_CAP = TRUE
  384. READ_ENABLED_CAP = TRUE
  385. READ_STATUS = TRUE
  386. READ_LOCK_CAP = TRUE
  387. READ_LOCK_STATUS = TRUE
  388. FvNameGuid = 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E
  389. !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
  390. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
  391. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmAccess.inf
  392. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf
  393. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf
  394. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf
  395. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf
  396. INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaAcpiTables.inf
  397. INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf
  398. !endif
  399. [FV.FvOsBoot]
  400. BlockSize = $(FLASH_BLOCK_SIZE)
  401. FvAlignment = 16
  402. ERASE_POLARITY = 1
  403. MEMORY_MAPPED = TRUE
  404. STICKY_WRITE = TRUE
  405. LOCK_CAP = TRUE
  406. LOCK_STATUS = TRUE
  407. WRITE_DISABLED_CAP = TRUE
  408. WRITE_ENABLED_CAP = TRUE
  409. WRITE_STATUS = TRUE
  410. WRITE_LOCK_CAP = TRUE
  411. WRITE_LOCK_STATUS = TRUE
  412. READ_DISABLED_CAP = TRUE
  413. READ_ENABLED_CAP = TRUE
  414. READ_STATUS = TRUE
  415. READ_LOCK_CAP = TRUE
  416. READ_LOCK_STATUS = TRUE
  417. FvNameGuid = 13BF8810-75FD-4B1A-91E6-E16C4201F80A
  418. FILE FV_IMAGE = B9020753-84A8-4BB6-947C-CE7D41F5CE39 {
  419. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  420. SECTION FV_IMAGE = FvOsBootUncompact
  421. }
  422. }
  423. FILE FV_IMAGE = D4632741-510C-44E3-BE21-C3D6D7881485 {
  424. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  425. SECTION FV_IMAGE = FvLateSilicon
  426. }
  427. }
  428. [FV.FvSecurityPreMemory]
  429. BlockSize = $(FLASH_BLOCK_SIZE)
  430. FvAlignment = 16 #FV alignment and FV attributes setting.
  431. ERASE_POLARITY = 1
  432. MEMORY_MAPPED = TRUE
  433. STICKY_WRITE = TRUE
  434. LOCK_CAP = TRUE
  435. LOCK_STATUS = TRUE
  436. WRITE_DISABLED_CAP = TRUE
  437. WRITE_ENABLED_CAP = TRUE
  438. WRITE_STATUS = TRUE
  439. WRITE_LOCK_CAP = TRUE
  440. WRITE_LOCK_STATUS = TRUE
  441. READ_DISABLED_CAP = TRUE
  442. READ_ENABLED_CAP = TRUE
  443. READ_STATUS = TRUE
  444. READ_LOCK_CAP = TRUE
  445. READ_LOCK_STATUS = TRUE
  446. FvNameGuid = 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B
  447. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
  448. INF IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
  449. INF IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
  450. [FV.FvSecurityPostMemory]
  451. BlockSize = $(FLASH_BLOCK_SIZE)
  452. FvAlignment = 16 #FV alignment and FV attributes setting.
  453. ERASE_POLARITY = 1
  454. MEMORY_MAPPED = TRUE
  455. STICKY_WRITE = TRUE
  456. LOCK_CAP = TRUE
  457. LOCK_STATUS = TRUE
  458. WRITE_DISABLED_CAP = TRUE
  459. WRITE_ENABLED_CAP = TRUE
  460. WRITE_STATUS = TRUE
  461. WRITE_LOCK_CAP = TRUE
  462. WRITE_LOCK_STATUS = TRUE
  463. READ_DISABLED_CAP = TRUE
  464. READ_ENABLED_CAP = TRUE
  465. READ_STATUS = TRUE
  466. READ_LOCK_CAP = TRUE
  467. READ_LOCK_STATUS = TRUE
  468. FvNameGuid = 4199E560-54AE-45E5-91A4-F7BC3804E14A
  469. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf
  470. !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
  471. INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
  472. !endif
  473. [FV.FvSecurityLate]
  474. BlockSize = $(FLASH_BLOCK_SIZE)
  475. FvAlignment = 16
  476. ERASE_POLARITY = 1
  477. MEMORY_MAPPED = TRUE
  478. STICKY_WRITE = TRUE
  479. LOCK_CAP = TRUE
  480. LOCK_STATUS = TRUE
  481. WRITE_DISABLED_CAP = TRUE
  482. WRITE_ENABLED_CAP = TRUE
  483. WRITE_STATUS = TRUE
  484. WRITE_LOCK_CAP = TRUE
  485. WRITE_LOCK_STATUS = TRUE
  486. READ_DISABLED_CAP = TRUE
  487. READ_ENABLED_CAP = TRUE
  488. READ_STATUS = TRUE
  489. READ_LOCK_CAP = TRUE
  490. READ_LOCK_STATUS = TRUE
  491. FvNameGuid = F753FE9A-EEFD-485B-840B-E032D538102C
  492. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf
  493. INF IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
  494. !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
  495. INF $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
  496. !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
  497. INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
  498. !endif
  499. !endif
  500. [FV.FvSecurity]
  501. BlockSize = $(FLASH_BLOCK_SIZE)
  502. FvAlignment = 16
  503. ERASE_POLARITY = 1
  504. MEMORY_MAPPED = TRUE
  505. STICKY_WRITE = TRUE
  506. LOCK_CAP = TRUE
  507. LOCK_STATUS = TRUE
  508. WRITE_DISABLED_CAP = TRUE
  509. WRITE_ENABLED_CAP = TRUE
  510. WRITE_STATUS = TRUE
  511. WRITE_LOCK_CAP = TRUE
  512. WRITE_LOCK_STATUS = TRUE
  513. READ_DISABLED_CAP = TRUE
  514. READ_ENABLED_CAP = TRUE
  515. READ_STATUS = TRUE
  516. READ_LOCK_CAP = TRUE
  517. READ_LOCK_STATUS = TRUE
  518. FvNameGuid = 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF
  519. FILE FV_IMAGE = 757CC075-1428-423D-A73C-22639706C119 {
  520. SECTION FV_IMAGE = FvSecurityPreMemory
  521. }
  522. FILE FV_IMAGE = 80BB8482-44D5-4BEC-82B5-8D87A933830B {
  523. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  524. SECTION FV_IMAGE = FvSecurityPostMemory
  525. }
  526. }
  527. FILE FV_IMAGE = C83522D9-80A1-4D95-8C25-3F1370497406 {
  528. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  529. SECTION FV_IMAGE = FvSecurityLate
  530. }
  531. }
  532. [FV.FvAdvancedPreMem]
  533. FvAlignment = 16
  534. ERASE_POLARITY = 1
  535. MEMORY_MAPPED = TRUE
  536. STICKY_WRITE = TRUE
  537. LOCK_CAP = TRUE
  538. LOCK_STATUS = TRUE
  539. WRITE_DISABLED_CAP = TRUE
  540. WRITE_ENABLED_CAP = TRUE
  541. WRITE_STATUS = TRUE
  542. WRITE_LOCK_CAP = TRUE
  543. WRITE_LOCK_STATUS = TRUE
  544. READ_DISABLED_CAP = TRUE
  545. READ_ENABLED_CAP = TRUE
  546. READ_STATUS = TRUE
  547. READ_LOCK_CAP = TRUE
  548. READ_LOCK_STATUS = TRUE
  549. FvNameGuid = 6053D78A-457E-4490-A237-31D0FBE2F305
  550. !if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
  551. INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
  552. !endif
  553. [FV.FvAdvancedPostMem]
  554. FvAlignment = 16
  555. ERASE_POLARITY = 1
  556. MEMORY_MAPPED = TRUE
  557. STICKY_WRITE = TRUE
  558. LOCK_CAP = TRUE
  559. LOCK_STATUS = TRUE
  560. WRITE_DISABLED_CAP = TRUE
  561. WRITE_ENABLED_CAP = TRUE
  562. WRITE_STATUS = TRUE
  563. WRITE_LOCK_CAP = TRUE
  564. WRITE_LOCK_STATUS = TRUE
  565. READ_DISABLED_CAP = TRUE
  566. READ_ENABLED_CAP = TRUE
  567. READ_STATUS = TRUE
  568. READ_LOCK_CAP = TRUE
  569. READ_LOCK_STATUS = TRUE
  570. FvNameGuid = BE3DF86F-E464-44A3-83F7-0D27E6B88C27
  571. [FV.FvAdvancedLate]
  572. FvAlignment = 16
  573. ERASE_POLARITY = 1
  574. MEMORY_MAPPED = TRUE
  575. STICKY_WRITE = TRUE
  576. LOCK_CAP = TRUE
  577. LOCK_STATUS = TRUE
  578. WRITE_DISABLED_CAP = TRUE
  579. WRITE_ENABLED_CAP = TRUE
  580. WRITE_STATUS = TRUE
  581. WRITE_LOCK_CAP = TRUE
  582. WRITE_LOCK_STATUS = TRUE
  583. READ_DISABLED_CAP = TRUE
  584. READ_ENABLED_CAP = TRUE
  585. READ_STATUS = TRUE
  586. READ_LOCK_CAP = TRUE
  587. READ_LOCK_STATUS = TRUE
  588. FvNameGuid = 11F6E304-43F9-4B2F-90AB-B8FFEAD6205D
  589. !if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
  590. INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
  591. INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
  592. INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
  593. !endif
  594. [FV.FvAdvanced]
  595. BlockSize = $(FLASH_BLOCK_SIZE)
  596. FvAlignment = 16
  597. ERASE_POLARITY = 1
  598. MEMORY_MAPPED = TRUE
  599. STICKY_WRITE = TRUE
  600. LOCK_CAP = TRUE
  601. LOCK_STATUS = TRUE
  602. WRITE_DISABLED_CAP = TRUE
  603. WRITE_ENABLED_CAP = TRUE
  604. WRITE_STATUS = TRUE
  605. WRITE_LOCK_CAP = TRUE
  606. WRITE_LOCK_STATUS = TRUE
  607. READ_DISABLED_CAP = TRUE
  608. READ_ENABLED_CAP = TRUE
  609. READ_STATUS = TRUE
  610. READ_LOCK_CAP = TRUE
  611. READ_LOCK_STATUS = TRUE
  612. FvNameGuid = B23E7388-9953-45C7-9201-0473DDE5487A
  613. FILE FV_IMAGE = 35E7406A-5842-4F2B-BC62-19022C12AF74 {
  614. SECTION FV_IMAGE = FvAdvancedPreMem
  615. }
  616. FILE FV_IMAGE = F5DCB34F-27EA-48AC-9406-C894F6D587CA {
  617. SECTION FV_IMAGE = FvAdvancedPostMem
  618. }
  619. FILE FV_IMAGE = 5248467B-B87B-4E74-AC02-398AF4BCB712 {
  620. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  621. SECTION FV_IMAGE = FvAdvancedLate
  622. }
  623. }
  624. ################################################################################
  625. #
  626. # Rules are use with the [FV] section's module INF type to define
  627. # how an FFS file is created for a given INF file. The following Rule are the default
  628. # rules for the different module type. User can add the customized rules to define the
  629. # content of the FFS file.
  630. #
  631. ################################################################################
  632. !include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf