PciHostBridgeLib.c 15 KB

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  1. /** @file
  2. Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
  3. Copyright (c) 2018, Linaro Limited. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <PiDxe.h>
  7. #include <Library/DebugLib.h>
  8. #include <Library/DevicePathLib.h>
  9. #include <Library/MemoryAllocationLib.h>
  10. #include <Library/PciHostBridgeLib.h>
  11. #include <Protocol/PciHostBridgeResourceAllocation.h>
  12. #include <Protocol/PciRootBridgeIo.h>
  13. #define ENUM_HB_NUM 8
  14. #define EFI_PCI_SUPPORT (EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \
  15. EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | \
  16. EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | \
  17. EFI_PCI_ATTRIBUTE_ISA_IO_16 | \
  18. EFI_PCI_ATTRIBUTE_VGA_MEMORY | \
  19. EFI_PCI_ATTRIBUTE_VGA_IO_16 | \
  20. EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16)
  21. #define EFI_PCI_ATTRIBUTE EFI_PCI_SUPPORT
  22. #pragma pack(1)
  23. typedef struct {
  24. ACPI_HID_DEVICE_PATH AcpiDevicePath;
  25. EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
  26. } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
  27. #pragma pack ()
  28. STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath [ENUM_HB_NUM] = {
  29. //Host Bridge 0
  30. {
  31. {
  32. {
  33. ACPI_DEVICE_PATH,
  34. ACPI_DP,
  35. {
  36. (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
  37. (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
  38. }
  39. },
  40. EISA_PNP_ID(0x0A03), // PCI
  41. 0
  42. },
  43. {
  44. END_DEVICE_PATH_TYPE,
  45. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  46. {
  47. END_DEVICE_PATH_LENGTH,
  48. 0
  49. }
  50. }
  51. },
  52. //Host Bridge 2
  53. {
  54. {
  55. {
  56. ACPI_DEVICE_PATH,
  57. ACPI_DP,
  58. {
  59. (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
  60. (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
  61. }
  62. },
  63. EISA_PNP_ID(0x0A03), // PCI
  64. 2
  65. },
  66. {
  67. END_DEVICE_PATH_TYPE,
  68. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  69. {
  70. END_DEVICE_PATH_LENGTH,
  71. 0
  72. }
  73. }
  74. },
  75. //Host Bridge 4
  76. {
  77. {
  78. {
  79. ACPI_DEVICE_PATH,
  80. ACPI_DP,
  81. {
  82. (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
  83. (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
  84. }
  85. },
  86. EISA_PNP_ID(0x0A03), // PCI
  87. 4
  88. },
  89. {
  90. END_DEVICE_PATH_TYPE,
  91. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  92. {
  93. END_DEVICE_PATH_LENGTH,
  94. 0
  95. }
  96. }
  97. },
  98. //Host Bridge 5
  99. {
  100. {
  101. {
  102. ACPI_DEVICE_PATH,
  103. ACPI_DP,
  104. {
  105. (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
  106. (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
  107. }
  108. },
  109. EISA_PNP_ID(0x0A03), // PCI
  110. 5
  111. },
  112. {
  113. END_DEVICE_PATH_TYPE,
  114. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  115. {
  116. END_DEVICE_PATH_LENGTH,
  117. 0
  118. }
  119. }
  120. },
  121. //Host Bridge 6
  122. {
  123. {
  124. {
  125. ACPI_DEVICE_PATH,
  126. ACPI_DP,
  127. {
  128. (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
  129. (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
  130. }
  131. },
  132. EISA_PNP_ID(0x0A03), // PCI
  133. 6
  134. },
  135. {
  136. END_DEVICE_PATH_TYPE,
  137. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  138. {
  139. END_DEVICE_PATH_LENGTH,
  140. 0
  141. }
  142. }
  143. },
  144. //Host Bridge 8
  145. {
  146. {
  147. {
  148. ACPI_DEVICE_PATH,
  149. ACPI_DP,
  150. {
  151. (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
  152. (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
  153. }
  154. },
  155. EISA_PNP_ID(0x0A03), // PCI
  156. 8
  157. },
  158. {
  159. END_DEVICE_PATH_TYPE,
  160. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  161. {
  162. END_DEVICE_PATH_LENGTH,
  163. 0
  164. }
  165. }
  166. },
  167. //Host Bridge 10
  168. {
  169. {
  170. {
  171. ACPI_DEVICE_PATH,
  172. ACPI_DP,
  173. {
  174. (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
  175. (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
  176. }
  177. },
  178. EISA_PNP_ID(0x0A03), // PCI
  179. 10
  180. },
  181. {
  182. END_DEVICE_PATH_TYPE,
  183. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  184. {
  185. END_DEVICE_PATH_LENGTH,
  186. 0
  187. }
  188. }
  189. },
  190. //Host Bridge 11
  191. {
  192. {
  193. {
  194. ACPI_DEVICE_PATH,
  195. ACPI_DP,
  196. {
  197. (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
  198. (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
  199. }
  200. },
  201. EISA_PNP_ID(0x0A03), // PCI
  202. 11
  203. },
  204. {
  205. END_DEVICE_PATH_TYPE,
  206. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  207. {
  208. END_DEVICE_PATH_LENGTH,
  209. 0
  210. }
  211. }
  212. }
  213. };
  214. STATIC PCI_ROOT_BRIDGE gRootBridge [ENUM_HB_NUM] = {
  215. //Host Bridge 0
  216. {
  217. 0, // Segment
  218. EFI_PCI_SUPPORT, // Supports
  219. EFI_PCI_ATTRIBUTE, // Attributes
  220. TRUE, // DmaAbove4G
  221. FALSE, // NoExtendedConfigSpace
  222. FALSE, // ResourceAssigned
  223. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  224. { // Bus
  225. 00,
  226. 0x3F
  227. },
  228. { // Io (32K)
  229. 0,
  230. 0x7FFF
  231. },
  232. { // Mem (256M - 64K - 1)
  233. 0xE0000000,
  234. 0xEFFEFFFF
  235. },
  236. { // MemAbove4G (8T + 256G)
  237. 0x80000000000,
  238. 0x83FFFFFFFFF
  239. },
  240. { // PMem
  241. 0xE0000000,
  242. 0xEFFEFFFF
  243. },
  244. { // PMemAbove4G
  245. 0x80000000000,
  246. 0x83FFFFFFFFF
  247. },
  248. (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
  249. },
  250. //Host Bridge 2
  251. {
  252. 0, // Segment
  253. EFI_PCI_SUPPORT, // Supports
  254. EFI_PCI_ATTRIBUTE, // Attributes
  255. TRUE, // DmaAbove4G
  256. FALSE, // NoExtendedConfigSpace
  257. FALSE, // ResourceAssigned
  258. EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes
  259. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  260. { // Bus
  261. 0x7A,
  262. 0x7A
  263. },
  264. { // Io
  265. MAX_UINT32,
  266. 0
  267. },
  268. { // Mem
  269. MAX_UINT32,
  270. 0
  271. },
  272. { // MemAbove4G
  273. 0x20c000000,
  274. 0x20c1fffff
  275. },
  276. { // PMem
  277. MAX_UINT32,
  278. 0
  279. },
  280. { // PMemAbove4G
  281. MAX_UINT64,
  282. 0
  283. },
  284. (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1]
  285. },
  286. //Host Bridge 4
  287. {
  288. 0, // Segment
  289. EFI_PCI_SUPPORT, // Supports
  290. EFI_PCI_ATTRIBUTE, // Attributes
  291. TRUE, // DmaAbove4G
  292. FALSE, // NoExtendedConfigSpace
  293. FALSE, // ResourceAssigned
  294. EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes
  295. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  296. { // Bus
  297. 0x7C,
  298. 0x7D
  299. },
  300. { // Io
  301. MAX_UINT32,
  302. 0
  303. },
  304. { // Mem
  305. MAX_UINT32,
  306. 0
  307. },
  308. { // MemAbove4G
  309. 0x120000000,
  310. 0x13fffffff
  311. },
  312. { // PMem
  313. MAX_UINT32,
  314. 0
  315. },
  316. { // PMemAbove4G
  317. MAX_UINT64,
  318. 0
  319. },
  320. (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[2]
  321. },
  322. //Host Bridge 5
  323. {
  324. 0, // Segment
  325. EFI_PCI_SUPPORT, // Supports
  326. EFI_PCI_ATTRIBUTE, // Attributes
  327. TRUE, // DmaAbove4G
  328. FALSE, // NoExtendedConfigSpace
  329. FALSE, // ResourceAssigned
  330. EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes
  331. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  332. { // Bus
  333. 0x74,
  334. 0x76
  335. },
  336. { // Io
  337. MAX_UINT32,
  338. 0
  339. },
  340. { // Mem
  341. 0xA2000000,
  342. 0xA2ffffff
  343. },
  344. { // MemAbove4G
  345. 0x144000000,
  346. 0x147ffffff
  347. },
  348. { // PMem
  349. MAX_UINT32,
  350. 0
  351. },
  352. { // PMemAbove4G
  353. MAX_UINT64,
  354. 0
  355. },
  356. (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[3]
  357. },
  358. //Host Bridge 6
  359. {
  360. 0, // Segment
  361. EFI_PCI_SUPPORT, // Supports
  362. EFI_PCI_ATTRIBUTE, // Attributes
  363. TRUE, // DmaAbove4G
  364. FALSE, // NoExtendedConfigSpace
  365. FALSE, // ResourceAssigned
  366. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  367. { // Bus
  368. 0x80,
  369. 0x9F
  370. },
  371. { // Io (32K)
  372. 0x0,
  373. 0x7FFF
  374. },
  375. { // Mem (256M - 64K -1)
  376. 0xF0000000,
  377. 0xFFFEFFFF
  378. },
  379. { // MemAbove4G (8T + 256G)
  380. 0x480000000000,
  381. 0x483FFFFFFFFF
  382. },
  383. { // PMem
  384. 0xF0000000,
  385. 0xFFFEFFFF
  386. },
  387. { // PMemAbove4G
  388. 0x480000000000,
  389. 0x483FFFFFFFFF
  390. },
  391. (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[4]
  392. },
  393. //Host Bridge 8
  394. {
  395. 0, // Segment
  396. EFI_PCI_SUPPORT, // Supports
  397. EFI_PCI_ATTRIBUTE, // Attributes
  398. TRUE, // DmaAbove4G
  399. FALSE, // NoExtendedConfigSpace
  400. FALSE, // ResourceAssigned
  401. EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes
  402. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  403. { // Bus
  404. 0xBA,
  405. 0xBA
  406. },
  407. { // Io
  408. MAX_UINT32,
  409. 0
  410. },
  411. { // Mem
  412. MAX_UINT32,
  413. 0
  414. },
  415. { // MemAbove4G
  416. 0x40020c000000,
  417. 0x40020c1fffff
  418. },
  419. { // PMem
  420. MAX_UINT32,
  421. 0
  422. },
  423. { // PMemAbove4G
  424. MAX_UINT64,
  425. 0
  426. },
  427. (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[5]
  428. },
  429. //Host Bridge 10
  430. {
  431. 0, // Segment
  432. EFI_PCI_SUPPORT, // Supports
  433. EFI_PCI_ATTRIBUTE, // Attributes
  434. TRUE, // DmaAbove4G
  435. FALSE, // NoExtendedConfigSpace
  436. FALSE, // ResourceAssigned
  437. EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes
  438. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  439. { // Bus
  440. 0xBC,
  441. 0xBD
  442. },
  443. { // Io
  444. MAX_UINT32,
  445. 0
  446. },
  447. { // Mem
  448. MAX_UINT32,
  449. 0
  450. },
  451. { // MemAbove4G
  452. 0x400120000000,
  453. 0x40013fffffff
  454. },
  455. { // PMem
  456. MAX_UINT32,
  457. 0
  458. },
  459. { // PMemAbove4G
  460. MAX_UINT64,
  461. 0
  462. },
  463. (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[6]
  464. },
  465. //Host Bridge 11
  466. {
  467. 0, // Segment
  468. EFI_PCI_SUPPORT, // Supports
  469. EFI_PCI_ATTRIBUTE, // Attributes
  470. TRUE, // DmaAbove4G
  471. FALSE, // NoExtendedConfigSpace
  472. FALSE, // ResourceAssigned
  473. EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes
  474. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  475. { // Bus
  476. 0xB4,
  477. 0xB6
  478. },
  479. { // Io
  480. MAX_UINT32,
  481. 0
  482. },
  483. { // Mem
  484. 0xA3000000,
  485. 0xA3ffffff
  486. },
  487. { // MemAbove4G
  488. 0x400144000000,
  489. 0x400147ffffff
  490. },
  491. { // PMem
  492. MAX_UINT32,
  493. 0
  494. },
  495. { // PMemAbove4G
  496. MAX_UINT64,
  497. 0
  498. },
  499. (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[7]
  500. }
  501. };
  502. /**
  503. Return all the root bridge instances in an array.
  504. @param Count Return the count of root bridge instances.
  505. @return All the root bridge instances in an array.
  506. The array should be passed into PciHostBridgeFreeRootBridges()
  507. when it's not used.
  508. **/
  509. PCI_ROOT_BRIDGE *
  510. EFIAPI
  511. PciHostBridgeGetRootBridges (
  512. UINTN *Count
  513. )
  514. {
  515. *Count = ENUM_HB_NUM;
  516. return gRootBridge;
  517. }
  518. /**
  519. Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
  520. @param Bridges The root bridge instances array.
  521. @param Count The count of the array.
  522. **/
  523. VOID
  524. EFIAPI
  525. PciHostBridgeFreeRootBridges (
  526. PCI_ROOT_BRIDGE *Bridges,
  527. UINTN Count
  528. )
  529. {
  530. if (Bridges == NULL && Count == 0) {
  531. return;
  532. }
  533. do {
  534. --Count;
  535. FreePool (Bridges[Count].DevicePath);
  536. } while (Count > 0);
  537. FreePool (Bridges);
  538. }
  539. STATIC CONST CHAR16 mPciHostBridgeLibAcpiAddressSpaceTypeStr[][4] = {
  540. L"Mem", L"I/O", L"Bus"
  541. };
  542. /**
  543. Inform the platform that the resource conflict happens.
  544. @param HostBridgeHandle Handle of the Host Bridge.
  545. @param Configuration Pointer to PCI I/O and PCI memory resource
  546. descriptors. The Configuration contains the resources
  547. for all the root bridges. The resource for each root
  548. bridge is terminated with END descriptor and an
  549. additional END is appended indicating the end of the
  550. entire resources. The resource descriptor field
  551. values follow the description in
  552. EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
  553. .SubmitResources().
  554. **/
  555. VOID
  556. EFIAPI
  557. PciHostBridgeResourceConflict (
  558. EFI_HANDLE HostBridgeHandle,
  559. VOID *Configuration
  560. )
  561. {
  562. EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
  563. UINTN RootBridgeIndex;
  564. DEBUG ((DEBUG_ERROR, "\n PciHostBridge: Resource conflict happens!\n"));
  565. RootBridgeIndex = 0;
  566. Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration;
  567. while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
  568. DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
  569. for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
  570. ASSERT (Descriptor->ResType <
  571. ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr)
  572. );
  573. DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
  574. mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
  575. Descriptor->AddrLen, Descriptor->AddrRangeMax
  576. ));
  577. if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
  578. DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
  579. Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
  580. ((Descriptor->SpecificFlag &
  581. EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
  582. ) != 0) ? L" (Prefetchable)" : L""
  583. ));
  584. }
  585. }
  586. //
  587. // Skip the END descriptor for root bridge
  588. //
  589. ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
  590. Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
  591. (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
  592. );
  593. }
  594. }