OemMiscLibD06.c 4.7 KB

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  1. /** @file
  2. *
  3. * Copyright (c) 2018, Hisilicon Limited. All rights reserved.
  4. * Copyright (c) 2018, Linaro Limited. All rights reserved.
  5. *
  6. * SPDX-License-Identifier: BSD-2-Clause-Patent
  7. *
  8. **/
  9. #include <Uefi.h>
  10. #include <PlatformArch.h>
  11. #include <Library/BaseMemoryLib.h>
  12. #include <Library/CpldD06.h>
  13. #include <Library/DebugLib.h>
  14. #include <Library/IoLib.h>
  15. #include <Library/LpcLib.h>
  16. #include <Library/OemAddressMapLib.h>
  17. #include <Library/OemMiscLib.h>
  18. #include <Library/PcdLib.h>
  19. #include <Library/PlatformSysCtrlLib.h>
  20. #include <Library/SerialPortLib.h>
  21. #include <Library/TimerLib.h>
  22. REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
  23. {67,0,0,0},
  24. {225,0,0,3},
  25. {0xFFFF,0xFFFF,0xFFFF,0xFFFF},
  26. {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
  27. };
  28. //Cpu0 Riser type is (X16 + X8) & Cpu1 Riser type is (X16 + X8)
  29. REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type1 [PCIEDEVICE_REPORT_MAX] = {
  30. {0x01,0,0,0},
  31. {0x03,0,0,1},
  32. {0xFF,0xFF,0xFF,2},
  33. {0x81,0,0,3},
  34. {0x84,0,0,4},
  35. {0xFF,0xFF,0xFF,5}
  36. };
  37. //Cpu0 Riser type is (X16 + X8) & Cpu1 Riser type is (3 * X8)
  38. REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type2 [PCIEDEVICE_REPORT_MAX] = {
  39. {0x01,0,0,0},
  40. {0x03,0,0,1},
  41. {0xFF,0xFF,0xFF,2},
  42. {0xFF,0xFF,0xFF,3},
  43. {0x81,0,0,4},
  44. {0x85,0,0,5}
  45. };
  46. //Cpu0 Riser type is (3 * X8) & Cpu1 Riser type is (X16 + X8)
  47. REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type3 [PCIEDEVICE_REPORT_MAX] = {
  48. {0xFF,0xFF,0xFF,0},
  49. {0x01,0,0,1},
  50. {0x04,0,0,2},
  51. {0x81,0,0,3},
  52. {0x84,0,0,4},
  53. {0xFF,0xFF,0xFF,5}
  54. };
  55. //Cpu0 Riser type is (3 * X8) & Cpu1 Riser type is (3 * X8)
  56. REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type4 [PCIEDEVICE_REPORT_MAX] = {
  57. {0xFF,0xFF,0xFF,0},
  58. {0x01,0,0,1},
  59. {0x04,0,0,2},
  60. {0xFF,0xFF,0xFF,3},
  61. {0x81,0,0,4},
  62. {0x85,0,0,5}
  63. };
  64. VOID
  65. GetPciDidVid (
  66. REPORT_PCIEDIDVID2BMC *Report
  67. )
  68. {
  69. UINT32 PresentStatus;
  70. UINT32 CardType;
  71. UINT8 Cpu0CardType = 0;
  72. UINT8 Cpu1CardType = 0;
  73. PresentStatus = MmioRead32 (CPLD_BASE_ADDRESS + CPLD_RISER_PRSNT_FLAG);
  74. CardType = MmioRead32 (CPLD_BASE_ADDRESS + CPLD_RISER2_BOARD_ID);
  75. // Offset 0x40: Bit7 = 1 CPU0 Riser present
  76. if ((PresentStatus & CPU0_RISER_PRESENT) != 0) {
  77. Cpu0CardType = (UINT8) (PresentStatus >> 8);
  78. }
  79. // Offset 0x40: Bit6 = 1 CPU1 Riser present
  80. if ((PresentStatus & CPU1_RISER_PRESENT) != 0) {
  81. Cpu1CardType = (UINT8)CardType;
  82. }
  83. if (OemIsMpBoot ()) {
  84. if (Cpu0CardType == CPLD_X16_X8_BOARD_ID) {
  85. if (Cpu1CardType == CPLD_X16_X8_BOARD_ID) {
  86. (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type1,
  87. sizeof (PcieDeviceToReport_2P_Type1));
  88. } else {
  89. (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type2,
  90. sizeof (PcieDeviceToReport_2P_Type2));
  91. }
  92. } else {
  93. if (Cpu1CardType == CPLD_X16_X8_BOARD_ID) {
  94. (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type3,
  95. sizeof (PcieDeviceToReport_2P_Type3));
  96. } else {
  97. (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type4,
  98. sizeof (PcieDeviceToReport_2P_Type4));
  99. }
  100. }
  101. } else {
  102. (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport,
  103. sizeof (PcieDeviceToReport));
  104. }
  105. }
  106. // Right now we only support 1P
  107. BOOLEAN
  108. OemIsSocketPresent (
  109. UINTN Socket
  110. )
  111. {
  112. UINT32 SocketMask = PcdGet32 (PcdSocketMask);
  113. return (BOOLEAN)((SocketMask & (1 << Socket)) ? TRUE : FALSE);
  114. }
  115. UINTN
  116. OemGetSocketNumber (
  117. VOID
  118. )
  119. {
  120. if(!OemIsMpBoot ()) {
  121. return 1;
  122. }
  123. return MAX_PROCESSOR_SOCKETS;
  124. }
  125. UINTN
  126. OemGetDdrChannel (
  127. VOID
  128. )
  129. {
  130. return MAX_MEMORY_CHANNELS;
  131. }
  132. UINTN
  133. OemGetDimmSlot (
  134. UINTN Socket,
  135. UINTN Channel
  136. )
  137. {
  138. return MAX_DIMM_PER_CHANNEL;
  139. }
  140. BOOLEAN
  141. OemIsMpBoot (
  142. VOID
  143. )
  144. {
  145. return PcdGet32 (PcdIsMPBoot);
  146. }
  147. VOID
  148. OemLpcInit (
  149. VOID
  150. )
  151. {
  152. LpcInit ();
  153. return;
  154. }
  155. UINT32
  156. OemIsWarmBoot (
  157. VOID
  158. )
  159. {
  160. return 0;
  161. }
  162. VOID
  163. OemBiosSwitch (
  164. UINT32 Master
  165. )
  166. {
  167. (VOID)Master;
  168. return;
  169. }
  170. BOOLEAN
  171. OemIsNeedDisableExpanderBuffer (
  172. VOID
  173. )
  174. {
  175. return TRUE;
  176. }
  177. UINTN OemGetCpuFreq (UINT8 Socket)
  178. {
  179. UINT8 BoardRevision;
  180. BoardRevision = MmioRead8 (CPLD_BASE_ADDRESS + CPLD_BOM_VER_FLAG);
  181. // Board revision 4 and higher run at 2.5GHz
  182. // Earlier revisions run at 2GHz
  183. if (BoardRevision >= CPLD_BOARD_REVISION_4TH) {
  184. return 2500000000;
  185. } else {
  186. return 2000000000;
  187. }
  188. }
  189. UINTN
  190. OemGetHccsFreq (
  191. VOID
  192. )
  193. {
  194. return HCCS_PLL_VALUE_2600;
  195. }