EarlyConfigPeimD06.c 3.7 KB

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  1. /** @file
  2. *
  3. * Copyright (c) 2018, Hisilicon Limited. All rights reserved.
  4. * Copyright (c) 2018, Linaro Limited. All rights reserved.
  5. *
  6. * SPDX-License-Identifier: BSD-2-Clause-Patent
  7. *
  8. **/
  9. #include <Uefi.h>
  10. #include <Library/ArmLib.h>
  11. #include <Library/CacheMaintenanceLib.h>
  12. #include <Library/DebugLib.h>
  13. #include <Library/IoLib.h>
  14. #include <Library/OemAddressMapLib.h>
  15. #include <Library/OemMiscLib.h>
  16. #include <Library/PcdLib.h>
  17. #include <Library/PlatformSysCtrlLib.h>
  18. #include <PiPei.h>
  19. #define PERI_SUBCTRL_BASE (0x40000000)
  20. #define MDIO_SUBCTRL_BASE (0x60000000)
  21. #define PCIE2_SUBCTRL_BASE (0xA0000000)
  22. #define PCIE0_SUBCTRL_BASE (0xB0000000)
  23. #define ALG_BASE (0xD0000000)
  24. #define SC_BROADCAST_EN_REG (0x16220)
  25. #define SC_BROADCAST_SCL1_ADDR0_REG (0x16230)
  26. #define SC_BROADCAST_SCL1_ADDR1_REG (0x16234)
  27. #define SC_BROADCAST_SCL2_ADDR0_REG (0x16238)
  28. #define SC_BROADCAST_SCL2_ADDR1_REG (0x1623C)
  29. #define SC_BROADCAST_SCL3_ADDR0_REG (0x16240)
  30. #define SC_BROADCAST_SCL3_ADDR1_REG (0x16244)
  31. #define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG (0x1000)
  32. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG (0x1010)
  33. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG (0x1014)
  34. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG (0x1018)
  35. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG (0x101C)
  36. #define PCIE_SUBCTRL_SC_REMAP_CTRL_REG (0x1200)
  37. #define SC_ITS_M3_INT_MUX_SEL_REG (0x21F0)
  38. #define SC_TM_CLKEN0_REG (0x2050)
  39. #define SC_TM_CLKEN0_REG_VALUE (0x3)
  40. #define SC_BROADCAST_EN_REG_VALUE (0x7)
  41. #define SC_BROADCAST_SCLx_ADDRx_REG_VALUE0 (0x0)
  42. #define SC_BROADCAST_SCLx_ADDRx_REG_VALUE1 (0x40016260)
  43. #define SC_BROADCAST_SCLx_ADDRx_REG_VALUE2 (0x60016260)
  44. #define SC_BROADCAST_SCLx_ADDRx_REG_VALUE3 (0x400)
  45. #define SC_ITS_M3_INT_MUX_SEL_REG_VALUE (0x7)
  46. #define PCIE_SUBCTRL_SC_REMAP_CTRL_REG_VALUE0 (0x0)
  47. #define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE0 (0x27)
  48. #define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE1 (0x2F)
  49. #define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE2 (0x77)
  50. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG_VALUE0 (0x178033)
  51. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG_VALUE0 (0x17003c)
  52. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0 (0x15003d)
  53. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE1 (0x170035)
  54. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG_VALUE0 (0x16003e)
  55. STATIC
  56. VOID
  57. QResetAp (
  58. VOID
  59. )
  60. {
  61. MmioWrite64 (FixedPcdGet64 (PcdMailBoxAddress), 0x0);
  62. (VOID)WriteBackInvalidateDataCacheRange (
  63. (VOID *)FixedPcdGet64 (PcdMailBoxAddress),
  64. sizeof (UINT64)
  65. );
  66. //SCCL A
  67. if (!PcdGet64 (PcdTrustedFirmwareEnable)) {
  68. StartUpBSP ();
  69. }
  70. }
  71. EFI_STATUS
  72. EFIAPI
  73. EarlyConfigEntry (
  74. IN EFI_PEI_FILE_HANDLE FileHandle,
  75. IN CONST EFI_PEI_SERVICES **PeiServices
  76. )
  77. {
  78. DEBUG ((DEBUG_INFO,"SMMU CONFIG........."));
  79. (VOID)SmmuConfigForBios ();
  80. DEBUG ((DEBUG_INFO,"Done\n"));
  81. DEBUG ((DEBUG_INFO,"AP CONFIG........."));
  82. (VOID)QResetAp ();
  83. DEBUG ((DEBUG_INFO,"Done\n"));
  84. DEBUG ((DEBUG_INFO,"MN CONFIG........."));
  85. (VOID)MN_CONFIG ();
  86. DEBUG ((DEBUG_INFO,"Done\n"));
  87. return EFI_SUCCESS;
  88. }