PlatformPciLib.c 10 KB

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  1. /** @file
  2. Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
  3. Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <Library/PcdLib.h>
  7. #include <Library/PlatformPciLib.h>
  8. UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0x8a0000000,0x8a0000000,0x8a0000000,0x8a0000000},
  9. {0x600a0000000,0x600a0000000,0x600a0000000,0x600a0000000, 0x700a0000000,0x700a0000000,0x700a0000000,0x700a0000000}};
  10. UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000, 0x8a0090000, 0x8a0200000, 0x8a00a0000, 0x8a00b0000},
  11. {0x600a0090000, 0x600a0200000, 0x600a00a0000, 0x600a00b0000, 0x700a0090000, 0x700a0200000, 0x700a00a0000, 0x700a00b0000}};
  12. UINT64 PCIE_PHY_BASE_1610 [PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000, 0x8a00c0000, 0x8a00d0000, 0x8a00e0000, 0x8a00f0000},
  13. {0x600a00c0000, 0x600a00d0000, 0x600a00e0000, 0x600a00f0000, 0x700a00c0000, 0x700a00d0000, 0x700a00e0000, 0x700a00f0000}};
  14. UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040},
  15. {0x400C6010040, 0x400C6010040, 0x400C6010040, 0x400C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040}};
  16. PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
  17. {// HostBridge 0
  18. /* Port 0 */
  19. {
  20. 0, //Segment
  21. PCI_HB0RB0_ECAM_BASE, //ecam
  22. 0x80, //BusBase
  23. 0x87, //BusLimit
  24. PCI_HB0RB0_IO_BASE, //IoBase
  25. (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
  26. PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
  27. PCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase
  28. (PCI_HB0RB0_PCI_BASE),//RbPciBar
  29. PCI_HB0RB0_PCIREGION_BASE, //PciRegionbase
  30. PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1 //PciRegionlimit
  31. },
  32. /* Port 1 */
  33. {
  34. 1, //Segment
  35. PCI_HB0RB1_ECAM_BASE,//ecam
  36. 0x90, //BusBase
  37. 0x97, //BusLimit
  38. (PCI_HB0RB1_IO_BASE), //IoBase
  39. (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit
  40. PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
  41. PCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase
  42. (PCI_HB0RB1_PCI_BASE), //RbPciBar
  43. PCI_HB0RB1_PCIREGION_BASE, //PciRegionbase
  44. PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1 //PciRegionlimit
  45. },
  46. /* Port 2 */
  47. {
  48. 2, //Segment
  49. PCI_HB0RB2_ECAM_BASE,
  50. 0xF8, //BusBase
  51. 0xFF, //BusLimit
  52. (PCI_HB0RB2_IO_BASE), //IOBase
  53. (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit
  54. PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
  55. PCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase
  56. (PCI_HB0RB2_PCI_BASE), //RbPciBar
  57. PCI_HB0RB2_PCIREGION_BASE, //PciRegionbase
  58. PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1 //PciRegionlimit
  59. },
  60. /* Port 3 */
  61. {
  62. 3, //Segment
  63. PCI_HB0RB3_ECAM_BASE,
  64. 0xb0, //BusBase
  65. 0xb7, //BusLimit
  66. (PCI_HB0RB3_IO_BASE), //IoBase
  67. (PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB3_IO_SIZE - 1), //IoLimit
  68. PCI_HB0RB3_CPUMEMREGIONBASE,
  69. PCI_HB0RB3_CPUIOREGIONBASE,
  70. (PCI_HB0RB3_PCI_BASE), //RbPciBar
  71. PCI_HB0RB3_PCIREGION_BASE, //PciRegionbase
  72. PCI_HB0RB3_PCIREGION_BASE + PCI_HB0RB3_PCIREGION_SIZE - 1 //PciRegionlimit
  73. },
  74. /* Port 4 */
  75. {
  76. 4, //Segment
  77. PCI_HB0RB4_ECAM_BASE, //ecam
  78. 0x88, //BusBase
  79. 0x8f, //BusLimit
  80. PCI_HB0RB4_IO_BASE, //IoBase
  81. (PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB4_IO_SIZE - 1), //IoLimit
  82. PCI_HB0RB4_CPUMEMREGIONBASE, //CpuMemRegionBase
  83. PCI_HB0RB4_CPUIOREGIONBASE, //CpuIoRegionBase
  84. (PCI_HB0RB4_PCI_BASE), //RbPciBar
  85. PCI_HB0RB4_PCIREGION_BASE, //PciRegionbase
  86. PCI_HB0RB4_PCIREGION_BASE + PCI_HB0RB4_PCIREGION_SIZE - 1 //PciRegionlimit
  87. },
  88. /* Port 5 */
  89. {
  90. 5, //Segment
  91. PCI_HB0RB5_ECAM_BASE,//ecam
  92. 0x78, //BusBase
  93. 0x7F, //BusLimit
  94. (PCI_HB0RB5_IO_BASE), //IoBase
  95. (PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB5_IO_SIZE - 1), //IoLimit
  96. PCI_HB0RB5_CPUMEMREGIONBASE, //CpuMemRegionBase
  97. PCI_HB0RB5_CPUIOREGIONBASE, //CpuIoRegionBase
  98. (PCI_HB0RB5_PCI_BASE), //RbPciBar
  99. PCI_HB0RB5_PCIREGION_BASE, //PciRegionbase
  100. PCI_HB0RB5_PCIREGION_BASE + PCI_HB0RB5_PCIREGION_SIZE - 1 //PciRegionlimit
  101. },
  102. /* Port 6 */
  103. {
  104. 6, //Segment
  105. PCI_HB0RB6_ECAM_BASE,
  106. 0xC0, //BusBase
  107. 0xC7, //BusLimit
  108. (PCI_HB0RB6_IO_BASE), //IOBase
  109. (PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB6_IO_SIZE - 1), //IoLimit
  110. PCI_HB0RB6_CPUMEMREGIONBASE, //CpuMemRegionBase
  111. PCI_HB0RB6_CPUIOREGIONBASE, //CpuIoRegionBase
  112. (PCI_HB0RB6_PCI_BASE), //RbPciBar
  113. PCI_HB0RB6_PCIREGION_BASE, //PciRegionbase
  114. PCI_HB0RB6_PCIREGION_BASE + PCI_HB0RB6_PCIREGION_SIZE - 1 //PciRegionlimit
  115. },
  116. /* Port 7 */
  117. {
  118. 7, //Segment
  119. PCI_HB0RB7_ECAM_BASE,
  120. 0x90, //BusBase
  121. 0x97, //BusLimit
  122. (PCI_HB0RB7_IO_BASE), //IoBase
  123. (PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB7_IO_SIZE - 1), //IoLimit
  124. PCI_HB0RB7_CPUMEMREGIONBASE,
  125. PCI_HB0RB7_CPUIOREGIONBASE,
  126. (PCI_HB0RB7_PCI_BASE), //RbPciBar
  127. PCI_HB0RB7_PCIREGION_BASE, //PciRegionbase
  128. PCI_HB0RB7_PCIREGION_BASE + PCI_HB0RB7_PCIREGION_SIZE - 1 //PciRegionlimit
  129. }
  130. },
  131. {// HostBridge 1
  132. /* Port 0 */
  133. {
  134. 8, //Segment
  135. PCI_HB1RB0_ECAM_BASE,
  136. 0x80, //BusBase
  137. 0x87, //BusLimit
  138. PCI_HB1RB0_IO_BASE, //IoBase
  139. (PCI_HB1RB0_CPUIOREGIONBASE + PCI_HB1RB0_IO_SIZE - 1), //IoLimit
  140. PCI_HB1RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
  141. PCI_HB1RB0_CPUIOREGIONBASE, //CpuIoRegionBase
  142. (PCI_HB1RB0_PCI_BASE), //RbPciBar
  143. PCI_HB1RB0_PCIREGION_BASE, //PciRegionbase
  144. PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit
  145. },
  146. /* Port 1 */
  147. {
  148. 9, //Segment
  149. PCI_HB1RB1_ECAM_BASE,
  150. 0x90, //BusBase
  151. 0x97, //BusLimit
  152. PCI_HB1RB1_IO_BASE, //IoBase
  153. (PCI_HB1RB1_CPUIOREGIONBASE + PCI_HB1RB1_IO_SIZE - 1), //IoLimit
  154. PCI_HB1RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
  155. PCI_HB1RB1_CPUIOREGIONBASE, //CpuIoRegionBase
  156. (PCI_HB1RB1_PCI_BASE), //RbPciBar
  157. PCI_HB1RB1_PCIREGION_BASE, //PciRegionbase
  158. PCI_HB1RB1_PCIREGION_BASE + PCI_HB1RB1_PCIREGION_SIZE - 1 //PciRegionlimit
  159. },
  160. /* Port 2 */
  161. {
  162. 0xa, //Segment
  163. PCI_HB1RB2_ECAM_BASE,
  164. 0x10, //BusBase
  165. 0x1f, //BusLimit
  166. PCI_HB1RB2_IO_BASE, //IoBase
  167. (PCI_HB1RB2_CPUIOREGIONBASE + PCI_HB1RB2_IO_SIZE - 1), //IoLimit
  168. PCI_HB1RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
  169. PCI_HB1RB2_CPUIOREGIONBASE, //CpuIoRegionBase
  170. (PCI_HB1RB2_PCI_BASE), //RbPciBar
  171. PCI_HB1RB2_PCIREGION_BASE, //PciRegionbase
  172. PCI_HB1RB2_PCIREGION_BASE + PCI_HB1RB2_PCIREGION_SIZE - 1 //PciRegionlimit
  173. },
  174. /* Port 3 */
  175. {
  176. 0xb, //Segment
  177. PCI_HB1RB3_ECAM_BASE,
  178. 0xb0, //BusBase
  179. 0xb7, //BusLimit
  180. PCI_HB1RB3_IO_BASE, //IoBase
  181. (PCI_HB1RB3_CPUIOREGIONBASE + PCI_HB1RB3_IO_SIZE - 1), //IoLimit
  182. PCI_HB1RB3_CPUMEMREGIONBASE, //CpuMemRegionBase
  183. PCI_HB1RB3_CPUIOREGIONBASE, //CpuIoRegionBase
  184. (PCI_HB1RB3_PCI_BASE), //RbPciBar
  185. PCI_HB1RB3_PCIREGION_BASE, //PciRegionbase
  186. PCI_HB1RB3_PCIREGION_BASE + PCI_HB1RB3_PCIREGION_SIZE - 1 //PciRegionlimit
  187. },
  188. /* Port 4 */
  189. {
  190. 0xc, //Segment
  191. PCI_HB1RB4_ECAM_BASE,
  192. 0x20, //BusBase
  193. 0x2f, //BusLimit
  194. PCI_HB1RB4_IO_BASE, //IoBase
  195. (PCI_HB1RB4_CPUIOREGIONBASE + PCI_HB1RB4_IO_SIZE - 1), //IoLimit
  196. PCI_HB1RB4_CPUMEMREGIONBASE, //CpuMemRegionBase
  197. PCI_HB1RB4_CPUIOREGIONBASE, //CpuIoRegionBase
  198. (PCI_HB1RB4_PCI_BASE), //RbPciBar
  199. PCI_HB1RB4_PCIREGION_BASE, //PciRegionbase
  200. PCI_HB1RB4_PCIREGION_BASE + PCI_HB1RB4_PCIREGION_SIZE - 1 //PciRegionlimit
  201. },
  202. /* Port 5 */
  203. {
  204. 0xd, //Segment
  205. PCI_HB1RB5_ECAM_BASE,
  206. 0x30, //BusBase
  207. 0x3f, //BusLimit
  208. PCI_HB1RB5_IO_BASE, //IoBase
  209. (PCI_HB1RB5_CPUIOREGIONBASE + PCI_HB1RB5_IO_SIZE - 1), //IoLimit
  210. PCI_HB1RB5_CPUMEMREGIONBASE, //CpuMemRegionBase
  211. PCI_HB1RB5_CPUIOREGIONBASE, //CpuIoRegionBase
  212. (PCI_HB1RB5_PCI_BASE), //RbPciBar
  213. PCI_HB1RB5_PCIREGION_BASE, //PciRegionbase
  214. PCI_HB1RB5_PCIREGION_BASE + PCI_HB1RB5_PCIREGION_SIZE - 1 //PciRegionlimit
  215. },
  216. /* Port 6 */
  217. {
  218. 0xe, //Segment
  219. PCI_HB1RB6_ECAM_BASE,
  220. 0xa8, //BusBase
  221. 0xaf, //BusLimit
  222. PCI_HB1RB6_IO_BASE, //IoBase
  223. (PCI_HB1RB6_CPUIOREGIONBASE + PCI_HB1RB6_IO_SIZE - 1), //IoLimit
  224. PCI_HB1RB6_CPUMEMREGIONBASE, //CpuMemRegionBase
  225. PCI_HB1RB6_CPUIOREGIONBASE, //CpuIoRegionBase
  226. (PCI_HB1RB6_PCI_BASE), //RbPciBar
  227. PCI_HB1RB6_PCIREGION_BASE, //PciRegionbase
  228. PCI_HB1RB6_PCIREGION_BASE + PCI_HB1RB6_PCIREGION_SIZE - 1 //PciRegionlimit
  229. },
  230. /* Port 7 */
  231. {
  232. 0xf, //Segment
  233. PCI_HB1RB7_ECAM_BASE,
  234. 0xb8, //BusBase
  235. 0xbf, //BusLimit
  236. PCI_HB1RB7_IO_BASE, //IoBase
  237. (PCI_HB1RB7_CPUIOREGIONBASE + PCI_HB1RB7_IO_SIZE - 1), //IoLimit
  238. PCI_HB1RB7_CPUMEMREGIONBASE, //CpuMemRegionBase
  239. PCI_HB1RB7_CPUIOREGIONBASE, //CpuIoRegionBase
  240. (PCI_HB1RB7_PCI_BASE), //RbPciBar
  241. PCI_HB1RB7_PCIREGION_BASE, //PciRegionbase
  242. PCI_HB1RB7_PCIREGION_BASE + PCI_HB1RB7_PCIREGION_SIZE - 1 //PciRegionlimit
  243. }
  244. }
  245. };