PlatformPciLib.c 4.2 KB

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  1. /** @file
  2. Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
  3. Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include <Library/PcdLib.h>
  7. #include <Library/PlatformPciLib.h>
  8. UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000},
  9. {0xb0000000,0xb0000000,0xb0000000,0xb0000000, 0xb0000000,0xb0000000,0xb0000000,0xb0000000}};
  10. UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000},
  11. {0xb0090000, 0xb0200000, 0xb00a0000, 0xb00b0000}};
  12. UINT64 PCIE_PHY_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000},
  13. {0xb00c0000,0xb00d0000, 0xb00e0000, 0xb00f0000}};
  14. UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040},
  15. {0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040}};
  16. PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
  17. {// HostBridge 0
  18. /* Port 0 */
  19. {
  20. 0, //Segment
  21. PCI_HB0RB0_ECAM_BASE, //ecam
  22. 0, //BusBase
  23. 31, //BusLimit
  24. PCI_HB0RB0_IO_BASE, //IoBase
  25. (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
  26. PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
  27. PCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase
  28. (PCI_HB0RB0_PCI_BASE), //RbPciBar
  29. PCI_HB0RB0_PCIREGION_BASE, //PciRegionBase
  30. PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //PciRegionLimit
  31. },
  32. /* Port 1 */
  33. {
  34. 1, //Segment
  35. PCI_HB0RB1_ECAM_BASE,//ecam
  36. 224, //BusBase
  37. 254, //BusLimit
  38. (PCI_HB0RB1_IO_BASE), //IoBase
  39. (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit
  40. PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
  41. PCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase
  42. (PCI_HB0RB1_PCI_BASE), //RbPciBar
  43. PCI_HB0RB1_PCIREGION_BASE, //PciRegionBase
  44. PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //PciRegionLimit
  45. },
  46. /* Port 2 */
  47. {
  48. 2, //Segment
  49. PCI_HB0RB2_ECAM_BASE,
  50. 128, //BusBase
  51. 159, //BusLimit
  52. (PCI_HB0RB2_IO_BASE), //IOBase
  53. (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit
  54. PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
  55. PCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase
  56. (PCI_HB0RB2_PCI_BASE), //RbPciBar
  57. PCI_HB0RB2_PCIREGION_BASE, //PciRegionBase
  58. PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //PciRegionLimit
  59. },
  60. /* Port 3 */
  61. {
  62. 3, //Segment
  63. PCI_HB0RB3_ECAM_BASE,
  64. 96, //BusBase
  65. 127, //BusLimit
  66. (0), //IoBase
  67. (0), //IoLimit
  68. 0,
  69. 0,
  70. (PCI_HB0RB3_PCI_BASE), //RbPciBar
  71. 0,
  72. 0
  73. }
  74. },
  75. {// HostBridge 1
  76. /* Port 0 */
  77. {
  78. 4, //Segment
  79. PCI_HB1RB0_ECAM_BASE,
  80. 128, //BusBase
  81. 159, //BusLimit
  82. (0), //IoBase
  83. (0), //IoLimit
  84. 0,
  85. 0,
  86. (PCI_HB1RB0_PCI_BASE), //RbPciBar
  87. 0,
  88. 0
  89. },
  90. /* Port 1 */
  91. {
  92. 5, //Segment
  93. PCI_HB1RB1_ECAM_BASE,
  94. 160, //BusBase
  95. 191, //BusLimit
  96. (0), //IoBase
  97. (0), //IoLimit
  98. 0,
  99. 0,
  100. (PCI_HB1RB1_PCI_BASE), //RbPciBar
  101. 0,
  102. 0
  103. },
  104. /* Port 2 */
  105. {
  106. 6, //Segment
  107. PCI_HB1RB2_ECAM_BASE,
  108. 192, //BusBase
  109. 223, //BusLimit
  110. (0), //IoBase
  111. (0), //IoLimit
  112. 0,
  113. 0,
  114. (PCI_HB1RB2_PCI_BASE), //RbPciBar
  115. 0,
  116. 0
  117. },
  118. /* Port 3 */
  119. {
  120. 7, //Segment
  121. PCI_HB1RB3_ECAM_BASE,
  122. 224, //BusBase
  123. 255, //BusLimit
  124. (0), //IoBase
  125. (0), //IoLimit
  126. 0,
  127. 0,
  128. (PCI_HB1RB3_PCI_BASE), //RbPciBar
  129. 0,
  130. 0
  131. }
  132. }
  133. };