BoardFeature2PHi1610.c 7.0 KB

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  1. /** @file
  2. *
  3. * Copyright (c) 2015, Hisilicon Limited. All rights reserved.
  4. * Copyright (c) 2015, Linaro Limited. All rights reserved.
  5. *
  6. * SPDX-License-Identifier: BSD-2-Clause-Patent
  7. *
  8. **/
  9. #include <Uefi.h>
  10. #include <Library/DebugLib.h>
  11. #include <Library/BaseMemoryLib.h>
  12. #include <Protocol/Smbios.h>
  13. #include <IndustryStandard/SmBios.h>
  14. #include <PlatformArch.h>
  15. #include <Library/OemMiscLib.h>
  16. #include <Library/I2CLib.h>
  17. #include <Library/HiiLib.h>
  18. I2C_DEVICE gRtcDevice = {
  19. .Socket = 0,
  20. .Port = 6,
  21. .DeviceType = DEVICE_TYPE_SPD,
  22. .SlaveDeviceAddress = 0x68
  23. };
  24. SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] =
  25. {
  26. {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
  27. };
  28. SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] =
  29. {
  30. {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
  31. };
  32. SERDES_PARAM gSerdesParam = {
  33. .Hilink0Mode = EmHilink0Pcie1X8,
  34. .Hilink1Mode = EmHilink1Pcie0X8,
  35. .Hilink2Mode = EmHilink2Pcie2X8,
  36. .Hilink3Mode = 0x0,
  37. .Hilink4Mode = 0xF,
  38. .Hilink5Mode = EmHilink5Sas1X4,
  39. .Hilink6Mode = 0x0,
  40. .UseSsc = 0,
  41. };
  42. SERDES_PARAM gSerdesParam0 = {
  43. .Hilink0Mode = EmHilink0Hccs1X8Width16,
  44. .Hilink1Mode = EmHilink1Hccs0X8Width16,
  45. .Hilink2Mode = EmHilink2Pcie2X8,
  46. .Hilink3Mode = 0x0,
  47. .Hilink4Mode = 0xF,
  48. .Hilink5Mode = EmHilink5Sas1X4,
  49. .Hilink6Mode = 0x0,
  50. .UseSsc = 0,
  51. };
  52. SERDES_PARAM gSerdesParam1 = {
  53. .Hilink0Mode = EmHilink0Hccs1X8Width16,
  54. .Hilink1Mode = EmHilink1Hccs0X8Width16,
  55. .Hilink2Mode = EmHilink2Pcie2X8,
  56. .Hilink3Mode = 0x0,
  57. .Hilink4Mode = 0xF,
  58. .Hilink5Mode = EmHilink5Pcie3X4,
  59. .Hilink6Mode = 0xF,
  60. .UseSsc = 0,
  61. };
  62. EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId)
  63. {
  64. if (ParamA == NULL) {
  65. DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
  66. return EFI_INVALID_PARAMETER;
  67. }
  68. (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA));
  69. return EFI_SUCCESS;
  70. }
  71. VOID OemPcieResetAndOffReset(void)
  72. {
  73. return;
  74. }
  75. SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = {
  76. // PCIe0 Slot 1
  77. {
  78. { // Hdr
  79. EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type,
  80. 0, // Length,
  81. 0 // Handle
  82. },
  83. 1, // SlotDesignation
  84. SlotTypePciExpressX8, // SlotType
  85. SlotDataBusWidth8X, // SlotDataBusWidth
  86. SlotUsageAvailable, // SlotUsage
  87. SlotLengthOther, // SlotLength
  88. 0x0001, // SlotId
  89. { // SlotCharacteristics1
  90. 0, // CharacteristicsUnknown :1;
  91. 0, // Provides50Volts :1;
  92. 0, // Provides33Volts :1;
  93. 0, // SharedSlot :1;
  94. 0, // PcCard16Supported :1;
  95. 0, // CardBusSupported :1;
  96. 0, // ZoomVideoSupported :1;
  97. 0 // ModemRingResumeSupported:1;
  98. },
  99. { // SlotCharacteristics2
  100. 0, // PmeSignalSupported :1;
  101. 0, // HotPlugDevicesSupported :1;
  102. 0, // SmbusSignalSupported :1;
  103. 0 // Reserved :5;
  104. },
  105. 0x00, // SegmentGroupNum
  106. 0x00, // BusNum
  107. 0 // DevFuncNum
  108. },
  109. // PCIe0 Slot 4
  110. {
  111. { // Hdr
  112. EFI_SMBIOS_TYPE_SYSTEM_SLOTS, // Type,
  113. 0, // Length,
  114. 0 // Handle
  115. },
  116. 1, // SlotDesignation
  117. SlotTypePciExpressX8, // SlotType
  118. SlotDataBusWidth8X, // SlotDataBusWidth
  119. SlotUsageAvailable, // SlotUsage
  120. SlotLengthOther, // SlotLength
  121. 0x0004, // SlotId
  122. { // SlotCharacteristics1
  123. 0, // CharacteristicsUnknown :1;
  124. 0, // Provides50Volts :1;
  125. 0, // Provides33Volts :1;
  126. 0, // SharedSlot :1;
  127. 0, // PcCard16Supported :1;
  128. 0, // CardBusSupported :1;
  129. 0, // ZoomVideoSupported :1;
  130. 0 // ModemRingResumeSupported:1;
  131. },
  132. { // SlotCharacteristics2
  133. 0, // PmeSignalSupported :1;
  134. 0, // HotPlugDevicesSupported :1;
  135. 0, // SmbusSignalSupported :1;
  136. 0 // Reserved :5;
  137. },
  138. 0x00, // SegmentGroupNum
  139. 0x00, // BusNum
  140. 0 // DevFuncNum
  141. }
  142. };
  143. UINT8 OemGetPcieSlotNumber ()
  144. {
  145. return sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9);
  146. }
  147. EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = {
  148. {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001), STRING_TOKEN(STR_LEMON_C10_DIMM_002)},
  149. {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011), STRING_TOKEN(STR_LEMON_C10_DIMM_012)},
  150. {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021), STRING_TOKEN(STR_LEMON_C10_DIMM_022)},
  151. {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031), STRING_TOKEN(STR_LEMON_C10_DIMM_032)}},
  152. {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101), STRING_TOKEN(STR_LEMON_C10_DIMM_102)},
  153. {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111), STRING_TOKEN(STR_LEMON_C10_DIMM_112)},
  154. {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121), STRING_TOKEN(STR_LEMON_C10_DIMM_122)},
  155. {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131), STRING_TOKEN(STR_LEMON_C10_DIMM_132)}}
  156. };
  157. EFI_HII_HANDLE
  158. EFIAPI
  159. OemGetPackages (
  160. )
  161. {
  162. return HiiAddPackages (
  163. &gEfiCallerIdGuid,
  164. NULL,
  165. OemMiscLib2PStrings,
  166. NULL,
  167. NULL
  168. );
  169. }