EarlyConfigPeimD03.c 8.7 KB

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  1. /** @file
  2. *
  3. * Copyright (c) 2016, Hisilicon Limited. All rights reserved.
  4. * Copyright (c) 2016, Linaro Limited. All rights reserved.
  5. *
  6. * SPDX-License-Identifier: BSD-2-Clause-Patent
  7. *
  8. **/
  9. #include <Uefi.h>
  10. #include <PiPei.h>
  11. #include <Library/DebugLib.h>
  12. #include <Library/PcdLib.h>
  13. #include <Library/IoLib.h>
  14. #include <Library/CacheMaintenanceLib.h>
  15. #include <PlatformArch.h>
  16. #include <Library/PlatformSysCtrlLib.h>
  17. #include <Library/OemMiscLib.h>
  18. #include <Library/OemAddressMapLib.h>
  19. #include <Library/ArmLib.h>
  20. #define PERI_SUBCTRL_BASE (0x40000000)
  21. #define MDIO_SUBCTRL_BASE (0x60000000)
  22. #define PCIE2_SUBCTRL_BASE (0xA0000000)
  23. #define PCIE0_SUBCTRL_BASE (0xB0000000)
  24. #define ALG_BASE (0xD0000000)
  25. #define SC_BROADCAST_EN_REG (0x16220)
  26. #define SC_BROADCAST_SCL1_ADDR0_REG (0x16230)
  27. #define SC_BROADCAST_SCL1_ADDR1_REG (0x16234)
  28. #define SC_BROADCAST_SCL2_ADDR0_REG (0x16238)
  29. #define SC_BROADCAST_SCL2_ADDR1_REG (0x1623C)
  30. #define SC_BROADCAST_SCL3_ADDR0_REG (0x16240)
  31. #define SC_BROADCAST_SCL3_ADDR1_REG (0x16244)
  32. #define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG (0x1000)
  33. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG (0x1010)
  34. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG (0x1014)
  35. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG (0x1018)
  36. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG (0x101C)
  37. #define PCIE_SUBCTRL_SC_REMAP_CTRL_REG (0x1200)
  38. #define SC_ITS_M3_INT_MUX_SEL_REG (0x21F0)
  39. #define SC_TM_CLKEN0_REG (0x2050)
  40. #define SC_TM_CLKEN0_REG_VALUE (0x3)
  41. #define SC_BROADCAST_EN_REG_VALUE (0x7)
  42. #define SC_BROADCAST_SCLx_ADDRx_REG_VALUE0 (0x0)
  43. #define SC_BROADCAST_SCLx_ADDRx_REG_VALUE1 (0x40016260)
  44. #define SC_BROADCAST_SCLx_ADDRx_REG_VALUE2 (0x60016260)
  45. #define SC_BROADCAST_SCLx_ADDRx_REG_VALUE3 (0x400)
  46. #define SC_ITS_M3_INT_MUX_SEL_REG_VALUE (0x7)
  47. #define PCIE_SUBCTRL_SC_REMAP_CTRL_REG_VALUE0 (0x0)
  48. #define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE0 (0x27)
  49. #define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE1 (0x2F)
  50. #define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE2 (0x77)
  51. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG_VALUE0 (0x178033)
  52. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG_VALUE0 (0x17003c)
  53. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0 (0x15003d)
  54. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE1 (0x170035)
  55. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG_VALUE0 (0x16003e)
  56. VOID PlatformTimerStart (VOID)
  57. {
  58. // Timer0 clock enable
  59. MmioWrite32 (PERI_SUBCTRL_BASE + SC_TM_CLKEN0_REG, SC_TM_CLKEN0_REG_VALUE);
  60. }
  61. void QResetAp(VOID)
  62. {
  63. MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0);
  64. (void)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8);
  65. ArmDataSynchronizationBarrier ();
  66. ArmInstructionSynchronizationBarrier ();
  67. //SCCL A
  68. if (!PcdGet64 (PcdTrustedFirmwareEnable))
  69. {
  70. StartUpBSP ();
  71. }
  72. }
  73. EFI_STATUS
  74. EFIAPI
  75. EarlyConfigEntry (
  76. IN EFI_PEI_FILE_HANDLE FileHandle,
  77. IN CONST EFI_PEI_SERVICES **PeiServices
  78. )
  79. {
  80. DEBUG((EFI_D_INFO,"SMMU CONFIG........."));
  81. (VOID)SmmuConfigForOS();
  82. DEBUG((EFI_D_INFO,"Done\n"));
  83. DEBUG((EFI_D_INFO,"AP CONFIG........."));
  84. (VOID)QResetAp();
  85. DEBUG((EFI_D_INFO,"Done\n"));
  86. DEBUG((EFI_D_INFO,"MN CONFIG........."));
  87. (VOID)MN_CONFIG();
  88. DEBUG((EFI_D_INFO,"Done\n"));
  89. if(OemIsMpBoot())
  90. {
  91. DEBUG((EFI_D_INFO,"Event Broadcast CONFIG........."));
  92. //EVENT broadcast
  93. MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
  94. MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
  95. MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
  96. MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
  97. MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
  98. MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
  99. MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
  100. MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
  101. MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
  102. MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
  103. MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
  104. MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
  105. MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
  106. MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
  107. MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
  108. MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
  109. MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
  110. MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
  111. MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
  112. MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
  113. MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
  114. MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
  115. MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
  116. MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
  117. MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
  118. MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
  119. MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
  120. MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
  121. DEBUG((EFI_D_INFO,"Done\n"));
  122. }
  123. DEBUG((EFI_D_INFO,"PCIE RAM Address CONFIG........."));
  124. if(OemIsMpBoot())
  125. {
  126. MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE0);
  127. MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0);
  128. MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE1);
  129. MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG_VALUE0);
  130. MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE1);
  131. }
  132. else
  133. {
  134. MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_REMAP_CTRL_REG, PCIE_SUBCTRL_SC_REMAP_CTRL_REG_VALUE0);
  135. MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE2);
  136. MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG_VALUE0);
  137. MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0);
  138. MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG_VALUE0);
  139. }
  140. DEBUG((EFI_D_INFO,"Done\n"));
  141. MmioWrite32(ALG_BASE + SC_ITS_M3_INT_MUX_SEL_REG, SC_ITS_M3_INT_MUX_SEL_REG_VALUE);
  142. DEBUG((EFI_D_INFO,"Timer CONFIG........."));
  143. PlatformTimerStart ();
  144. DEBUG((EFI_D_INFO,"Done\n"));
  145. return EFI_SUCCESS;
  146. }