DwEmmcDxe.c 21 KB

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  1. /** @file
  2. This file implement the MMC Host Protocol for the DesignWare eMMC.
  3. WARNING:
  4. This driver fails to follow the UEFI driver model without a good
  5. reason, and only remains in the tree because it is still used by
  6. a small number of platforms. It will be removed when no longer used.
  7. Copyright (c) 2014-2017, Linaro Limited. All rights reserved.
  8. SPDX-License-Identifier: BSD-2-Clause-Patent
  9. **/
  10. #include <Library/BaseMemoryLib.h>
  11. #include <Library/CacheMaintenanceLib.h>
  12. #include <Library/DebugLib.h>
  13. #include <Library/DevicePathLib.h>
  14. #include <Library/IoLib.h>
  15. #include <Library/MemoryAllocationLib.h>
  16. #include <Library/PcdLib.h>
  17. #include <Library/TimerLib.h>
  18. #include <Library/UefiBootServicesTableLib.h>
  19. #include <Library/UefiLib.h>
  20. #include <Protocol/MmcHost.h>
  21. #include "DwEmmc.h"
  22. #define DWEMMC_DESC_PAGE 1
  23. #define DWEMMC_BLOCK_SIZE 512
  24. #define DWEMMC_DMA_BUF_SIZE (512 * 8)
  25. #define DWEMMC_MAX_DESC_PAGES 512
  26. /* Internal IDMAC interrupt defines */
  27. #define DWMCI_IDINTEN_RI (1 << 1)
  28. #define DWMCI_IDINTEN_TI (1 << 0)
  29. #define DWMCI_IDINTEN_MASK (DWMCI_IDINTEN_TI | \
  30. DWMCI_IDINTEN_RI)
  31. #define DWMCI_DMA_EN (1 << 5)
  32. typedef struct {
  33. UINT32 Des0;
  34. UINT32 Des1;
  35. UINT32 Des2;
  36. UINT32 Des3;
  37. } DWEMMC_IDMAC_DESCRIPTOR;
  38. EFI_MMC_HOST_PROTOCOL *gpMmcHost;
  39. DWEMMC_IDMAC_DESCRIPTOR *gpIdmacDesc;
  40. EFI_GUID mDwEmmcDevicePathGuid = EFI_CALLER_ID_GUID;
  41. STATIC UINT32 mDwEmmcCommand;
  42. STATIC UINT32 mDwEmmcArgument;
  43. STATIC UINT32 app_cmd = 0;
  44. EFI_STATUS
  45. DwEmmcReadBlockData (
  46. IN EFI_MMC_HOST_PROTOCOL *This,
  47. IN EFI_LBA Lba,
  48. IN UINTN Length,
  49. IN UINT32* Buffer
  50. );
  51. BOOLEAN
  52. DwEmmcIsPowerOn (
  53. VOID
  54. )
  55. {
  56. return TRUE;
  57. }
  58. EFI_STATUS
  59. DwEmmcInitialize (
  60. VOID
  61. )
  62. {
  63. DEBUG ((DEBUG_BLKIO, "DwEmmcInitialize()"));
  64. return EFI_SUCCESS;
  65. }
  66. BOOLEAN
  67. DwEmmcIsCardPresent (
  68. IN EFI_MMC_HOST_PROTOCOL *This
  69. )
  70. {
  71. return TRUE;
  72. }
  73. BOOLEAN
  74. DwEmmcIsReadOnly (
  75. IN EFI_MMC_HOST_PROTOCOL *This
  76. )
  77. {
  78. return FALSE;
  79. }
  80. BOOLEAN
  81. DwEmmcIsDmaSupported (
  82. IN EFI_MMC_HOST_PROTOCOL *This
  83. )
  84. {
  85. return TRUE;
  86. }
  87. void mmc_debug_printf()
  88. {
  89. //UINT32 data, data1,
  90. UINT32 addr = 0x16020000;
  91. //data = MmioRead32(0x13020170);
  92. //data1 = MmioRead32(0x13020178);
  93. //DEBUG ((DEBUG_INFO, "\nCLK 0 0x%x clk 1 0x%x\n", data, data1));
  94. for (; addr <= 0x16020098; addr+=4) {
  95. if ((addr & 0xf) == 0x0) {
  96. DEBUG ((DEBUG_INFO,"\naddr 0x%08x:", addr));
  97. }
  98. DEBUG ((DEBUG_INFO, " %08x", MmioRead32(addr)));
  99. }
  100. DEBUG ((DEBUG_INFO, "\n"));
  101. }
  102. EFI_STATUS
  103. DwEmmcBuildDevicePath (
  104. IN EFI_MMC_HOST_PROTOCOL *This,
  105. IN EFI_DEVICE_PATH_PROTOCOL **DevicePath
  106. )
  107. {
  108. EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode;
  109. NewDevicePathNode = CreateDeviceNode (HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH));
  110. CopyGuid (& ((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid, &mDwEmmcDevicePathGuid);
  111. *DevicePath = NewDevicePathNode;
  112. return EFI_SUCCESS;
  113. }
  114. EFI_STATUS
  115. DwEmmcUpdateClock (
  116. VOID
  117. )
  118. {
  119. UINT32 Data;
  120. /* CMD_UPDATE_CLK */
  121. Data = BIT_CMD_WAIT_PRVDATA_COMPLETE | BIT_CMD_UPDATE_CLOCK_ONLY |
  122. BIT_CMD_START;
  123. MmioWrite32 (DWEMMC_CMD, Data);
  124. while (1) {
  125. Data = MmioRead32 (DWEMMC_CMD);
  126. if (!(Data & CMD_START_BIT)) {
  127. break;
  128. }
  129. Data = MmioRead32 (DWEMMC_RINTSTS);
  130. if (Data & DWEMMC_INT_HLE) {
  131. Print (L"failed to update mmc clock frequency\n");
  132. return EFI_DEVICE_ERROR;
  133. }
  134. }
  135. return EFI_SUCCESS;
  136. }
  137. EFI_STATUS
  138. DwEmmcSetClock (
  139. IN UINTN ClockFreq
  140. )
  141. {
  142. UINT32 Divider, Rate, Data;
  143. EFI_STATUS Status;
  144. BOOLEAN Found = FALSE;
  145. for (Divider = 1; Divider < 256; Divider++) {
  146. Rate = PcdGet32 (PcdDwEmmcDxeClockFrequencyInHz);
  147. if ((Rate / (2 * Divider)) <= ClockFreq) {
  148. Found = TRUE;
  149. break;
  150. }
  151. }
  152. if (Found == FALSE) {
  153. return EFI_NOT_FOUND;
  154. }
  155. // Wait until MMC is idle
  156. do {
  157. Data = MmioRead32 (DWEMMC_STATUS);
  158. } while (Data & DWEMMC_STS_DATA_BUSY);
  159. // Disable MMC clock first
  160. MmioWrite32 (DWEMMC_CLKENA, 0);
  161. Status = DwEmmcUpdateClock ();
  162. ASSERT (!EFI_ERROR (Status));
  163. MmioWrite32 (DWEMMC_CLKDIV, Divider);
  164. Status = DwEmmcUpdateClock ();
  165. ASSERT (!EFI_ERROR (Status));
  166. // Enable MMC clock
  167. MmioWrite32 (DWEMMC_CLKENA, 1);
  168. MmioWrite32 (DWEMMC_CLKSRC, 0);
  169. Status = DwEmmcUpdateClock ();
  170. ASSERT (!EFI_ERROR (Status));
  171. return EFI_SUCCESS;
  172. }
  173. EFI_STATUS
  174. DwEmmcNotifyState (
  175. IN EFI_MMC_HOST_PROTOCOL *This,
  176. IN MMC_STATE State
  177. )
  178. {
  179. UINT32 Data;
  180. EFI_STATUS Status;
  181. switch (State) {
  182. case MmcInvalidState:
  183. return EFI_INVALID_PARAMETER;
  184. case MmcHwInitializationState:
  185. MmioWrite32 (DWEMMC_PWREN, 1);
  186. // If device already turn on then restart it
  187. Data = DWEMMC_CTRL_RESET_ALL;
  188. MmioWrite32 (DWEMMC_CTRL, Data);
  189. do {
  190. // Wait until reset operation finished
  191. Data = MmioRead32 (DWEMMC_CTRL);
  192. } while (Data & DWEMMC_CTRL_RESET_ALL);
  193. // Setup clock that could not be higher than 400KHz.
  194. Status = DwEmmcSetClock (400000);
  195. ASSERT (!EFI_ERROR (Status));
  196. // Wait clock stable
  197. MicroSecondDelay (100);
  198. MmioWrite32 (DWEMMC_CTYPE, 0);
  199. MmioWrite32 (DWEMMC_RINTSTS, ~0);
  200. MmioWrite32 (DWEMMC_INTMASK, 0);
  201. MmioWrite32 (DWEMMC_TMOUT, ~0);
  202. MmioWrite32 (DWEMMC_IDINTEN, 0);
  203. MmioWrite32 (DWEMMC_BMOD, DWEMMC_IDMAC_SWRESET);
  204. MmioWrite32 (DWEMMC_BLKSIZ, DWEMMC_BLOCK_SIZE);
  205. do {
  206. Data = MmioRead32 (DWEMMC_BMOD);
  207. } while (Data & DWEMMC_IDMAC_SWRESET);
  208. MmioWrite32 (DWEMMC_IDINTEN, 0x3);
  209. break;
  210. case MmcIdleState:
  211. break;
  212. case MmcReadyState:
  213. break;
  214. case MmcIdentificationState:
  215. break;
  216. case MmcStandByState:
  217. break;
  218. case MmcTransferState:
  219. break;
  220. case MmcSendingDataState:
  221. break;
  222. case MmcReceiveDataState:
  223. break;
  224. case MmcProgrammingState:
  225. break;
  226. case MmcDisconnectState:
  227. break;
  228. default:
  229. return EFI_INVALID_PARAMETER;
  230. }
  231. return EFI_SUCCESS;
  232. }
  233. // Need to prepare DMA buffer first before sending commands to MMC card
  234. BOOLEAN
  235. IsPendingReadCommand (
  236. IN MMC_CMD MmcCmd
  237. )
  238. {
  239. UINTN Mask;
  240. Mask = BIT_CMD_DATA_EXPECTED | BIT_CMD_READ;
  241. if ((MmcCmd & Mask) == Mask) {
  242. return TRUE;
  243. }
  244. return FALSE;
  245. }
  246. BOOLEAN
  247. IsPendingWriteCommand (
  248. IN MMC_CMD MmcCmd
  249. )
  250. {
  251. UINTN Mask;
  252. Mask = BIT_CMD_DATA_EXPECTED | BIT_CMD_WRITE;
  253. if ((MmcCmd & Mask) == Mask) {
  254. return TRUE;
  255. }
  256. return FALSE;
  257. }
  258. EFI_STATUS
  259. SendCommand (
  260. IN MMC_CMD MmcCmd,
  261. IN UINT32 Argument
  262. )
  263. {
  264. UINT32 Data, ErrMask;
  265. // Wait until MMC is idle
  266. do {
  267. Data = MmioRead32 (DWEMMC_STATUS);
  268. } while (Data & DWEMMC_STS_DATA_BUSY);
  269. MmioWrite32 (DWEMMC_RINTSTS, ~0);
  270. MmioWrite32 (DWEMMC_CMDARG, Argument);
  271. MmioWrite32 (DWEMMC_CMD, MmcCmd);
  272. //DEBUG ((DEBUG_INFO, "send cmd %d\n", MmcCmd & 0x3f));
  273. ErrMask = DWEMMC_INT_EBE | DWEMMC_INT_HLE | DWEMMC_INT_RTO |
  274. DWEMMC_INT_RCRC | DWEMMC_INT_RE;
  275. ErrMask |= DWEMMC_INT_DCRC | DWEMMC_INT_DRT | DWEMMC_INT_SBE;
  276. do {
  277. MicroSecondDelay(500);
  278. Data = MmioRead32 (DWEMMC_RINTSTS);
  279. if (Data & ErrMask) {
  280. return EFI_DEVICE_ERROR;
  281. }
  282. if (Data & DWEMMC_INT_DTO) { // Transfer Done
  283. break;
  284. }
  285. } while (!(Data & DWEMMC_INT_CMD_DONE));
  286. return EFI_SUCCESS;
  287. }
  288. EFI_STATUS
  289. DwEmmcSendCommand (
  290. IN EFI_MMC_HOST_PROTOCOL *This,
  291. IN MMC_CMD MmcCmd,
  292. IN UINT32 Argument
  293. )
  294. {
  295. UINT32 Cmd = 0;
  296. EFI_STATUS Status = EFI_SUCCESS;
  297. switch (MMC_GET_INDX(MmcCmd)) {
  298. case MMC_INDX(0):
  299. Cmd = BIT_CMD_SEND_INIT;
  300. break;
  301. case MMC_INDX(1):
  302. Cmd = BIT_CMD_RESPONSE_EXPECT;
  303. break;
  304. case MMC_INDX(2):
  305. Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_LONG_RESPONSE |
  306. BIT_CMD_CHECK_RESPONSE_CRC | BIT_CMD_SEND_INIT;
  307. break;
  308. case MMC_INDX(3):
  309. Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
  310. BIT_CMD_SEND_INIT;
  311. break;
  312. case MMC_INDX(7):
  313. if (Argument)
  314. Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
  315. else
  316. Cmd = 0;
  317. break;
  318. case MMC_INDX(8):
  319. if (Argument) /* sd */
  320. Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
  321. BIT_CMD_WAIT_PRVDATA_COMPLETE;
  322. else /* emmc */
  323. Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
  324. BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
  325. BIT_CMD_WAIT_PRVDATA_COMPLETE;
  326. break;
  327. case MMC_INDX(9):
  328. Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
  329. BIT_CMD_LONG_RESPONSE;
  330. break;
  331. case MMC_INDX(12):
  332. Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
  333. BIT_CMD_STOP_ABORT_CMD;
  334. break;
  335. case MMC_INDX(13):
  336. Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
  337. BIT_CMD_WAIT_PRVDATA_COMPLETE;
  338. break;
  339. case MMC_INDX(16):
  340. Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
  341. /* BIT_CMD_DATA_EXPECTED | BIT_CMD_READ | */
  342. BIT_CMD_WAIT_PRVDATA_COMPLETE;
  343. break;
  344. case MMC_INDX(6): /* sd */
  345. if (MmcCmd & (1 << 31))
  346. Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
  347. BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
  348. BIT_CMD_WAIT_PRVDATA_COMPLETE;
  349. else
  350. Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
  351. break;
  352. case MMC_INDX(17):
  353. case MMC_INDX(18):
  354. Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
  355. BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
  356. BIT_CMD_WAIT_PRVDATA_COMPLETE;
  357. break;
  358. case MMC_INDX(24):
  359. case MMC_INDX(25):
  360. Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
  361. BIT_CMD_DATA_EXPECTED | BIT_CMD_WRITE |
  362. BIT_CMD_WAIT_PRVDATA_COMPLETE;
  363. break;
  364. case MMC_INDX(30):
  365. Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
  366. BIT_CMD_DATA_EXPECTED;
  367. break;
  368. default:
  369. Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
  370. break;
  371. }
  372. if (app_cmd) {
  373. switch (MMC_GET_INDX(MmcCmd)) {
  374. case MMC_INDX(41):
  375. Cmd = BIT_CMD_RESPONSE_EXPECT;
  376. break;
  377. case MMC_INDX(51):
  378. Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC |
  379. BIT_CMD_DATA_EXPECTED | BIT_CMD_READ |
  380. BIT_CMD_WAIT_PRVDATA_COMPLETE;
  381. break;
  382. case MMC_INDX(6):
  383. Cmd = BIT_CMD_RESPONSE_EXPECT | BIT_CMD_CHECK_RESPONSE_CRC;
  384. break;
  385. default:
  386. break;
  387. }
  388. }
  389. Cmd |= MMC_GET_INDX(MmcCmd) | BIT_CMD_USE_HOLD_REG | BIT_CMD_START;
  390. if (IsPendingReadCommand (Cmd) || IsPendingWriteCommand (Cmd)) {
  391. mDwEmmcCommand = Cmd;
  392. mDwEmmcArgument = Argument;
  393. } else {
  394. Status = SendCommand (Cmd, Argument);
  395. }
  396. if ((Status == EFI_SUCCESS) && ((MmcCmd & 0x3f) == 55))
  397. app_cmd = 1;
  398. else
  399. app_cmd = 0;
  400. return Status;
  401. }
  402. EFI_STATUS
  403. DwEmmcReceiveResponse (
  404. IN EFI_MMC_HOST_PROTOCOL *This,
  405. IN MMC_RESPONSE_TYPE Type,
  406. IN UINT32* Buffer
  407. )
  408. {
  409. if (Buffer == NULL) {
  410. return EFI_INVALID_PARAMETER;
  411. }
  412. if ( (Type == MMC_RESPONSE_TYPE_R1)
  413. || (Type == MMC_RESPONSE_TYPE_R1b)
  414. || (Type == MMC_RESPONSE_TYPE_R3)
  415. || (Type == MMC_RESPONSE_TYPE_R6)
  416. || (Type == MMC_RESPONSE_TYPE_R7))
  417. {
  418. Buffer[0] = MmioRead32 (DWEMMC_RESP0);
  419. } else if (Type == MMC_RESPONSE_TYPE_R2) {
  420. Buffer[0] = MmioRead32 (DWEMMC_RESP0);
  421. Buffer[1] = MmioRead32 (DWEMMC_RESP1);
  422. Buffer[2] = MmioRead32 (DWEMMC_RESP2);
  423. Buffer[3] = MmioRead32 (DWEMMC_RESP3);
  424. }
  425. return EFI_SUCCESS;
  426. }
  427. VOID
  428. DwEmmcAdjustFifoThreshold (
  429. VOID
  430. )
  431. {
  432. /* DMA multiple transaction size map to reg value as array index */
  433. CONST UINT32 BurstSize[] = {1, 4, 8, 16, 32, 64, 128, 256};
  434. UINT32 BlkDepthInFifo, FifoThreshold, FifoWidth, FifoDepth;
  435. UINT32 BlkSize = DWEMMC_BLOCK_SIZE, Idx = 0, RxWatermark = 1, TxWatermark, TxWatermarkInvers;
  436. /* Skip FIFO adjustment if we do not have platform FIFO depth info */
  437. FifoDepth = PcdGet32 (PcdDwEmmcDxeFifoDepth);
  438. if (!FifoDepth) {
  439. return;
  440. }
  441. TxWatermark = FifoDepth / 2;
  442. TxWatermarkInvers = FifoDepth - TxWatermark;
  443. FifoWidth = DWEMMC_GET_HDATA_WIDTH (MmioRead32 (DWEMMC_HCON));
  444. if (!FifoWidth) {
  445. FifoWidth = 2;
  446. } else if (FifoWidth == 2) {
  447. FifoWidth = 8;
  448. } else {
  449. FifoWidth = 4;
  450. }
  451. BlkDepthInFifo = BlkSize / FifoWidth;
  452. Idx = ARRAY_SIZE (BurstSize) - 1;
  453. while (Idx && ((BlkDepthInFifo % BurstSize[Idx]) || (TxWatermarkInvers % BurstSize[Idx]))) {
  454. Idx--;
  455. }
  456. RxWatermark = BurstSize[Idx] - 1;
  457. FifoThreshold = DWEMMC_DMA_BURST_SIZE (Idx) | DWEMMC_FIFO_TWMARK (TxWatermark)
  458. | DWEMMC_FIFO_RWMARK (RxWatermark);
  459. MmioWrite32 (DWEMMC_FIFOTH, FifoThreshold);
  460. }
  461. EFI_STATUS
  462. PrepareDmaData (
  463. IN DWEMMC_IDMAC_DESCRIPTOR* IdmacDesc,
  464. IN UINTN Length,
  465. IN UINT32* Buffer
  466. )
  467. {
  468. UINTN Cnt, Blks, Idx, LastIdx;
  469. UINT32 Data/* , flag, cnt */;
  470. MmioWrite32 (DWEMMC_CTRL, DWEMMC_CTRL_FIFO_RESET);
  471. do {
  472. // Wait until reset operation finished
  473. Data = MmioRead32 (DWEMMC_CTRL);
  474. } while (Data & DWEMMC_CTRL_RESET_ALL);
  475. MmioWrite32 (DWEMMC_IDSTS, 0xffffffff);
  476. Cnt = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
  477. Blks = (Length + DWEMMC_BLOCK_SIZE - 1) / DWEMMC_BLOCK_SIZE;
  478. //Length = DWEMMC_BLOCK_SIZE * Blks;
  479. for (Idx = 0; Idx < Cnt; Idx++) {
  480. (IdmacDesc + Idx)->Des0 = DWEMMC_IDMAC_DES0_OWN | DWEMMC_IDMAC_DES0_CH |
  481. DWEMMC_IDMAC_DES0_DIC;
  482. (IdmacDesc + Idx)->Des1 = DWEMMC_IDMAC_DES1_BS1(DWEMMC_DMA_BUF_SIZE);
  483. /* Buffer Address */
  484. (IdmacDesc + Idx)->Des2 = (UINT32)((UINTN)Buffer + DWEMMC_DMA_BUF_SIZE * Idx);
  485. /* Next Descriptor Address */
  486. (IdmacDesc + Idx)->Des3 = (UINT32)((UINTN)IdmacDesc +
  487. (sizeof(DWEMMC_IDMAC_DESCRIPTOR) * (Idx + 1)));
  488. }
  489. /* First Descriptor */
  490. IdmacDesc->Des0 |= DWEMMC_IDMAC_DES0_FS;
  491. /* Last Descriptor */
  492. LastIdx = Cnt - 1;
  493. (IdmacDesc + LastIdx)->Des0 |= DWEMMC_IDMAC_DES0_LD;
  494. (IdmacDesc + LastIdx)->Des0 &= ~(DWEMMC_IDMAC_DES0_DIC | DWEMMC_IDMAC_DES0_CH);
  495. (IdmacDesc + LastIdx)->Des1 = DWEMMC_IDMAC_DES1_BS1(Length -
  496. (LastIdx * DWEMMC_DMA_BUF_SIZE));
  497. /* Set the Next field of Last Descriptor */
  498. //(IdmacDesc + LastIdx)->Des3 = 0;
  499. MmioWrite32 (DWEMMC_DBADDR, (UINT32)((UINTN)IdmacDesc));
  500. return EFI_SUCCESS;
  501. }
  502. VOID
  503. StartDma (
  504. UINTN Length
  505. )
  506. {
  507. UINT32 Data;
  508. Data = MmioRead32 (DWEMMC_CTRL);
  509. Data |= DWEMMC_CTRL_DMA_EN | DWEMMC_CTRL_IDMAC_EN;
  510. MmioWrite32 (DWEMMC_CTRL, Data);
  511. Data = MmioRead32 (DWEMMC_BMOD);
  512. Data |= DWEMMC_IDMAC_ENABLE | DWEMMC_IDMAC_FB;
  513. MmioWrite32 (DWEMMC_BMOD, Data);
  514. MmioWrite32 (DWEMMC_BLKSIZ,
  515. (Length < DWEMMC_BLOCK_SIZE) ? Length : DWEMMC_BLOCK_SIZE);
  516. MmioWrite32 (DWEMMC_BYTCNT, Length);
  517. }
  518. EFI_STATUS
  519. DwEmmcWaitDmaComplete (
  520. IN EFI_MMC_HOST_PROTOCOL *This,
  521. IN UINT32 read
  522. )
  523. {
  524. UINT32 mask, Ctrl, timeout = 100000;
  525. EFI_STATUS ret = EFI_SUCCESS;
  526. if (read)
  527. mask = DWMCI_IDINTEN_RI;
  528. else
  529. mask = DWMCI_IDINTEN_TI;
  530. do {
  531. Ctrl = MmioRead32 (DWEMMC_IDSTS);
  532. if (Ctrl & mask)
  533. break;
  534. timeout--;
  535. gBS->Stall(1);
  536. } while (timeout);
  537. if (!timeout) {
  538. DEBUG ((DEBUG_INFO, "wait dma to\n"));
  539. ret = EFI_DEVICE_ERROR;
  540. }
  541. MmioWrite32 (DWEMMC_IDSTS, DWMCI_IDINTEN_MASK);
  542. Ctrl = MmioRead32(DWEMMC_CTRL);
  543. Ctrl &= ~(DWMCI_DMA_EN);
  544. Ctrl = MmioWrite32(DWEMMC_CTRL, Ctrl);
  545. gBS->Stall(100);
  546. return ret;
  547. }
  548. EFI_STATUS
  549. DwEmmcReadBlockData (
  550. IN EFI_MMC_HOST_PROTOCOL *This,
  551. IN EFI_LBA Lba,
  552. IN UINTN Length,
  553. IN UINT32* Buffer
  554. )
  555. {
  556. EFI_STATUS Status;
  557. UINT32 DescPages, CountPerPage, Count;
  558. EFI_TPL Tpl;
  559. Tpl = gBS->RaiseTPL (TPL_NOTIFY);
  560. CountPerPage = EFI_PAGE_SIZE / 16;
  561. Count = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
  562. DescPages = (Count + CountPerPage - 1) / CountPerPage;
  563. InvalidateDataCacheRange (Buffer, Length);
  564. // DEBUG ((DEBUG_INFO, "BUFFER %lx length %x\n", (UINT64)Buffer, Length));
  565. Status = PrepareDmaData (gpIdmacDesc, Length, Buffer);
  566. if (EFI_ERROR (Status)) {
  567. goto out;
  568. }
  569. WriteBackDataCacheRange (gpIdmacDesc, DescPages * EFI_PAGE_SIZE);
  570. StartDma (Length);
  571. Status = SendCommand (mDwEmmcCommand, mDwEmmcArgument);
  572. if (EFI_ERROR (Status)) {
  573. DEBUG ((DEBUG_ERROR, "Failed to read data, mDwEmmcCommand:%x, mDwEmmcArgument:%x, Status:%r\n", mDwEmmcCommand, mDwEmmcArgument, Status));
  574. goto out;
  575. }
  576. Status = DwEmmcWaitDmaComplete(This, 1);
  577. out:
  578. // Restore Tpl
  579. gBS->RestoreTPL (Tpl);
  580. return Status;
  581. }
  582. EFI_STATUS
  583. DwEmmcWriteBlockData (
  584. IN EFI_MMC_HOST_PROTOCOL *This,
  585. IN EFI_LBA Lba,
  586. IN UINTN Length,
  587. IN UINT32* Buffer
  588. )
  589. {
  590. EFI_STATUS Status;
  591. UINT32 DescPages, CountPerPage, Count;
  592. EFI_TPL Tpl;
  593. Tpl = gBS->RaiseTPL (TPL_NOTIFY);
  594. CountPerPage = EFI_PAGE_SIZE / 16;
  595. Count = (Length + DWEMMC_DMA_BUF_SIZE - 1) / DWEMMC_DMA_BUF_SIZE;
  596. DescPages = (Count + CountPerPage - 1) / CountPerPage;
  597. WriteBackDataCacheRange (Buffer, Length);
  598. Status = PrepareDmaData (gpIdmacDesc, Length, Buffer);
  599. if (EFI_ERROR (Status)) {
  600. goto out;
  601. }
  602. WriteBackDataCacheRange (gpIdmacDesc, DescPages * EFI_PAGE_SIZE);
  603. StartDma (Length);
  604. Status = SendCommand (mDwEmmcCommand, mDwEmmcArgument);
  605. if (EFI_ERROR (Status)) {
  606. DEBUG ((DEBUG_ERROR, "Failed to write data, mDwEmmcCommand:%x, mDwEmmcArgument:%x, Status:%r\n", mDwEmmcCommand, mDwEmmcArgument, Status));
  607. goto out;
  608. }
  609. Status = DwEmmcWaitDmaComplete(This, 0);
  610. out:
  611. // Restore Tpl
  612. gBS->RestoreTPL (Tpl);
  613. return Status;
  614. }
  615. EFI_STATUS
  616. DwEmmcSetIos (
  617. IN EFI_MMC_HOST_PROTOCOL *This,
  618. IN UINT32 BusClockFreq,
  619. IN UINT32 BusWidth,
  620. IN UINT32 TimingMode
  621. )
  622. {
  623. EFI_STATUS Status = EFI_SUCCESS;
  624. UINT32 Data;
  625. if ((PcdGet32 (PcdDwEmmcDxeMaxClockFreqInHz) != 0) &&
  626. (BusClockFreq > PcdGet32 (PcdDwEmmcDxeMaxClockFreqInHz))) {
  627. return EFI_UNSUPPORTED;
  628. }
  629. if (TimingMode != EMMCBACKWARD) {
  630. Data = MmioRead32 (DWEMMC_UHSREG);
  631. switch (TimingMode) {
  632. case EMMCHS52DDR1V2:
  633. case EMMCHS52DDR1V8:
  634. Data |= 1 << 16;
  635. break;
  636. case EMMCHS52:
  637. case EMMCHS26:
  638. Data &= ~(1 << 16);
  639. break;
  640. default:
  641. return EFI_UNSUPPORTED;
  642. }
  643. MmioWrite32 (DWEMMC_UHSREG, Data);
  644. }
  645. DEBUG ((DEBUG_INFO, "Set bus width %d clock %d\n",BusWidth, BusClockFreq));
  646. switch (BusWidth) {
  647. case 1:
  648. MmioWrite32 (DWEMMC_CTYPE, 0);
  649. break;
  650. case 4:
  651. MmioWrite32 (DWEMMC_CTYPE, 1);
  652. break;
  653. case 8:
  654. MmioWrite32 (DWEMMC_CTYPE, 1 << 16);
  655. break;
  656. default:
  657. return EFI_UNSUPPORTED;
  658. }
  659. if (BusClockFreq) {
  660. Status = DwEmmcSetClock (BusClockFreq);
  661. }
  662. return Status;
  663. }
  664. BOOLEAN
  665. DwEmmcIsMultiBlock (
  666. IN EFI_MMC_HOST_PROTOCOL *This
  667. )
  668. {
  669. return TRUE;
  670. }
  671. EFI_MMC_HOST_PROTOCOL gMciHost = {
  672. MMC_HOST_PROTOCOL_REVISION,
  673. DwEmmcIsCardPresent,
  674. DwEmmcIsReadOnly,
  675. DwEmmcBuildDevicePath,
  676. DwEmmcNotifyState,
  677. DwEmmcSendCommand,
  678. DwEmmcReceiveResponse,
  679. DwEmmcReadBlockData,
  680. DwEmmcWriteBlockData,
  681. DwEmmcSetIos,
  682. DwEmmcIsMultiBlock
  683. };
  684. EFI_STATUS
  685. DwEmmcDxeInitialize (
  686. IN EFI_HANDLE ImageHandle,
  687. IN EFI_SYSTEM_TABLE *SystemTable
  688. )
  689. {
  690. EFI_STATUS Status;
  691. EFI_HANDLE Handle;
  692. if (!FixedPcdGetBool (PcdDwPermitObsoleteDrivers)) {
  693. ASSERT (FALSE);
  694. return EFI_UNSUPPORTED;
  695. }
  696. Handle = NULL;
  697. DwEmmcAdjustFifoThreshold ();
  698. gpIdmacDesc = (DWEMMC_IDMAC_DESCRIPTOR *)AllocatePages (DWEMMC_MAX_DESC_PAGES);
  699. if (gpIdmacDesc == NULL) {
  700. return EFI_BUFFER_TOO_SMALL;
  701. }
  702. DEBUG ((DEBUG_BLKIO, "DwEmmcDxeInitialize()\n"));
  703. //Publish Component Name, BlockIO protocol interfaces
  704. Status = gBS->InstallMultipleProtocolInterfaces (
  705. &Handle,
  706. &gEmbeddedMmcHostProtocolGuid, &gMciHost,
  707. NULL
  708. );
  709. ASSERT_EFI_ERROR (Status);
  710. return EFI_SUCCESS;
  711. }