Platform.c 34 KB

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  1. /** @file
  2. Copyright (c) 2004 - 2019, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. Module Name:
  5. Platform.c
  6. Abstract:
  7. Platform Initialization Driver.
  8. --*/
  9. #include "PlatformDxe.h"
  10. #include "Platform.h"
  11. #include "PchCommonDefinitions.h"
  12. #include <Protocol/PchPlatformPolicy.h>
  13. #include <Protocol/CpuIo2.h>
  14. #include <Library/S3BootScriptLib.h>
  15. #include <Guid/PciLanInfo.h>
  16. #include <Guid/ItkData.h>
  17. #include <Library/PciLib.h>
  18. #include <PlatformBootMode.h>
  19. #include <Guid/EventGroup.h>
  20. #include <Guid/Vlv2Variable.h>
  21. #include <Protocol/GlobalNvsArea.h>
  22. #include <Protocol/IgdOpRegion.h>
  23. #include <Library/PcdLib.h>
  24. #include <Protocol/VariableLock.h>
  25. //
  26. // VLV2 GPIO GROUP OFFSET
  27. //
  28. #define GPIO_SCORE_OFFSET 0x0000
  29. #define GPIO_NCORE_OFFSET 0x1000
  30. #define GPIO_SSUS_OFFSET 0x2000
  31. typedef struct {
  32. UINT32 offset;
  33. UINT32 val;
  34. } CFIO_PNP_INIT;
  35. GPIO_CONF_PAD_INIT mTB_BL_GpioInitData_SC_TRI_Exit_boot_Service[] =
  36. {
  37. // Pad Name GPIO Number Used As GPO Default Function# INT Capable Interrupt Type PULL H/L MMIO Offset
  38. GPIO_INIT_ITEM("LPC_CLKOUT0 GPIOC_47 " ,TRISTS ,NA ,F0 , , ,NONE ,0x47),
  39. GPIO_INIT_ITEM("LPC_CLKOUT1 GPIOC_48 " ,TRISTS ,NA ,F0 , , ,NONE ,0x41),
  40. };
  41. EFI_GUID mSystemHiiExportDatabase = EFI_HII_EXPORT_DATABASE_GUID;
  42. EFI_GUID mPlatformDriverGuid = EFI_PLATFORM_DRIVER_GUID;
  43. SYSTEM_CONFIGURATION mSystemConfiguration;
  44. EFI_HANDLE mImageHandle;
  45. BOOLEAN mMfgMode = FALSE;
  46. UINT32 mPlatformBootMode = PLATFORM_NORMAL_MODE;
  47. extern CHAR16 gItkDataVarName[];
  48. EFI_PLATFORM_INFO_HOB mPlatformInfo;
  49. EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;
  50. EFI_EVENT mReadyToBootEvent;
  51. UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;
  52. UINT8 mNumberSmbusAddress = sizeof( mSmbusRsvdAddresses ) / sizeof( mSmbusRsvdAddresses[0] );
  53. UINTN mPciLanCount = 0;
  54. VOID *mPciLanInfo = NULL;
  55. UINTN SpiBase;
  56. static EFI_SPEAKER_IF_PROTOCOL mSpeakerInterface = {
  57. ProgramToneFrequency,
  58. GenerateBeepTone
  59. };
  60. CFIO_PNP_INIT mTB_BL_GpioInitData_SC_TRI_S0ix_Exit_boot_Service[] =
  61. {
  62. {0x410 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pconf0
  63. {0x470 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pconf0
  64. {0x560 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pconf0
  65. {0x450 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pconf0
  66. {0x480 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pconf0
  67. {0x420 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pconf0
  68. {0x430 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pconf0
  69. {0x440 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pconf0
  70. {0x460 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pconf0
  71. {0x418 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pad_val
  72. {0x478 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pad_val
  73. {0x568 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pad_val
  74. {0x458 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pad_val
  75. {0x488 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pad_val
  76. {0x428 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pad_val
  77. {0x438 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pad_val
  78. {0x448 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pad_val
  79. {0x468 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pad_val
  80. };
  81. VOID
  82. EfiOrMem (
  83. IN VOID *Destination,
  84. IN VOID *Source,
  85. IN UINTN Length
  86. );
  87. #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
  88. STATIC
  89. VOID
  90. InitFirmwareId();
  91. #endif
  92. VOID
  93. InitializeClockRouting(
  94. );
  95. VOID
  96. InitializeSlotInfo (
  97. );
  98. #if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0
  99. VOID
  100. InitializeSensorInfoVariable (
  101. );
  102. #endif
  103. VOID
  104. InitTcoReset (
  105. );
  106. VOID
  107. InitExI ();
  108. VOID
  109. InitItk();
  110. VOID
  111. InitPlatformBootMode();
  112. VOID
  113. InitMfgAndConfigModeStateVar();
  114. VOID
  115. InitPchPlatformPolicy (
  116. IN EFI_PLATFORM_INFO_HOB *PlatformInfo
  117. );
  118. VOID
  119. InitVlvPlatformPolicy (
  120. );
  121. VOID
  122. PchInitBeforeBoot(
  123. );
  124. VOID
  125. UpdateDVMTSetup(
  126. );
  127. VOID
  128. InitRC6Policy(
  129. VOID
  130. );
  131. EFI_STATUS
  132. EFIAPI
  133. SaveSetupRecoveryVar(
  134. VOID
  135. )
  136. {
  137. EFI_STATUS Status = EFI_SUCCESS;
  138. UINTN SizeOfNvStore = 0;
  139. UINTN SizeOfSetupVar = 0;
  140. SYSTEM_CONFIGURATION *SetupData = NULL;
  141. SYSTEM_CONFIGURATION *RecoveryNvData = NULL;
  142. EDKII_VARIABLE_LOCK_PROTOCOL *VariableLock = NULL;
  143. DEBUG ((EFI_D_INFO, "SaveSetupRecoveryVar() Entry \n"));
  144. SizeOfNvStore = sizeof(SYSTEM_CONFIGURATION);
  145. RecoveryNvData = AllocateZeroPool (sizeof(SYSTEM_CONFIGURATION));
  146. if (NULL == RecoveryNvData) {
  147. Status = EFI_OUT_OF_RESOURCES;
  148. goto Exit;
  149. }
  150. Status = gRT->GetVariable(
  151. L"SetupRecovery",
  152. &gEfiNormalSetupGuid,
  153. NULL,
  154. &SizeOfNvStore,
  155. RecoveryNvData
  156. );
  157. if (EFI_ERROR (Status)) {
  158. // Don't find the "SetupRecovery" variable.
  159. // have to copy "Setup" variable to "SetupRecovery" variable.
  160. SetupData = AllocateZeroPool (sizeof(SYSTEM_CONFIGURATION));
  161. if (NULL == SetupData) {
  162. Status = EFI_OUT_OF_RESOURCES;
  163. goto Exit;
  164. }
  165. SizeOfSetupVar = sizeof(SYSTEM_CONFIGURATION);
  166. Status = gRT->GetVariable(
  167. NORMAL_SETUP_NAME,
  168. &gEfiNormalSetupGuid,
  169. NULL,
  170. &SizeOfSetupVar,
  171. SetupData
  172. );
  173. ASSERT_EFI_ERROR (Status);
  174. Status = gRT->SetVariable (
  175. L"SetupRecovery",
  176. &gEfiNormalSetupGuid,
  177. EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
  178. sizeof(SYSTEM_CONFIGURATION),
  179. SetupData
  180. );
  181. ASSERT_EFI_ERROR (Status);
  182. Status = gBS->LocateProtocol (&gEdkiiVariableLockProtocolGuid, NULL, (VOID **) &VariableLock);
  183. if (!EFI_ERROR (Status)) {
  184. Status = VariableLock->RequestToLock (VariableLock, L"SetupRecovery", &gEfiNormalSetupGuid);
  185. ASSERT_EFI_ERROR (Status);
  186. }
  187. }
  188. Exit:
  189. if (RecoveryNvData)
  190. FreePool (RecoveryNvData);
  191. if (SetupData)
  192. FreePool (SetupData);
  193. return Status;
  194. }
  195. VOID
  196. TristateLpcGpioConfig (
  197. IN UINT32 Gpio_Mmio_Offset,
  198. IN UINT32 Gpio_Pin_Num,
  199. GPIO_CONF_PAD_INIT* Gpio_Conf_Data
  200. )
  201. {
  202. UINT32 index;
  203. UINT32 mmio_conf0;
  204. UINT32 mmio_padval;
  205. PAD_CONF0 conf0_val;
  206. PAD_VAL pad_val;
  207. //
  208. // GPIO WELL -- Memory base registers
  209. //
  210. //
  211. // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
  212. // GPIO write 0x01001002 to IOBASE + Gpio_Mmio_Offset + 0x0900
  213. //
  214. for(index=0; index < Gpio_Pin_Num; index++)
  215. {
  216. //
  217. // Calculate the MMIO Address for specific GPIO pin CONF0 register pointed by index.
  218. //
  219. mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;
  220. mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL + Gpio_Conf_Data[index].offset * 16;
  221. #ifdef EFI_DEBUG
  222. DEBUG ((EFI_D_INFO, "%s, ", Gpio_Conf_Data[index].pad_name));
  223. #endif
  224. DEBUG ((EFI_D_INFO, "Usage = %d, Func# = %d, IntType = %d, Pull Up/Down = %d, MMIO Base = 0x%08x, ",
  225. Gpio_Conf_Data[index].usage,
  226. Gpio_Conf_Data[index].func,
  227. Gpio_Conf_Data[index].int_type,
  228. Gpio_Conf_Data[index].pull,
  229. mmio_conf0));
  230. //
  231. // Step 1: PadVal Programming
  232. //
  233. pad_val.dw = MmioRead32(mmio_padval);
  234. //
  235. // Config PAD_VAL only for GPIO (Non-Native) Pin
  236. //
  237. if(Native != Gpio_Conf_Data[index].usage)
  238. {
  239. pad_val.dw &= ~0x6; // Clear bits 1:2
  240. pad_val.dw |= (Gpio_Conf_Data[index].usage & 0x6); // Set bits 1:2 according to PadVal
  241. //
  242. // set GPO default value
  243. //
  244. if(Gpio_Conf_Data[index].usage == GPO && Gpio_Conf_Data[index].gpod4 != NA)
  245. {
  246. pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4;
  247. }
  248. }
  249. DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw));
  250. MmioWrite32(mmio_padval, pad_val.dw);
  251. //
  252. // Step 2: CONF0 Programming
  253. // Read GPIO default CONF0 value, which is assumed to be default value after reset.
  254. //
  255. conf0_val.dw = MmioRead32(mmio_conf0);
  256. //
  257. // Set Function #
  258. //
  259. conf0_val.r.Func_Pin_Mux = Gpio_Conf_Data[index].func;
  260. if(GPO == Gpio_Conf_Data[index].usage)
  261. {
  262. //
  263. // If used as GPO, then internal pull need to be disabled
  264. //
  265. conf0_val.r.Pull_assign = 0; // Non-pull
  266. }
  267. else
  268. {
  269. //
  270. // Set PullUp / PullDown
  271. //
  272. if(P_20K_H == Gpio_Conf_Data[index].pull)
  273. {
  274. conf0_val.r.Pull_assign = 0x1; // PullUp
  275. conf0_val.r.Pull_strength = 0x2;// 20K
  276. }
  277. else if(P_20K_L == Gpio_Conf_Data[index].pull)
  278. {
  279. conf0_val.r.Pull_assign = 0x2; // PullDown
  280. conf0_val.r.Pull_strength = 0x2;// 20K
  281. }
  282. else if(P_NONE == Gpio_Conf_Data[index].pull)
  283. {
  284. conf0_val.r.Pull_assign = 0; // Non-pull
  285. }
  286. else
  287. {
  288. ASSERT(FALSE); // Invalid value
  289. }
  290. }
  291. //
  292. // Set INT Trigger Type
  293. //
  294. conf0_val.dw &= ~0x0f000000; // Clear bits 27:24
  295. //
  296. // Set INT Trigger Type
  297. //
  298. if(TRIG_ == Gpio_Conf_Data[index].int_type)
  299. {
  300. //
  301. // Interrupt not capable, clear bits 27:24
  302. //
  303. }
  304. else
  305. {
  306. conf0_val.dw |= (Gpio_Conf_Data[index].int_type & 0x0f)<<24;
  307. }
  308. DEBUG ((EFI_D_INFO, "Set CONF0 = 0x%08x\n", conf0_val.dw));
  309. //
  310. // Write back the targeted GPIO config value according to platform (board) GPIO setting
  311. //
  312. MmioWrite32 (mmio_conf0, conf0_val.dw);
  313. }
  314. // A0 BIOS Spec doesn't mention it although X0 does. comment out now.
  315. // GPIO SCORE write 0x01001002 to IOBASE + 0x0900
  316. //
  317. }
  318. VOID
  319. EFIAPI
  320. SpiBiosProtectionFunction(
  321. EFI_EVENT Event,
  322. VOID *Context
  323. )
  324. {
  325. UINTN mPciD31F0RegBase;
  326. UINTN BiosFlaLower0;
  327. UINTN BiosFlaLimit0;
  328. UINTN BiosFlaLower1;
  329. UINTN BiosFlaLimit1;
  330. BiosFlaLower0 = PcdGet32(PcdFlashMicroCodeAddress)-PcdGet32(PcdFlashAreaBaseAddress);
  331. BiosFlaLimit0 = PcdGet32(PcdFlashMicroCodeSize)-1;
  332. BiosFlaLower1 = PcdGet32(PcdFlashFvMainBase)-PcdGet32(PcdFlashAreaBaseAddress);
  333. BiosFlaLimit1 = (PcdGet32(PcdFlashFvRecoveryBase)-PcdGet32(PcdFlashFvMainBase)+PcdGet32(PcdFlashFvRecoverySize))-1;
  334. mPciD31F0RegBase = MmPciAddress (0,
  335. DEFAULT_PCI_BUS_NUMBER_PCH,
  336. PCI_DEVICE_NUMBER_PCH_LPC,
  337. PCI_FUNCTION_NUMBER_PCH_LPC,
  338. 0
  339. );
  340. SpiBase = MmioRead32(mPciD31F0RegBase + R_PCH_LPC_SPI_BASE) & B_PCH_LPC_SPI_BASE_BAR;
  341. //
  342. //Set SMM_BWP, WPD and LE bit
  343. //
  344. MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_SMM_BWP);
  345. MmioAnd32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8)(~B_PCH_SPI_BCR_BIOSWE));
  346. MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_BLE);
  347. //
  348. //First check if FLOCKDN or PR0FLOCKDN is set. No action if either of them set already.
  349. //
  350. if( (MmioRead16(SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) != 0 ||
  351. (MmioRead32(SpiBase + R_PCH_SPI_IND_LOCK)& B_PCH_SPI_IND_LOCK_PR0) != 0) {
  352. //
  353. //Already locked. we could take no action here
  354. //
  355. DEBUG((EFI_D_INFO, "PR0 already locked down. Stop configuring PR0.\n"));
  356. return;
  357. }
  358. //
  359. //Set PR0
  360. //
  361. MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR0),
  362. B_PCH_SPI_PR0_RPE|B_PCH_SPI_PR0_WPE|\
  363. (B_PCH_SPI_PR0_PRB_MASK&(BiosFlaLower0>>12))|(B_PCH_SPI_PR0_PRL_MASK&(BiosFlaLimit0>>12)<<16));
  364. //
  365. //Set PR1
  366. //
  367. MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR1),
  368. B_PCH_SPI_PR1_RPE|B_PCH_SPI_PR1_WPE|\
  369. (B_PCH_SPI_PR1_PRB_MASK&(BiosFlaLower1>>12))|(B_PCH_SPI_PR1_PRL_MASK&(BiosFlaLimit1>>12)<<16));
  370. //
  371. //Lock down PRx
  372. //
  373. MmioOr16 ((UINTN) (SpiBase + R_PCH_SPI_HSFS), (UINT16) (B_PCH_SPI_HSFS_FLOCKDN));
  374. //
  375. // Verify if it's really locked.
  376. //
  377. if ((MmioRead16 (SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) == 0) {
  378. DEBUG((EFI_D_ERROR, "Failed to lock down PRx.\n"));
  379. }
  380. return;
  381. }
  382. VOID
  383. EFIAPI
  384. InitPciDevPME (
  385. EFI_EVENT Event,
  386. VOID *Context
  387. )
  388. {
  389. UINTN VarSize;
  390. VarSize = sizeof(SYSTEM_CONFIGURATION);
  391. gRT->GetVariable(
  392. NORMAL_SETUP_NAME,
  393. &gEfiNormalSetupGuid,
  394. NULL,
  395. &VarSize,
  396. &mSystemConfiguration
  397. );
  398. //
  399. //Program HDA PME_EN
  400. //
  401. PchAzaliaPciCfg32Or (R_PCH_HDA_PCS, B_PCH_HDA_PCS_PMEE);
  402. //
  403. //Program SATA PME_EN
  404. //
  405. PchSataPciCfg32Or (R_PCH_SATA_PMCS, B_PCH_SATA_PMCS_PMEE);
  406. DEBUG ((EFI_D_INFO, "InitPciDevPME mSystemConfiguration.EhciPllCfgEnable = 0x%x \n",mSystemConfiguration.EhciPllCfgEnable));
  407. if (mSystemConfiguration.EhciPllCfgEnable != 1) {
  408. //
  409. //Program EHCI PME_EN
  410. //
  411. PchMmPci32Or (
  412. 0,
  413. 0,
  414. PCI_DEVICE_NUMBER_PCH_USB,
  415. PCI_FUNCTION_NUMBER_PCH_EHCI,
  416. R_PCH_EHCI_PWR_CNTL_STS,
  417. B_PCH_EHCI_PWR_CNTL_STS_PME_EN
  418. );
  419. }
  420. {
  421. UINTN EhciPciMmBase;
  422. UINT32 Buffer32 = 0;
  423. EhciPciMmBase = MmPciAddress (0,
  424. 0,
  425. PCI_DEVICE_NUMBER_PCH_USB,
  426. PCI_FUNCTION_NUMBER_PCH_EHCI,
  427. 0
  428. );
  429. DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() EhciPciMmBase = 0x%x \n",EhciPciMmBase));
  430. Buffer32 = MmioRead32(EhciPciMmBase + R_PCH_EHCI_PWR_CNTL_STS);
  431. DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() R_PCH_EHCI_PWR_CNTL_STS = 0x%x \n",Buffer32));
  432. }
  433. }
  434. VOID
  435. EFIAPI
  436. InitThermalZone (
  437. EFI_EVENT Event,
  438. VOID *Context
  439. )
  440. {
  441. UINTN VarSize;
  442. EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;
  443. VarSize = sizeof(SYSTEM_CONFIGURATION);
  444. gRT->GetVariable(
  445. NORMAL_SETUP_NAME,
  446. &gEfiNormalSetupGuid,
  447. NULL,
  448. &VarSize,
  449. &mSystemConfiguration
  450. );
  451. gBS->LocateProtocol (
  452. &gEfiGlobalNvsAreaProtocolGuid,
  453. NULL,
  454. (void **)&GlobalNvsArea
  455. );
  456. GlobalNvsArea->Area->CriticalThermalTripPoint = mSystemConfiguration.CriticalThermalTripPoint;
  457. GlobalNvsArea->Area->PassiveThermalTripPoint = mSystemConfiguration.PassiveThermalTripPoint;
  458. }
  459. #if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY
  460. #endif
  461. EFI_STATUS
  462. EFIAPI
  463. TristateLpcGpioS0i3Config (
  464. UINT32 Gpio_Mmio_Offset,
  465. UINT32 Gpio_Pin_Num,
  466. CFIO_PNP_INIT* Gpio_Conf_Data
  467. )
  468. {
  469. UINT32 index;
  470. UINT32 mmio_reg;
  471. UINT32 mmio_val;
  472. DEBUG ((DEBUG_INFO, "TristateLpcGpioS0i3Config\n"));
  473. for(index=0; index < Gpio_Pin_Num; index++)
  474. {
  475. mmio_reg = IO_BASE_ADDRESS + Gpio_Mmio_Offset + Gpio_Conf_Data[index].offset;
  476. MmioWrite32(mmio_reg, Gpio_Conf_Data[index].val);
  477. mmio_val = 0;
  478. mmio_val = MmioRead32(mmio_reg);
  479. DEBUG ((EFI_D_INFO, "Set MMIO=0x%08x PAD_VAL = 0x%08x,\n", mmio_reg, mmio_val));
  480. }
  481. return EFI_SUCCESS;
  482. }
  483. /**
  484. Event Notification during exit boot service to enabel ACPI mode
  485. Disable SW SMI Timer, SMI from USB & Intel Specific USB 2
  486. Clear all ACPI event status and disable all ACPI events
  487. Disable PM sources except power button
  488. Clear status bits
  489. Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")
  490. Update EC to disable SMI and enable SCI
  491. Enable SCI
  492. Enable PME_B0_EN in GPE0a_EN
  493. @param Event - EFI Event Handle
  494. @param Context - Pointer to Notify Context
  495. @retval Nothing
  496. **/
  497. VOID
  498. EFIAPI
  499. EnableAcpiCallback (
  500. IN EFI_EVENT Event,
  501. IN VOID *Context
  502. )
  503. {
  504. UINT32 RegData32;
  505. UINT16 Pm1Cnt;
  506. UINT16 AcpiBase;
  507. UINT32 Gpe0aEn;
  508. AcpiBase = MmioRead16 (
  509. PchPciDeviceMmBase (DEFAULT_PCI_BUS_NUMBER_PCH,
  510. PCI_DEVICE_NUMBER_PCH_LPC,
  511. PCI_FUNCTION_NUMBER_PCH_LPC) + R_PCH_LPC_ACPI_BASE
  512. ) & B_PCH_LPC_ACPI_BASE_BAR;
  513. DEBUG ((EFI_D_INFO, "EnableAcpiCallback: AcpiBase = %x\n", AcpiBase));
  514. //
  515. // Disable SW SMI Timer, SMI from USB & Intel Specific USB 2
  516. //
  517. RegData32 = IoRead32(AcpiBase + R_PCH_SMI_EN);
  518. RegData32 &= ~(B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_INTEL_USB2);
  519. IoWrite32(AcpiBase + R_PCH_SMI_EN, RegData32);
  520. RegData32 = IoRead32(AcpiBase + R_PCH_SMI_STS);
  521. RegData32 |= B_PCH_SMI_STS_SWSMI_TMR;
  522. IoWrite32(AcpiBase + R_PCH_SMI_STS, RegData32);
  523. //
  524. // Disable PM sources except power button
  525. // power button is enabled only for PCAT. Disabled it on Tablet platform
  526. //
  527. IoWrite16(AcpiBase + R_PCH_ACPI_PM1_EN, B_PCH_ACPI_PM1_EN_PWRBTN);
  528. IoWrite16(AcpiBase + R_PCH_ACPI_PM1_STS, 0xffff);
  529. //
  530. // Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")
  531. // Clear Status D reg VM bit, Date of month Alarm to make Data in CMOS RAM is no longer Valid
  532. //
  533. IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_D);
  534. IoWrite8 (PCAT_RTC_DATA_REGISTER, 0x0);
  535. RegData32 = IoRead32(AcpiBase + R_PCH_ALT_GP_SMI_EN);
  536. RegData32 &= ~(BIT7);
  537. IoWrite32((AcpiBase + R_PCH_ALT_GP_SMI_EN), RegData32);
  538. //
  539. // Enable SCI
  540. //
  541. Pm1Cnt = IoRead16(AcpiBase + R_PCH_ACPI_PM1_CNT);
  542. Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN;
  543. IoWrite16(AcpiBase + R_PCH_ACPI_PM1_CNT, Pm1Cnt);
  544. IoWrite8(0x80, 0xA0); //SW_SMI_ACPI_ENABLE
  545. //
  546. // Enable PME_B0_EN in GPE0a_EN
  547. // Caution: Enable PME_B0_EN must be placed after enabling SCI.
  548. // Otherwise, USB PME could not be handled as SMI event since no handler is there.
  549. //
  550. Gpe0aEn = IoRead32 (AcpiBase + R_PCH_ACPI_GPE0a_EN);
  551. Gpe0aEn |= B_PCH_ACPI_GPE0a_EN_PME_B0;
  552. IoWrite32(AcpiBase + R_PCH_ACPI_GPE0a_EN, Gpe0aEn);
  553. }
  554. /**
  555. Routine Description:
  556. This is the standard EFI driver point for the Driver. This
  557. driver is responsible for setting up any platform specific policy or
  558. initialization information.
  559. @param ImageHandle Handle for the image of this driver.
  560. @param SystemTable Pointer to the EFI System Table.
  561. @retval EFI_SUCCESS Policy decisions set.
  562. **/
  563. EFI_STATUS
  564. EFIAPI
  565. InitializePlatform (
  566. IN EFI_HANDLE ImageHandle,
  567. IN EFI_SYSTEM_TABLE *SystemTable
  568. )
  569. {
  570. EFI_STATUS Status;
  571. UINTN VarSize;
  572. EFI_HANDLE Handle = NULL;
  573. EFI_EVENT mEfiExitBootServicesEvent;
  574. EFI_EVENT RtcEvent;
  575. VOID *RtcCallbackReg = NULL;
  576. mImageHandle = ImageHandle;
  577. Status = gBS->InstallProtocolInterface (
  578. &Handle,
  579. &gEfiSpeakerInterfaceProtocolGuid,
  580. EFI_NATIVE_INTERFACE,
  581. &mSpeakerInterface
  582. );
  583. Status = gBS->LocateProtocol (
  584. &gEfiPciRootBridgeIoProtocolGuid,
  585. NULL,
  586. (VOID **) &mPciRootBridgeIo
  587. );
  588. ASSERT_EFI_ERROR (Status);
  589. VarSize = sizeof(EFI_PLATFORM_INFO_HOB);
  590. Status = gRT->GetVariable(
  591. L"PlatformInfo",
  592. &gEfiVlv2VariableGuid,
  593. NULL,
  594. &VarSize,
  595. &mPlatformInfo
  596. );
  597. //
  598. // Initialize Product Board ID variable
  599. //
  600. InitMfgAndConfigModeStateVar();
  601. InitPlatformBootMode();
  602. //
  603. // Install Observable protocol
  604. //
  605. InitializeObservableProtocol();
  606. Status = SaveSetupRecoveryVar();
  607. if (EFI_ERROR (Status)) {
  608. DEBUG ((EFI_D_ERROR, "InitializePlatform() Save SetupRecovery variable failed \n"));
  609. }
  610. VarSize = sizeof(SYSTEM_CONFIGURATION);
  611. Status = gRT->GetVariable(
  612. NORMAL_SETUP_NAME,
  613. &gEfiNormalSetupGuid,
  614. NULL,
  615. &VarSize,
  616. &mSystemConfiguration
  617. );
  618. if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
  619. //The setup variable is corrupted
  620. VarSize = sizeof(SYSTEM_CONFIGURATION);
  621. Status = gRT->GetVariable(
  622. L"SetupRecovery",
  623. &gEfiNormalSetupGuid,
  624. NULL,
  625. &VarSize,
  626. &mSystemConfiguration
  627. );
  628. ASSERT_EFI_ERROR (Status);
  629. Status = gRT->SetVariable (
  630. NORMAL_SETUP_NAME,
  631. &gEfiNormalSetupGuid,
  632. EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
  633. sizeof(SYSTEM_CONFIGURATION),
  634. &mSystemConfiguration
  635. );
  636. }
  637. Status = EfiCreateEventReadyToBootEx (
  638. TPL_CALLBACK,
  639. ReadyToBootFunction,
  640. NULL,
  641. &mReadyToBootEvent
  642. );
  643. //
  644. // Create a ReadyToBoot Event to run the PME init process
  645. //
  646. Status = EfiCreateEventReadyToBootEx (
  647. TPL_CALLBACK,
  648. InitPciDevPME,
  649. NULL,
  650. &mReadyToBootEvent
  651. );
  652. //
  653. // Create a ReadyToBoot Event to run enable PR0/PR1 and lock down,unlock variable region
  654. //
  655. if(mSystemConfiguration.SpiRwProtect==1) {
  656. Status = EfiCreateEventReadyToBootEx (
  657. TPL_CALLBACK,
  658. SpiBiosProtectionFunction,
  659. NULL,
  660. &mReadyToBootEvent
  661. );
  662. }
  663. //
  664. // Create a ReadyToBoot Event to run the thermalzone init process
  665. //
  666. Status = EfiCreateEventReadyToBootEx (
  667. TPL_CALLBACK,
  668. InitThermalZone,
  669. NULL,
  670. &mReadyToBootEvent
  671. );
  672. ReportStatusCodeEx (
  673. EFI_PROGRESS_CODE,
  674. EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP1,
  675. 0,
  676. &gEfiCallerIdGuid,
  677. NULL,
  678. NULL,
  679. 0
  680. );
  681. #if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0
  682. //
  683. // Initialize Sensor Info variable
  684. //
  685. InitializeSensorInfoVariable();
  686. #endif
  687. InitPchPlatformPolicy(&mPlatformInfo);
  688. InitVlvPlatformPolicy();
  689. //
  690. // Add usb policy
  691. //
  692. InitializeClockRouting();
  693. InitializeSlotInfo();
  694. InitTcoReset();
  695. //
  696. //Init ExI
  697. //
  698. InitExI();
  699. ReportStatusCodeEx (
  700. EFI_PROGRESS_CODE,
  701. EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP2,
  702. 0,
  703. &gEfiCallerIdGuid,
  704. NULL,
  705. NULL,
  706. 0
  707. );
  708. //
  709. // Install PCI Bus Driver Hook
  710. //
  711. PciBusDriverHook();
  712. InitItk();
  713. ReportStatusCodeEx (
  714. EFI_PROGRESS_CODE,
  715. EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP3,
  716. 0,
  717. &gEfiCallerIdGuid,
  718. NULL,
  719. NULL,
  720. 0
  721. );
  722. //
  723. // Initialize Password States and Callbacks
  724. //
  725. PchInitBeforeBoot();
  726. #if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY
  727. #endif
  728. #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
  729. //
  730. // Re-write Firmware ID if it is changed
  731. //
  732. InitFirmwareId();
  733. #endif
  734. ReportStatusCodeEx (
  735. EFI_PROGRESS_CODE,
  736. EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP4,
  737. 0,
  738. &gEfiCallerIdGuid,
  739. NULL,
  740. NULL,
  741. 0
  742. );
  743. Status = gBS->CreateEventEx (
  744. EVT_NOTIFY_SIGNAL,
  745. TPL_NOTIFY,
  746. EnableAcpiCallback,
  747. NULL,
  748. &gEfiEventExitBootServicesGuid,
  749. &mEfiExitBootServicesEvent
  750. );
  751. //
  752. // Adjust RTC deafult time to be BIOS-built time.
  753. //
  754. Status = gBS->CreateEvent (
  755. EVT_NOTIFY_SIGNAL,
  756. TPL_CALLBACK,
  757. AdjustDefaultRtcTimeCallback,
  758. NULL,
  759. &RtcEvent
  760. );
  761. if (!EFI_ERROR (Status)) {
  762. Status = gBS->RegisterProtocolNotify (
  763. &gEfiEndOfDxeEventGroupGuid,
  764. RtcEvent,
  765. &RtcCallbackReg
  766. );
  767. }
  768. return EFI_SUCCESS;
  769. }
  770. /**
  771. Source Or Destination with Length bytes.
  772. @param[in] Destination Target memory
  773. @param[in] Source Source memory
  774. @param[in] Length Number of bytes
  775. @retval None
  776. **/
  777. VOID
  778. EfiOrMem (
  779. IN VOID *Destination,
  780. IN VOID *Source,
  781. IN UINTN Length
  782. )
  783. {
  784. CHAR8 *Destination8;
  785. CHAR8 *Source8;
  786. if (Source < Destination) {
  787. Destination8 = (CHAR8 *) Destination + Length - 1;
  788. Source8 = (CHAR8 *) Source + Length - 1;
  789. while (Length--) {
  790. *(Destination8--) |= *(Source8--);
  791. }
  792. } else {
  793. Destination8 = (CHAR8 *) Destination;
  794. Source8 = (CHAR8 *) Source;
  795. while (Length--) {
  796. *(Destination8++) |= *(Source8++);
  797. }
  798. }
  799. }
  800. VOID
  801. PchInitBeforeBoot()
  802. {
  803. //
  804. // Saved SPI Opcode menu to fix EFI variable unable to write after S3 resume.
  805. //
  806. S3BootScriptSaveMemWrite (
  807. EfiBootScriptWidthUint32,
  808. (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)),
  809. 1,
  810. (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)));
  811. S3BootScriptSaveMemWrite (
  812. EfiBootScriptWidthUint32,
  813. (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)),
  814. 1,
  815. (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)));
  816. S3BootScriptSaveMemWrite (
  817. EfiBootScriptWidthUint16,
  818. (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE),
  819. 1,
  820. (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE));
  821. S3BootScriptSaveMemWrite (
  822. EfiBootScriptWidthUint16,
  823. (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP),
  824. 1,
  825. (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP));
  826. //
  827. // Saved MTPMC_1 for S3 resume.
  828. //
  829. S3BootScriptSaveMemWrite (
  830. EfiBootScriptWidthUint32,
  831. (UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1),
  832. 1,
  833. (VOID *)(UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1));
  834. return;
  835. }
  836. VOID
  837. EFIAPI
  838. ReadyToBootFunction (
  839. EFI_EVENT Event,
  840. VOID *Context
  841. )
  842. {
  843. //
  844. // save LAN info to a variable
  845. //
  846. if (NULL != mPciLanInfo) {
  847. gRT->SetVariable (
  848. L"PciLanInfo",
  849. &gEfiPciLanInfoGuid,
  850. EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,
  851. mPciLanCount * sizeof(PCI_LAN_INFO),
  852. mPciLanInfo
  853. );
  854. }
  855. if (NULL != mPciLanInfo) {
  856. gBS->FreePool (mPciLanInfo);
  857. mPciLanInfo = NULL;
  858. }
  859. }
  860. /**
  861. Initializes manufacturing and config mode setting.
  862. **/
  863. VOID
  864. InitMfgAndConfigModeStateVar()
  865. {
  866. EFI_PLATFORM_SETUP_ID *BootModeBuffer;
  867. VOID *HobList;
  868. HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);
  869. if (HobList != NULL) {
  870. BootModeBuffer = GET_GUID_HOB_DATA (HobList);
  871. //
  872. // Check if in Manufacturing mode
  873. //
  874. if ( !CompareMem (
  875. &BootModeBuffer->SetupName,
  876. MANUFACTURE_SETUP_NAME,
  877. StrSize (MANUFACTURE_SETUP_NAME)
  878. ) ) {
  879. mMfgMode = TRUE;
  880. }
  881. }
  882. }
  883. /**
  884. Initializes manufacturing and config mode setting.
  885. **/
  886. VOID
  887. InitPlatformBootMode()
  888. {
  889. EFI_PLATFORM_SETUP_ID *BootModeBuffer;
  890. VOID *HobList;
  891. HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);
  892. if (HobList != NULL) {
  893. BootModeBuffer = GET_GUID_HOB_DATA (HobList);
  894. mPlatformBootMode = BootModeBuffer->PlatformBootMode;
  895. }
  896. }
  897. /**
  898. Initializes ITK.
  899. **/
  900. VOID
  901. InitItk(
  902. )
  903. {
  904. EFI_STATUS Status;
  905. UINT16 ItkModBiosState;
  906. UINT8 Value;
  907. UINTN DataSize;
  908. UINT32 Attributes;
  909. //
  910. // Setup local variable according to ITK variable
  911. //
  912. //
  913. // Read ItkBiosModVar to determine if BIOS has been modified by ITK
  914. // If ItkBiosModVar = 0 or if variable hasn't been initialized then BIOS has not been modified by ITK modified
  915. // Set local variable VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME=0 if BIOS has not been modified by ITK
  916. //
  917. DataSize = sizeof (Value);
  918. Status = gRT->GetVariable (
  919. ITK_BIOS_MOD_VAR_NAME,
  920. &gItkDataVarGuid,
  921. &Attributes,
  922. &DataSize,
  923. &Value
  924. );
  925. if (Status == EFI_NOT_FOUND) {
  926. //
  927. // Variable not found, hasn't been initialized, intialize to 0
  928. //
  929. Value=0x00;
  930. //
  931. // Write variable to flash.
  932. //
  933. gRT->SetVariable (
  934. ITK_BIOS_MOD_VAR_NAME,
  935. &gItkDataVarGuid,
  936. EFI_VARIABLE_RUNTIME_ACCESS |
  937. EFI_VARIABLE_NON_VOLATILE |
  938. EFI_VARIABLE_BOOTSERVICE_ACCESS,
  939. sizeof (Value),
  940. &Value
  941. );
  942. }
  943. if ( (!EFI_ERROR (Status)) || (Status == EFI_NOT_FOUND) ) {
  944. if (Value == 0x00) {
  945. ItkModBiosState = 0x00;
  946. } else {
  947. ItkModBiosState = 0x01;
  948. }
  949. gRT->SetVariable (
  950. VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME,
  951. &gEfiNormalSetupGuid,
  952. EFI_VARIABLE_BOOTSERVICE_ACCESS,
  953. 2,
  954. (void *)&ItkModBiosState
  955. );
  956. }
  957. }
  958. #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)
  959. /**
  960. Initializes the BIOS FIRMWARE ID from the FIRMWARE_ID build variable.
  961. **/
  962. STATIC
  963. VOID
  964. InitFirmwareId(
  965. )
  966. {
  967. EFI_STATUS Status;
  968. CHAR16 FirmwareIdNameWithPassword[] = FIRMWARE_ID_NAME_WITH_PASSWORD;
  969. //
  970. // First try writing the variable without a password in case we are
  971. // upgrading from a BIOS without password protection on the FirmwareId
  972. //
  973. Status = gRT->SetVariable(
  974. (CHAR16 *)&gFirmwareIdName,
  975. &gFirmwareIdGuid,
  976. EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |
  977. EFI_VARIABLE_RUNTIME_ACCESS,
  978. sizeof( FIRMWARE_ID ) - 1,
  979. FIRMWARE_ID
  980. );
  981. if (Status == EFI_INVALID_PARAMETER) {
  982. //
  983. // Since setting the firmware id without the password failed,
  984. // a password must be required.
  985. //
  986. Status = gRT->SetVariable(
  987. (CHAR16 *)&FirmwareIdNameWithPassword,
  988. &gFirmwareIdGuid,
  989. EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |
  990. EFI_VARIABLE_RUNTIME_ACCESS,
  991. sizeof( FIRMWARE_ID ) - 1,
  992. FIRMWARE_ID
  993. );
  994. }
  995. }
  996. #endif
  997. VOID
  998. UpdateDVMTSetup(
  999. )
  1000. {
  1001. //
  1002. // Workaround to support IIA bug.
  1003. // IIA request to change option value to 4, 5 and 7 relatively
  1004. // instead of 1, 2, and 3 which follow Lakeport Specs.
  1005. // Check option value, temporary hardcode GraphicsDriverMemorySize
  1006. // Option value to fulfill IIA requirment. So that user no need to
  1007. // load default and update setupvariable after update BIOS.
  1008. // Option value hardcoded as: 1 to 4, 2 to 5, 3 to 7.
  1009. // *This is for broadwater and above product only.
  1010. //
  1011. SYSTEM_CONFIGURATION SystemConfiguration;
  1012. UINTN VarSize;
  1013. EFI_STATUS Status;
  1014. VarSize = sizeof(SYSTEM_CONFIGURATION);
  1015. Status = gRT->GetVariable(
  1016. NORMAL_SETUP_NAME,
  1017. &gEfiNormalSetupGuid,
  1018. NULL,
  1019. &VarSize,
  1020. &SystemConfiguration
  1021. );
  1022. if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {
  1023. //The setup variable is corrupted
  1024. VarSize = sizeof(SYSTEM_CONFIGURATION);
  1025. Status = gRT->GetVariable(
  1026. L"SetupRecovery",
  1027. &gEfiNormalSetupGuid,
  1028. NULL,
  1029. &VarSize,
  1030. &SystemConfiguration
  1031. );
  1032. ASSERT_EFI_ERROR (Status);
  1033. }
  1034. if((SystemConfiguration.GraphicsDriverMemorySize < 4) && !EFI_ERROR(Status) ) {
  1035. switch (SystemConfiguration.GraphicsDriverMemorySize){
  1036. case 1:
  1037. SystemConfiguration.GraphicsDriverMemorySize = 4;
  1038. break;
  1039. case 2:
  1040. SystemConfiguration.GraphicsDriverMemorySize = 5;
  1041. break;
  1042. case 3:
  1043. SystemConfiguration.GraphicsDriverMemorySize = 7;
  1044. break;
  1045. default:
  1046. break;
  1047. }
  1048. Status = gRT->SetVariable (
  1049. NORMAL_SETUP_NAME,
  1050. &gEfiNormalSetupGuid,
  1051. EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
  1052. sizeof(SYSTEM_CONFIGURATION),
  1053. &SystemConfiguration
  1054. );
  1055. }
  1056. }
  1057. UINT8
  1058. ReadCmosBank1Byte (
  1059. IN EFI_CPU_IO_PROTOCOL *CpuIo,
  1060. IN UINT8 Index
  1061. )
  1062. {
  1063. UINT8 Data;
  1064. CpuIo->Io.Write (CpuIo, EfiCpuIoWidthUint8, 0x72, 1, &Index);
  1065. CpuIo->Io.Read (CpuIo, EfiCpuIoWidthUint8, 0x73, 1, &Data);
  1066. return Data;
  1067. }
  1068. VOID
  1069. WriteCmosBank1Byte (
  1070. IN EFI_CPU_IO_PROTOCOL *CpuIo,
  1071. IN UINT8 Index,
  1072. IN UINT8 Data
  1073. )
  1074. {
  1075. CpuIo->Io.Write (
  1076. CpuIo,
  1077. EfiCpuIoWidthUint8,
  1078. 0x72,
  1079. 1,
  1080. &Index
  1081. );
  1082. CpuIo->Io.Write (
  1083. CpuIo,
  1084. EfiCpuIoWidthUint8,
  1085. 0x73,
  1086. 1,
  1087. &Data
  1088. );
  1089. }