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- /** @file
- Copyright (c) 2023, Ampere Computing LLC. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
- **/
- // PCI0 RCA0
- Device (PCI0) {
- //
- // Hardware ID must be PNP0A08, which maps to a PCIe root complex.
- // Section 6.1.5
- //
- Name (_HID, "PNP0A08")
- Name (_CCA, ONE)
- Method (_STA, 0, NotSerialized) {
- Return (0xF) // The default value is 0x0. Unfortunately, it breaks
- // run-time patching as the representation of 0 is special
- // encoding and cannot be patched to expand with extra bytes
- // easily. As such, we default to 0xF and patch this based
- // on whether the port was enabled or not by the BIOS.
- }
- //
- // Optionally, include a compatible ID of PNP0A03, which maps to a PCI
- // root complex for use with pre-PCIe operating systems.
- // Section 6.1.2
- //
- Name (_CID, "PNP0A03")
- //
- // Declare the segment number of this root complex. Most systems only
- // have one segment, which is numbered 0.
- // Section 6.5.6
- //
- Name (_SEG, 12)
- //
- // Declare the base bus number, which is the bus number of the root
- // bus in this root complex. This is usually 0, but need not be.
- // For root complexes supporting multiple root busses, this should
- // be the lowest numbered root bus.
- // Section 6.5.5
- //
- Name (_BBN, 0)
- //
- // The _UID value provides a way of uniquely identifying a device
- // in the case where more than one instance of a specific device
- // is implemented with the same _HID/_CID. For systems with a
- // single root complex, this is usually just 0. For systems with
- // multiple root complexes, this should be different for each
- // root complex.
- // Section 6.1.12
- //
- Name (_UID, "PCI0")
- Name (_STR, Unicode("PCIe 0 Device"))
- //
- // Declare the PCI Routing Table.
- // This defines SPI mappings of the four line-based interrupts
- // associated with the root complex and hierarchy below it.
- // Section 6.2.12
- //
- Name (_PRT, Package() {
- //
- // Routing for device 0, all functions.
- // Note: ARM doesn't support LNK nodes, so the third param
- // is 0 and the fourth param is the SPI number of the interrupt
- // line. In this example, the A/B/C/D interrupts are wired to
- // SPI lines 128/129/130/131 respectively. PCI0 RCA0
- //
- Package() {0x0001FFFF, 0, 0, 128},
- Package() {0x0001FFFF, 1, 0, 129},
- Package() {0x0001FFFF, 2, 0, 130},
- Package() {0x0001FFFF, 3, 0, 131},
- Package() {0x0002FFFF, 0, 0, 128},
- Package() {0x0002FFFF, 1, 0, 129},
- Package() {0x0002FFFF, 2, 0, 130},
- Package() {0x0002FFFF, 3, 0, 131},
- Package() {0x0003FFFF, 0, 0, 128},
- Package() {0x0003FFFF, 1, 0, 129},
- Package() {0x0003FFFF, 2, 0, 130},
- Package() {0x0003FFFF, 3, 0, 131},
- Package() {0x0004FFFF, 0, 0, 128},
- Package() {0x0004FFFF, 1, 0, 129},
- Package() {0x0004FFFF, 2, 0, 130},
- Package() {0x0004FFFF, 3, 0, 131},
- })
- //
- // Declare the resources assigned to this root complex.
- // Section 6.2.2
- //
- Method (_CBA, 0, Serialized) {
- Return (0x33FFF0000000)
- }
- Name (RBUF, ResourceTemplate () {
- //
- // Declare the range of bus numbers assigned to this root
- // complex. In this example, the minimum bus number will be
- // 0, the maximum bus number will be 0xFF, supporting
- // 256 busses total.
- // Section 19.5.141
- //
- WordBusNumber (
- ResourceProducer,
- MinFixed, // IsMinFixed
- MaxFixed, // IsMaxFixed
- PosDecode, // Decode
- 0, // AddressGranularity
- 0, // AddressMinimum - Minimum Bus Number
- 255, // AddressMaximum - Maximum Bus Number
- 0, // AddressTranslation - Set to 0
- 256) // RangeLength - Number of Busses
- //
- // Declare the memory range to be used for BAR memory
- // windows. This declares a 4GB region starting at
- // 0x4000000000.
- // Section 19.5.80
- //
- // Memory32Fixed (ReadWrite, 0x1FE40000, 0x10000, )
- QWordMemory (
- ResourceProducer, // ResourceUsage
- PosDecode, // Decode
- MinFixed, // IsMinFixed
- MaxFixed, // IsMaxFixed
- Cacheable, // Cacheable
- ReadWrite, // ReadAndWrite
- 0x0000000000000000, // AddressGranularity - GRA
- 0x0000000040000000, // AddressMinimum - MIN
- 0x000000004FFFFFFF, // AddressMinimum - MAX
- 0x0000000000000000, // AddressTranslation - TRA
- 0x0000000010000000 // RangeLength - LEN
- )
- QWordMemory (
- ResourceProducer, // ResourceUsage
- PosDecode, // Decode
- MinFixed, // IsMinFixed
- MaxFixed, // IsMaxFixed
- Cacheable, // Cacheable
- ReadWrite, // ReadAndWrite
- 0x0000000000000000, // AddressGranularity - GRA
- 0x0000300000000000, // AddressMinimum - MIN
- 0x000033FFDFFFFFFF, // AddressMaximum - MAX
- 0x0000000000000000, // AddressTranslation - TRA
- 0x000003FFE0000000 // RangeLength - LEN
- )
- })
- Method (_CRS, 0, Serialized) {
- Return (RBUF)
- }
- //
- // Declare an _OSC (OS Control Handoff) method which takes 4 arguments.
- //
- // Argments:
- // Arg0 A Buffer containing a UUID
- // Arg1 An Integer containing a Revision ID of the buffer format
- // Arg2 An Integer containing a count of entries in Arg3
- // Arg3 A Buffer containing a list of DWORD capabilities
- // Return Value:
- // A Buffer containing a list of capabilities
- // See the APCI spec, Section 6.2.10,
- // and the PCI FW spec, Section 4.5.
- //
- // The following is an example, and may need modification for
- // specific implementations.
- //
- Name (SUPP,0) // PCI _OSC Support Field value
- Name (CTRL,0) // PCI _OSC Control Field value
- Method (_OSC, 4) {
- //
- // Look for the PCI Host Bridge Interface UUID.
- // Section 6.2.10.3
- //
- //
- // Create DWord-adressable fields from the Capabilities Buffer
- // Create CDW1 outside the test as it's used in the else clause.
- //
- CreateDWordField (Arg3, 0, CDW1)
- If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
- CreateDWordField (Arg3, 4, CDW2)
- CreateDWordField (Arg3, 8, CDW3)
- //
- // Save Capabilities DWord 2 & 3
- //
- Store (CDW2, SUPP)
- Store (CDW3, CTRL)
- //
- // Only allow native hot plug control if OS supports:
- // ASPM
- // Clock PM
- // MSI/MSI-X
- //
- If (LNotEqual (And (SUPP, 0x16), 0x16)) {
- //
- // Mask bit 0 (and undefined bits)
- //
- And (CTRL, 0x1E, CTRL)
- }
- //
- // Never allow native Hot plug, PME.
- // Never allow SHPC (no SHPC controller in this system).
- // Only allow PCIe AER control if PCIe AER Firmware-First is disabled
- // Allows PCI Express Capability Structure control
- //
- if (AERF) {
- And (CTRL, 0x10, CTRL)
- } Else {
- And (CTRL, 0x18, CTRL)
- }
- //
- // Check for unknown revision.
- //
- If (LNotEqual (Arg1, One)) {
- Or (CDW1, 0x08, CDW1)
- }
- //
- // Check if capabilities bits were masked.
- //
- If (LNotEqual (CDW3, CTRL)) {
- Or (CDW1, 0x10, CDW1)
- }
- //
- // Update DWORD3 in the buffer.
- //
- Store (CTRL, CDW3)
- Return (Arg3)
- } Else {
- //
- // Unrecognized UUID
- //
- Or (CDW1, 4, CDW1)
- Return (Arg3)
- }
- } // End _OSC
- //
- // Declare a _DSM method for various functions called by the OS.
- // See the APCI spec, Section 9.14.1,
- // and the PCI FW spec, Section 4.6.
- // See also:
- // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc
- //
- Method (_DSM, 0x4, Serialized) {
- //
- // Match against the _DSM PCI GUID.
- //
- If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
- Switch (ToInteger(Arg2)) {
- //
- // Function 0: Return supported functions as a bitfield
- // with one bit for each supported function.
- // Bit 0 must always be set, as that represents
- // function 0 (which is what is being called here).
- // Support for different functions may depend on
- // the revision ID of the interface, passed as Arg1.
- //
- Case (0) {
- //
- // Functions 0-7 are supported.
- //
- Return (Buffer() {0x01})
- }
- }
- }
- //
- // If not one of the function identifiers we recognize, then return a buffer
- // with bit 0 set to 0 indicating no functions supported.
- //
- Return (Buffer() {0})
- }
- //
- // Root Port 0 Device within the Root Complex.
- //
- Device (RP0) {
- //
- // Device 0, Function 0.
- //
- Name (_ADR, 0x00000000)
- }
- Method (_PXM, 0, NotSerialized) {
- // Patch by code
- Return(0xFF)
- }
- } // PCI0 RCA0
- // PCI1 RCA1
- Device (PCI1) {
- //
- // Hardware ID must be PNP0A08, which maps to a PCIe root complex.
- // Section 6.1.5
- //
- Name (_HID, "PNP0A08")
- Name (_CCA, ONE)
- Method (_STA, 0, NotSerialized) {
- Return (0xF) // The default value is 0x0. Unfortunately, it breaks
- // run-time patching as the representation of 0 is special
- // encoding and cannot be patched to expand with extra bytes
- // easily. As such, we default to 0xF and patch this based
- // on whether the port was enabled or not by the BIOS.
- }
- //
- // Optionally, include a compatible ID of PNP0A03, which maps to a PCI
- // root complex for use with pre-PCIe operating systems.
- // Section 6.1.2
- //
- Name (_CID, "PNP0A03")
- //
- // Declare the segment number of this root complex. Most systems only
- // have one segment, which is numbered 0.
- // Section 6.5.6
- //
- Name (_SEG, 13)
- //
- // Declare the base bus number, which is the bus number of the root
- // bus in this root complex. This is usually 0, but need not be.
- // For root complexes supporting multiple root busses, this should
- // be the lowest numbered root bus.
- // Section 6.5.5
- //
- Name (_BBN, 0)
- //
- // The _UID value provides a way of uniquely identifying a device
- // in the case where more than one instance of a specific device
- // is implemented with the same _HID/_CID. For systems with a
- // single root complex, this is usually just 0. For systems with
- // multiple root complexes, this should be different for each
- // root complex.
- // Section 6.1.12
- //
- Name (_UID, "PCI1")
- Name (_STR, Unicode("PCIe 1 Device"))
- //
- // Declare the PCI Routing Table.
- // This defines SPI mappings of the four line-based interrupts
- // associated with the root complex and hierarchy below it.
- // Section 6.2.12
- //
- Name (_PRT, Package() {
- //
- // Routing for device 0, all functions.
- // Note: ARM doesn't support LNK nodes, so the third param
- // is 0 and the fourth param is the SPI number of the interrupt
- // line. In this example, the A/B/C/D interrupts are wired to
- // SPI lines 132/133/134/135 respectively. PCI1 RCA1
- //
- Package() {0x0001FFFF, 0, 0, 132},
- Package() {0x0001FFFF, 1, 0, 133},
- Package() {0x0001FFFF, 2, 0, 134},
- Package() {0x0001FFFF, 3, 0, 135},
- Package() {0x0002FFFF, 0, 0, 132},
- Package() {0x0002FFFF, 1, 0, 133},
- Package() {0x0002FFFF, 2, 0, 134},
- Package() {0x0002FFFF, 3, 0, 135},
- Package() {0x0003FFFF, 0, 0, 132},
- Package() {0x0003FFFF, 1, 0, 133},
- Package() {0x0003FFFF, 2, 0, 134},
- Package() {0x0003FFFF, 3, 0, 135},
- Package() {0x0004FFFF, 0, 0, 132},
- Package() {0x0004FFFF, 1, 0, 133},
- Package() {0x0004FFFF, 2, 0, 134},
- Package() {0x0004FFFF, 3, 0, 135},
- })
- //
- // Declare the resources assigned to this root complex.
- // Section 6.2.2
- //
- Method (_CBA, 0, Serialized) {
- Return (0x37FFF0000000)
- }
- Name (RBUF, ResourceTemplate () {
- //
- // Declare the range of bus numbers assigned to this root
- // complex. In this example, the minimum bus number will be
- // 0, the maximum bus number will be 0xFF, supporting
- // 256 busses total.
- // Section 19.5.141
- //
- WordBusNumber (
- ResourceProducer,
- MinFixed, // IsMinFixed
- MaxFixed, // IsMaxFixed
- PosDecode, // Decode
- 0, // AddressGranularity
- 0, // AddressMinimum - Minimum Bus Number
- 255, // AddressMaximum - Maximum Bus Number
- 0, // AddressTranslation - Set to 0
- 256) // RangeLength - Number of Busses
- //
- // Declare the memory range to be used for BAR memory
- // windows. This declares a 4GB region starting at
- // 0x4000000000.
- // Section 19.5.80
- //
- // Memory32Fixed (ReadWrite, 0x1FE40000, 0x10000, )
- QWordMemory (
- ResourceProducer, // ResourceUsage
- PosDecode, // Decode
- MinFixed, // IsMinFixed
- MaxFixed, // IsMaxFixed
- Cacheable, // Cacheable
- ReadWrite, // ReadAndWrite
- 0x0000000000000000, // AddressGranularity - GRA
- 0x0000000050000000, // AddressMinimum - MIN
- 0x000000005FFFFFFF, // AddressMinimum - MAX
- 0x0000000000000000, // AddressTranslation - TRA
- 0x0000000010000000 // RangeLength - LEN
- )
- QWordMemory (
- ResourceProducer, // ResourceUsage
- PosDecode, // Decode
- MinFixed, // IsMinFixed
- MaxFixed, // IsMaxFixed
- Cacheable, // Cacheable
- ReadWrite, // ReadAndWrite
- 0x0000000000000000, // AddressGranularity - GRA
- 0x0000340000000000, // AddressMinimum - MIN
- 0x000037FFDFFFFFFF, // AddressMaximum - MAX
- 0x0000000000000000, // AddressTranslation - TRA
- 0x000003FFE0000000 // RangeLength - LEN
- )
- })
- Method (_CRS, 0, Serialized) {
- Return (RBUF)
- }
- //
- // Declare an _OSC (OS Control Handoff) method which takes 4 arguments.
- //
- // Argments:
- // Arg0 A Buffer containing a UUID
- // Arg1 An Integer containing a Revision ID of the buffer format
- // Arg2 An Integer containing a count of entries in Arg3
- // Arg3 A Buffer containing a list of DWORD capabilities
- // Return Value:
- // A Buffer containing a list of capabilities
- // See the APCI spec, Section 6.2.10,
- // and the PCI FW spec, Section 4.5.
- //
- // The following is an example, and may need modification for
- // specific implementations.
- //
- Name (SUPP,0) // PCI _OSC Support Field value
- Name (CTRL,0) // PCI _OSC Control Field value
- Method (_OSC, 4) {
- //
- // Look for the PCI Host Bridge Interface UUID.
- // Section 6.2.10.3
- //
- //
- // Create DWord-adressable fields from the Capabilities Buffer
- // Create CDW1 outside the test as it's used in the else clause.
- //
- CreateDWordField (Arg3, 0, CDW1)
- If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
- CreateDWordField (Arg3, 4, CDW2)
- CreateDWordField (Arg3, 8, CDW3)
- //
- // Save Capabilities DWord 2 & 3
- //
- Store (CDW2, SUPP)
- Store (CDW3, CTRL)
- //
- // Only allow native hot plug control if OS supports:
- // ASPM
- // Clock PM
- // MSI/MSI-X
- //
- If (LNotEqual (And (SUPP, 0x16), 0x16)) {
- //
- // Mask bit 0 (and undefined bits)
- //
- And (CTRL, 0x1E, CTRL)
- }
- //
- // Never allow native Hot plug, PME.
- // Never allow SHPC (no SHPC controller in this system).
- // Only allow PCIe AER control if PCIe AER Firmware-First is disabled
- // Allows PCI Express Capability Structure control
- //
- if (AERF) {
- And (CTRL, 0x10, CTRL)
- } Else {
- And (CTRL, 0x18, CTRL)
- }
- //
- // Check for unknown revision.
- //
- If (LNotEqual (Arg1, One)) {
- Or (CDW1, 0x08, CDW1)
- }
- //
- // Check if capabilities bits were masked.
- //
- If (LNotEqual (CDW3, CTRL)) {
- Or (CDW1, 0x10, CDW1)
- }
- //
- // Update DWORD3 in the buffer.
- //
- Store (CTRL, CDW3)
- Return (Arg3)
- } Else {
- //
- // Unrecognized UUID
- //
- Or (CDW1, 4, CDW1)
- Return (Arg3)
- }
- } // End _OSC
- //
- // Declare a _DSM method for various functions called by the OS.
- // See the APCI spec, Section 9.14.1,
- // and the PCI FW spec, Section 4.6.
- // See also:
- // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc
- //
- Method (_DSM, 0x4, Serialized) {
- //
- // Match against the _DSM PCI GUID.
- //
- If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
- Switch (ToInteger(Arg2)) {
- //
- // Function 0: Return supported functions as a bitfield
- // with one bit for each supported function.
- // Bit 0 must always be set, as that represents
- // function 0 (which is what is being called here).
- // Support for different functions may depend on
- // the revision ID of the interface, passed as Arg1.
- //
- Case (0) {
- //
- // Functions 0-7 are supported.
- //
- Return (Buffer() {0x01})
- }
- }
- }
- //
- // If not one of the function identifiers we recognize, then return a buffer
- // with bit 0 set to 0 indicating no functions supported.
- //
- Return (Buffer() {0})
- }
- //
- // Root Port 0 Device within the Root Complex.
- //
- Device (RP0) {
- //
- // Device 0, Function 0.
- //
- Name (_ADR, 0x00000000)
- }
- Method (_PXM, 0, NotSerialized) {
- // Patch by code
- Return(0xFF)
- }
- } // PCI1 RCA1
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