PCI-S0.Rca01.asi 18 KB

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  1. /** @file
  2. Copyright (c) 2023, Ampere Computing LLC. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. // PCI0 RCA0
  6. Device (PCI0) {
  7. //
  8. // Hardware ID must be PNP0A08, which maps to a PCIe root complex.
  9. // Section 6.1.5
  10. //
  11. Name (_HID, "PNP0A08")
  12. Name (_CCA, ONE)
  13. Method (_STA, 0, NotSerialized) {
  14. Return (0xF) // The default value is 0x0. Unfortunately, it breaks
  15. // run-time patching as the representation of 0 is special
  16. // encoding and cannot be patched to expand with extra bytes
  17. // easily. As such, we default to 0xF and patch this based
  18. // on whether the port was enabled or not by the BIOS.
  19. }
  20. //
  21. // Optionally, include a compatible ID of PNP0A03, which maps to a PCI
  22. // root complex for use with pre-PCIe operating systems.
  23. // Section 6.1.2
  24. //
  25. Name (_CID, "PNP0A03")
  26. //
  27. // Declare the segment number of this root complex. Most systems only
  28. // have one segment, which is numbered 0.
  29. // Section 6.5.6
  30. //
  31. Name (_SEG, 12)
  32. //
  33. // Declare the base bus number, which is the bus number of the root
  34. // bus in this root complex. This is usually 0, but need not be.
  35. // For root complexes supporting multiple root busses, this should
  36. // be the lowest numbered root bus.
  37. // Section 6.5.5
  38. //
  39. Name (_BBN, 0)
  40. //
  41. // The _UID value provides a way of uniquely identifying a device
  42. // in the case where more than one instance of a specific device
  43. // is implemented with the same _HID/_CID. For systems with a
  44. // single root complex, this is usually just 0. For systems with
  45. // multiple root complexes, this should be different for each
  46. // root complex.
  47. // Section 6.1.12
  48. //
  49. Name (_UID, "PCI0")
  50. Name (_STR, Unicode("PCIe 0 Device"))
  51. //
  52. // Declare the PCI Routing Table.
  53. // This defines SPI mappings of the four line-based interrupts
  54. // associated with the root complex and hierarchy below it.
  55. // Section 6.2.12
  56. //
  57. Name (_PRT, Package() {
  58. //
  59. // Routing for device 0, all functions.
  60. // Note: ARM doesn't support LNK nodes, so the third param
  61. // is 0 and the fourth param is the SPI number of the interrupt
  62. // line. In this example, the A/B/C/D interrupts are wired to
  63. // SPI lines 128/129/130/131 respectively. PCI0 RCA0
  64. //
  65. Package() {0x0001FFFF, 0, 0, 128},
  66. Package() {0x0001FFFF, 1, 0, 129},
  67. Package() {0x0001FFFF, 2, 0, 130},
  68. Package() {0x0001FFFF, 3, 0, 131},
  69. Package() {0x0002FFFF, 0, 0, 128},
  70. Package() {0x0002FFFF, 1, 0, 129},
  71. Package() {0x0002FFFF, 2, 0, 130},
  72. Package() {0x0002FFFF, 3, 0, 131},
  73. Package() {0x0003FFFF, 0, 0, 128},
  74. Package() {0x0003FFFF, 1, 0, 129},
  75. Package() {0x0003FFFF, 2, 0, 130},
  76. Package() {0x0003FFFF, 3, 0, 131},
  77. Package() {0x0004FFFF, 0, 0, 128},
  78. Package() {0x0004FFFF, 1, 0, 129},
  79. Package() {0x0004FFFF, 2, 0, 130},
  80. Package() {0x0004FFFF, 3, 0, 131},
  81. })
  82. //
  83. // Declare the resources assigned to this root complex.
  84. // Section 6.2.2
  85. //
  86. Method (_CBA, 0, Serialized) {
  87. Return (0x33FFF0000000)
  88. }
  89. Name (RBUF, ResourceTemplate () {
  90. //
  91. // Declare the range of bus numbers assigned to this root
  92. // complex. In this example, the minimum bus number will be
  93. // 0, the maximum bus number will be 0xFF, supporting
  94. // 256 busses total.
  95. // Section 19.5.141
  96. //
  97. WordBusNumber (
  98. ResourceProducer,
  99. MinFixed, // IsMinFixed
  100. MaxFixed, // IsMaxFixed
  101. PosDecode, // Decode
  102. 0, // AddressGranularity
  103. 0, // AddressMinimum - Minimum Bus Number
  104. 255, // AddressMaximum - Maximum Bus Number
  105. 0, // AddressTranslation - Set to 0
  106. 256) // RangeLength - Number of Busses
  107. //
  108. // Declare the memory range to be used for BAR memory
  109. // windows. This declares a 4GB region starting at
  110. // 0x4000000000.
  111. // Section 19.5.80
  112. //
  113. // Memory32Fixed (ReadWrite, 0x1FE40000, 0x10000, )
  114. QWordMemory (
  115. ResourceProducer, // ResourceUsage
  116. PosDecode, // Decode
  117. MinFixed, // IsMinFixed
  118. MaxFixed, // IsMaxFixed
  119. Cacheable, // Cacheable
  120. ReadWrite, // ReadAndWrite
  121. 0x0000000000000000, // AddressGranularity - GRA
  122. 0x0000000040000000, // AddressMinimum - MIN
  123. 0x000000004FFFFFFF, // AddressMinimum - MAX
  124. 0x0000000000000000, // AddressTranslation - TRA
  125. 0x0000000010000000 // RangeLength - LEN
  126. )
  127. QWordMemory (
  128. ResourceProducer, // ResourceUsage
  129. PosDecode, // Decode
  130. MinFixed, // IsMinFixed
  131. MaxFixed, // IsMaxFixed
  132. Cacheable, // Cacheable
  133. ReadWrite, // ReadAndWrite
  134. 0x0000000000000000, // AddressGranularity - GRA
  135. 0x0000300000000000, // AddressMinimum - MIN
  136. 0x000033FFDFFFFFFF, // AddressMaximum - MAX
  137. 0x0000000000000000, // AddressTranslation - TRA
  138. 0x000003FFE0000000 // RangeLength - LEN
  139. )
  140. })
  141. Method (_CRS, 0, Serialized) {
  142. Return (RBUF)
  143. }
  144. //
  145. // Declare an _OSC (OS Control Handoff) method which takes 4 arguments.
  146. //
  147. // Argments:
  148. // Arg0 A Buffer containing a UUID
  149. // Arg1 An Integer containing a Revision ID of the buffer format
  150. // Arg2 An Integer containing a count of entries in Arg3
  151. // Arg3 A Buffer containing a list of DWORD capabilities
  152. // Return Value:
  153. // A Buffer containing a list of capabilities
  154. // See the APCI spec, Section 6.2.10,
  155. // and the PCI FW spec, Section 4.5.
  156. //
  157. // The following is an example, and may need modification for
  158. // specific implementations.
  159. //
  160. Name (SUPP,0) // PCI _OSC Support Field value
  161. Name (CTRL,0) // PCI _OSC Control Field value
  162. Method (_OSC, 4) {
  163. //
  164. // Look for the PCI Host Bridge Interface UUID.
  165. // Section 6.2.10.3
  166. //
  167. //
  168. // Create DWord-adressable fields from the Capabilities Buffer
  169. // Create CDW1 outside the test as it's used in the else clause.
  170. //
  171. CreateDWordField (Arg3, 0, CDW1)
  172. If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
  173. CreateDWordField (Arg3, 4, CDW2)
  174. CreateDWordField (Arg3, 8, CDW3)
  175. //
  176. // Save Capabilities DWord 2 & 3
  177. //
  178. Store (CDW2, SUPP)
  179. Store (CDW3, CTRL)
  180. //
  181. // Only allow native hot plug control if OS supports:
  182. // ASPM
  183. // Clock PM
  184. // MSI/MSI-X
  185. //
  186. If (LNotEqual (And (SUPP, 0x16), 0x16)) {
  187. //
  188. // Mask bit 0 (and undefined bits)
  189. //
  190. And (CTRL, 0x1E, CTRL)
  191. }
  192. //
  193. // Never allow native Hot plug, PME.
  194. // Never allow SHPC (no SHPC controller in this system).
  195. // Only allow PCIe AER control if PCIe AER Firmware-First is disabled
  196. // Allows PCI Express Capability Structure control
  197. //
  198. if (AERF) {
  199. And (CTRL, 0x10, CTRL)
  200. } Else {
  201. And (CTRL, 0x18, CTRL)
  202. }
  203. //
  204. // Check for unknown revision.
  205. //
  206. If (LNotEqual (Arg1, One)) {
  207. Or (CDW1, 0x08, CDW1)
  208. }
  209. //
  210. // Check if capabilities bits were masked.
  211. //
  212. If (LNotEqual (CDW3, CTRL)) {
  213. Or (CDW1, 0x10, CDW1)
  214. }
  215. //
  216. // Update DWORD3 in the buffer.
  217. //
  218. Store (CTRL, CDW3)
  219. Return (Arg3)
  220. } Else {
  221. //
  222. // Unrecognized UUID
  223. //
  224. Or (CDW1, 4, CDW1)
  225. Return (Arg3)
  226. }
  227. } // End _OSC
  228. //
  229. // Declare a _DSM method for various functions called by the OS.
  230. // See the APCI spec, Section 9.14.1,
  231. // and the PCI FW spec, Section 4.6.
  232. // See also:
  233. // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc
  234. //
  235. Method (_DSM, 0x4, Serialized) {
  236. //
  237. // Match against the _DSM PCI GUID.
  238. //
  239. If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
  240. Switch (ToInteger(Arg2)) {
  241. //
  242. // Function 0: Return supported functions as a bitfield
  243. // with one bit for each supported function.
  244. // Bit 0 must always be set, as that represents
  245. // function 0 (which is what is being called here).
  246. // Support for different functions may depend on
  247. // the revision ID of the interface, passed as Arg1.
  248. //
  249. Case (0) {
  250. //
  251. // Functions 0-7 are supported.
  252. //
  253. Return (Buffer() {0x01})
  254. }
  255. }
  256. }
  257. //
  258. // If not one of the function identifiers we recognize, then return a buffer
  259. // with bit 0 set to 0 indicating no functions supported.
  260. //
  261. Return (Buffer() {0})
  262. }
  263. //
  264. // Root Port 0 Device within the Root Complex.
  265. //
  266. Device (RP0) {
  267. //
  268. // Device 0, Function 0.
  269. //
  270. Name (_ADR, 0x00000000)
  271. }
  272. Method (_PXM, 0, NotSerialized) {
  273. // Patch by code
  274. Return(0xFF)
  275. }
  276. } // PCI0 RCA0
  277. // PCI1 RCA1
  278. Device (PCI1) {
  279. //
  280. // Hardware ID must be PNP0A08, which maps to a PCIe root complex.
  281. // Section 6.1.5
  282. //
  283. Name (_HID, "PNP0A08")
  284. Name (_CCA, ONE)
  285. Method (_STA, 0, NotSerialized) {
  286. Return (0xF) // The default value is 0x0. Unfortunately, it breaks
  287. // run-time patching as the representation of 0 is special
  288. // encoding and cannot be patched to expand with extra bytes
  289. // easily. As such, we default to 0xF and patch this based
  290. // on whether the port was enabled or not by the BIOS.
  291. }
  292. //
  293. // Optionally, include a compatible ID of PNP0A03, which maps to a PCI
  294. // root complex for use with pre-PCIe operating systems.
  295. // Section 6.1.2
  296. //
  297. Name (_CID, "PNP0A03")
  298. //
  299. // Declare the segment number of this root complex. Most systems only
  300. // have one segment, which is numbered 0.
  301. // Section 6.5.6
  302. //
  303. Name (_SEG, 13)
  304. //
  305. // Declare the base bus number, which is the bus number of the root
  306. // bus in this root complex. This is usually 0, but need not be.
  307. // For root complexes supporting multiple root busses, this should
  308. // be the lowest numbered root bus.
  309. // Section 6.5.5
  310. //
  311. Name (_BBN, 0)
  312. //
  313. // The _UID value provides a way of uniquely identifying a device
  314. // in the case where more than one instance of a specific device
  315. // is implemented with the same _HID/_CID. For systems with a
  316. // single root complex, this is usually just 0. For systems with
  317. // multiple root complexes, this should be different for each
  318. // root complex.
  319. // Section 6.1.12
  320. //
  321. Name (_UID, "PCI1")
  322. Name (_STR, Unicode("PCIe 1 Device"))
  323. //
  324. // Declare the PCI Routing Table.
  325. // This defines SPI mappings of the four line-based interrupts
  326. // associated with the root complex and hierarchy below it.
  327. // Section 6.2.12
  328. //
  329. Name (_PRT, Package() {
  330. //
  331. // Routing for device 0, all functions.
  332. // Note: ARM doesn't support LNK nodes, so the third param
  333. // is 0 and the fourth param is the SPI number of the interrupt
  334. // line. In this example, the A/B/C/D interrupts are wired to
  335. // SPI lines 132/133/134/135 respectively. PCI1 RCA1
  336. //
  337. Package() {0x0001FFFF, 0, 0, 132},
  338. Package() {0x0001FFFF, 1, 0, 133},
  339. Package() {0x0001FFFF, 2, 0, 134},
  340. Package() {0x0001FFFF, 3, 0, 135},
  341. Package() {0x0002FFFF, 0, 0, 132},
  342. Package() {0x0002FFFF, 1, 0, 133},
  343. Package() {0x0002FFFF, 2, 0, 134},
  344. Package() {0x0002FFFF, 3, 0, 135},
  345. Package() {0x0003FFFF, 0, 0, 132},
  346. Package() {0x0003FFFF, 1, 0, 133},
  347. Package() {0x0003FFFF, 2, 0, 134},
  348. Package() {0x0003FFFF, 3, 0, 135},
  349. Package() {0x0004FFFF, 0, 0, 132},
  350. Package() {0x0004FFFF, 1, 0, 133},
  351. Package() {0x0004FFFF, 2, 0, 134},
  352. Package() {0x0004FFFF, 3, 0, 135},
  353. })
  354. //
  355. // Declare the resources assigned to this root complex.
  356. // Section 6.2.2
  357. //
  358. Method (_CBA, 0, Serialized) {
  359. Return (0x37FFF0000000)
  360. }
  361. Name (RBUF, ResourceTemplate () {
  362. //
  363. // Declare the range of bus numbers assigned to this root
  364. // complex. In this example, the minimum bus number will be
  365. // 0, the maximum bus number will be 0xFF, supporting
  366. // 256 busses total.
  367. // Section 19.5.141
  368. //
  369. WordBusNumber (
  370. ResourceProducer,
  371. MinFixed, // IsMinFixed
  372. MaxFixed, // IsMaxFixed
  373. PosDecode, // Decode
  374. 0, // AddressGranularity
  375. 0, // AddressMinimum - Minimum Bus Number
  376. 255, // AddressMaximum - Maximum Bus Number
  377. 0, // AddressTranslation - Set to 0
  378. 256) // RangeLength - Number of Busses
  379. //
  380. // Declare the memory range to be used for BAR memory
  381. // windows. This declares a 4GB region starting at
  382. // 0x4000000000.
  383. // Section 19.5.80
  384. //
  385. // Memory32Fixed (ReadWrite, 0x1FE40000, 0x10000, )
  386. QWordMemory (
  387. ResourceProducer, // ResourceUsage
  388. PosDecode, // Decode
  389. MinFixed, // IsMinFixed
  390. MaxFixed, // IsMaxFixed
  391. Cacheable, // Cacheable
  392. ReadWrite, // ReadAndWrite
  393. 0x0000000000000000, // AddressGranularity - GRA
  394. 0x0000000050000000, // AddressMinimum - MIN
  395. 0x000000005FFFFFFF, // AddressMinimum - MAX
  396. 0x0000000000000000, // AddressTranslation - TRA
  397. 0x0000000010000000 // RangeLength - LEN
  398. )
  399. QWordMemory (
  400. ResourceProducer, // ResourceUsage
  401. PosDecode, // Decode
  402. MinFixed, // IsMinFixed
  403. MaxFixed, // IsMaxFixed
  404. Cacheable, // Cacheable
  405. ReadWrite, // ReadAndWrite
  406. 0x0000000000000000, // AddressGranularity - GRA
  407. 0x0000340000000000, // AddressMinimum - MIN
  408. 0x000037FFDFFFFFFF, // AddressMaximum - MAX
  409. 0x0000000000000000, // AddressTranslation - TRA
  410. 0x000003FFE0000000 // RangeLength - LEN
  411. )
  412. })
  413. Method (_CRS, 0, Serialized) {
  414. Return (RBUF)
  415. }
  416. //
  417. // Declare an _OSC (OS Control Handoff) method which takes 4 arguments.
  418. //
  419. // Argments:
  420. // Arg0 A Buffer containing a UUID
  421. // Arg1 An Integer containing a Revision ID of the buffer format
  422. // Arg2 An Integer containing a count of entries in Arg3
  423. // Arg3 A Buffer containing a list of DWORD capabilities
  424. // Return Value:
  425. // A Buffer containing a list of capabilities
  426. // See the APCI spec, Section 6.2.10,
  427. // and the PCI FW spec, Section 4.5.
  428. //
  429. // The following is an example, and may need modification for
  430. // specific implementations.
  431. //
  432. Name (SUPP,0) // PCI _OSC Support Field value
  433. Name (CTRL,0) // PCI _OSC Control Field value
  434. Method (_OSC, 4) {
  435. //
  436. // Look for the PCI Host Bridge Interface UUID.
  437. // Section 6.2.10.3
  438. //
  439. //
  440. // Create DWord-adressable fields from the Capabilities Buffer
  441. // Create CDW1 outside the test as it's used in the else clause.
  442. //
  443. CreateDWordField (Arg3, 0, CDW1)
  444. If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
  445. CreateDWordField (Arg3, 4, CDW2)
  446. CreateDWordField (Arg3, 8, CDW3)
  447. //
  448. // Save Capabilities DWord 2 & 3
  449. //
  450. Store (CDW2, SUPP)
  451. Store (CDW3, CTRL)
  452. //
  453. // Only allow native hot plug control if OS supports:
  454. // ASPM
  455. // Clock PM
  456. // MSI/MSI-X
  457. //
  458. If (LNotEqual (And (SUPP, 0x16), 0x16)) {
  459. //
  460. // Mask bit 0 (and undefined bits)
  461. //
  462. And (CTRL, 0x1E, CTRL)
  463. }
  464. //
  465. // Never allow native Hot plug, PME.
  466. // Never allow SHPC (no SHPC controller in this system).
  467. // Only allow PCIe AER control if PCIe AER Firmware-First is disabled
  468. // Allows PCI Express Capability Structure control
  469. //
  470. if (AERF) {
  471. And (CTRL, 0x10, CTRL)
  472. } Else {
  473. And (CTRL, 0x18, CTRL)
  474. }
  475. //
  476. // Check for unknown revision.
  477. //
  478. If (LNotEqual (Arg1, One)) {
  479. Or (CDW1, 0x08, CDW1)
  480. }
  481. //
  482. // Check if capabilities bits were masked.
  483. //
  484. If (LNotEqual (CDW3, CTRL)) {
  485. Or (CDW1, 0x10, CDW1)
  486. }
  487. //
  488. // Update DWORD3 in the buffer.
  489. //
  490. Store (CTRL, CDW3)
  491. Return (Arg3)
  492. } Else {
  493. //
  494. // Unrecognized UUID
  495. //
  496. Or (CDW1, 4, CDW1)
  497. Return (Arg3)
  498. }
  499. } // End _OSC
  500. //
  501. // Declare a _DSM method for various functions called by the OS.
  502. // See the APCI spec, Section 9.14.1,
  503. // and the PCI FW spec, Section 4.6.
  504. // See also:
  505. // http://download.microsoft.com/download/9/c/5/9c5b2167-8017-4bae-9fde-d599bac8184a/PCI-rsc.doc
  506. //
  507. Method (_DSM, 0x4, Serialized) {
  508. //
  509. // Match against the _DSM PCI GUID.
  510. //
  511. If (LEqual (Arg0, ToUUID("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {
  512. Switch (ToInteger(Arg2)) {
  513. //
  514. // Function 0: Return supported functions as a bitfield
  515. // with one bit for each supported function.
  516. // Bit 0 must always be set, as that represents
  517. // function 0 (which is what is being called here).
  518. // Support for different functions may depend on
  519. // the revision ID of the interface, passed as Arg1.
  520. //
  521. Case (0) {
  522. //
  523. // Functions 0-7 are supported.
  524. //
  525. Return (Buffer() {0x01})
  526. }
  527. }
  528. }
  529. //
  530. // If not one of the function identifiers we recognize, then return a buffer
  531. // with bit 0 set to 0 indicating no functions supported.
  532. //
  533. Return (Buffer() {0})
  534. }
  535. //
  536. // Root Port 0 Device within the Root Complex.
  537. //
  538. Device (RP0) {
  539. //
  540. // Device 0, Function 0.
  541. //
  542. Name (_ADR, 0x00000000)
  543. }
  544. Method (_PXM, 0, NotSerialized) {
  545. // Patch by code
  546. Return(0xFF)
  547. }
  548. } // PCI1 RCA1