NorFlash.h 11 KB

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  1. /** @file NorFlashDxe.h
  2. Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
  3. Copyright (c) 2017, Socionext Inc. All rights reserved.<BR>
  4. Copyright (c) 2017, Linaro, Ltd. All rights reserved.<BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #ifndef __NOR_FLASH_DXE_H__
  8. #define __NOR_FLASH_DXE_H__
  9. #include <PiDxe.h>
  10. #include <Guid/EventGroup.h>
  11. #include <Protocol/BlockIo.h>
  12. #include <Protocol/DiskIo.h>
  13. #include <Protocol/FirmwareVolumeBlock.h>
  14. #include <Library/DebugLib.h>
  15. #include <Library/IoLib.h>
  16. #include "Fip006Reg.h"
  17. #define NOR_FLASH_ERASE_RETRY 10
  18. #define GET_NOR_BLOCK_ADDRESS(BaseAddr, Lba, LbaSize) \
  19. ((BaseAddr) + (UINTN)((Lba) * (LbaSize)))
  20. #define NOR_FLASH_SIGNATURE SIGNATURE_32('S', 'n', 'o', 'r')
  21. #define INSTANCE_FROM_FVB_THIS(a) CR(a, NOR_FLASH_INSTANCE, FvbProtocol, \
  22. NOR_FLASH_SIGNATURE)
  23. #define INSTANCE_FROM_BLKIO_THIS(a) CR(a, NOR_FLASH_INSTANCE, BlockIoProtocol,\
  24. NOR_FLASH_SIGNATURE)
  25. #define INSTANCE_FROM_DISKIO_THIS(a) CR(a, NOR_FLASH_INSTANCE, DiskIoProtocol, \
  26. NOR_FLASH_SIGNATURE)
  27. #define CSDC(Data, Cont, Trp, Dec) \
  28. (((Data) << 8) | (((Cont) & 1) << 3) | (((Trp) & 3) << 1) | ((Dec) & 1))
  29. #define CSDC_TRP_MBM 0
  30. #define CSDC_TRP_DUAL 1
  31. #define CSDC_TRP_QUAD 2
  32. #define CSDC_TRP_SINGLE 3
  33. #define CSDC_DEC_LEAVE_ASIS 0
  34. #define CSDC_DEC_DECODE 1
  35. #define CSDC_CONT_NON_CONTINUOUS 0
  36. #define CSDC_CONT_CONTINUOUS 1
  37. #define CSDC_ADDRESS_7_0 0x0
  38. #define CSDC_ADDRESS_15_8 0x1
  39. #define CSDC_ADDRESS_23_16 0x2
  40. #define CSDC_ADDRESS_31_24 0x3
  41. #define CSDC_HIGH_Z 0x4
  42. #define CSDC_END 0x7
  43. typedef struct {
  44. UINT8 Code;
  45. BOOLEAN AddrAccess;
  46. BOOLEAN AddrMode4Byte;
  47. BOOLEAN HighZ;
  48. BOOLEAN ReadWrite;
  49. UINT8 CscfgMbm;
  50. UINT8 CsdcTrp;
  51. } CSDC_DEFINITION;
  52. typedef struct _NOR_FLASH_INSTANCE NOR_FLASH_INSTANCE;
  53. typedef EFI_STATUS (*NOR_FLASH_INITIALIZE) (NOR_FLASH_INSTANCE* Instance);
  54. #pragma pack(1)
  55. typedef struct {
  56. VENDOR_DEVICE_PATH Vendor;
  57. UINT8 Index;
  58. EFI_DEVICE_PATH_PROTOCOL End;
  59. } NOR_FLASH_DEVICE_PATH;
  60. #pragma pack()
  61. struct _NOR_FLASH_INSTANCE {
  62. UINT32 Signature;
  63. EFI_HANDLE Handle;
  64. BOOLEAN Initialized;
  65. NOR_FLASH_INITIALIZE Initialize;
  66. UINTN HostRegisterBaseAddress;
  67. UINTN DeviceBaseAddress;
  68. UINTN RegionBaseAddress;
  69. UINTN Size;
  70. UINTN BlockSize;
  71. UINTN LastBlock;
  72. EFI_LBA StartLba;
  73. EFI_LBA OffsetLba;
  74. EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL FvbProtocol;
  75. VOID* ShadowBuffer;
  76. NOR_FLASH_DEVICE_PATH DevicePath;
  77. UINT32 Flags;
  78. #define NOR_FLASH_POLL_FSR BIT0
  79. };
  80. typedef struct {
  81. EFI_TPL OriginalTPL;
  82. BOOLEAN InterruptsEnabled;
  83. } NOR_FLASH_LOCK_CONTEXT;
  84. VOID
  85. EFIAPI
  86. NorFlashLock (
  87. NOR_FLASH_LOCK_CONTEXT *Context
  88. );
  89. VOID
  90. EFIAPI
  91. NorFlashUnlock (
  92. NOR_FLASH_LOCK_CONTEXT *Context
  93. );
  94. EFI_STATUS
  95. NorFlashReadCfiData (
  96. IN UINTN DeviceBaseAddress,
  97. IN UINTN CFI_Offset,
  98. IN UINT32 NumberOfBytes,
  99. OUT UINT32 *Data
  100. );
  101. EFI_STATUS
  102. NorFlashWriteBuffer (
  103. IN NOR_FLASH_INSTANCE *Instance,
  104. IN UINTN TargetAddress,
  105. IN UINTN BufferSizeInBytes,
  106. IN UINT32 *Buffer
  107. );
  108. extern UINTN mFlashNvStorageVariableBase;
  109. EFI_STATUS
  110. NorFlashCreateInstance (
  111. IN UINTN HostRegisterBase,
  112. IN UINTN NorFlashDeviceBase,
  113. IN UINTN NorFlashRegionBase,
  114. IN UINTN NorFlashSize,
  115. IN UINT32 Index,
  116. IN UINT32 BlockSize,
  117. IN BOOLEAN HasVarStore,
  118. OUT NOR_FLASH_INSTANCE** NorFlashInstance
  119. );
  120. EFI_STATUS
  121. EFIAPI
  122. NorFlashFvbInitialize (
  123. IN NOR_FLASH_INSTANCE* Instance
  124. );
  125. EFI_STATUS
  126. ValidateFvHeader (
  127. IN NOR_FLASH_INSTANCE *Instance
  128. );
  129. EFI_STATUS
  130. InitializeFvAndVariableStoreHeaders (
  131. IN NOR_FLASH_INSTANCE *Instance
  132. );
  133. EFI_STATUS
  134. EFIAPI
  135. FvbGetAttributes(
  136. IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
  137. OUT EFI_FVB_ATTRIBUTES_2 *Attributes
  138. );
  139. EFI_STATUS
  140. EFIAPI
  141. FvbSetAttributes(
  142. IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
  143. IN OUT EFI_FVB_ATTRIBUTES_2 *Attributes
  144. );
  145. EFI_STATUS
  146. EFIAPI
  147. FvbGetPhysicalAddress(
  148. IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
  149. OUT EFI_PHYSICAL_ADDRESS *Address
  150. );
  151. EFI_STATUS
  152. EFIAPI
  153. FvbGetBlockSize(
  154. IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
  155. IN EFI_LBA Lba,
  156. OUT UINTN *BlockSize,
  157. OUT UINTN *NumberOfBlocks
  158. );
  159. EFI_STATUS
  160. EFIAPI
  161. FvbRead(
  162. IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
  163. IN EFI_LBA Lba,
  164. IN UINTN Offset,
  165. IN OUT UINTN *NumBytes,
  166. IN OUT UINT8 *Buffer
  167. );
  168. EFI_STATUS
  169. EFIAPI
  170. FvbWrite(
  171. IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
  172. IN EFI_LBA Lba,
  173. IN UINTN Offset,
  174. IN OUT UINTN *NumBytes,
  175. IN UINT8 *Buffer
  176. );
  177. EFI_STATUS
  178. EFIAPI
  179. FvbEraseBlocks(
  180. IN CONST EFI_FIRMWARE_VOLUME_BLOCK2_PROTOCOL *This,
  181. ...
  182. );
  183. //
  184. // NorFlashDxe.c
  185. //
  186. EFI_STATUS
  187. NorFlashUnlockAndEraseSingleBlock (
  188. IN NOR_FLASH_INSTANCE *Instance,
  189. IN UINTN BlockAddress
  190. );
  191. EFI_STATUS
  192. NorFlashWriteSingleBlock (
  193. IN NOR_FLASH_INSTANCE *Instance,
  194. IN EFI_LBA Lba,
  195. IN UINTN Offset,
  196. IN OUT UINTN *NumBytes,
  197. IN UINT8 *Buffer
  198. );
  199. EFI_STATUS
  200. NorFlashWriteBlocks (
  201. IN NOR_FLASH_INSTANCE *Instance,
  202. IN EFI_LBA Lba,
  203. IN UINTN BufferSizeInBytes,
  204. IN VOID *Buffer
  205. );
  206. EFI_STATUS
  207. NorFlashReadBlocks (
  208. IN NOR_FLASH_INSTANCE *Instance,
  209. IN EFI_LBA Lba,
  210. IN UINTN BufferSizeInBytes,
  211. OUT VOID *Buffer
  212. );
  213. EFI_STATUS
  214. NorFlashRead (
  215. IN NOR_FLASH_INSTANCE *Instance,
  216. IN EFI_LBA Lba,
  217. IN UINTN Offset,
  218. IN UINTN BufferSizeInBytes,
  219. OUT VOID *Buffer
  220. );
  221. EFI_STATUS
  222. NorFlashWrite (
  223. IN NOR_FLASH_INSTANCE *Instance,
  224. IN EFI_LBA Lba,
  225. IN UINTN Offset,
  226. IN OUT UINTN *NumBytes,
  227. IN UINT8 *Buffer
  228. );
  229. EFI_STATUS
  230. NorFlashReset (
  231. IN NOR_FLASH_INSTANCE *Instance
  232. );
  233. EFI_STATUS
  234. NorFlashReadID (
  235. IN NOR_FLASH_INSTANCE *Instance,
  236. OUT UINT8 JedecId[3]
  237. );
  238. typedef struct {
  239. UINTN DeviceBaseAddress; // Start address of the Device Base Address (DBA)
  240. UINTN RegionBaseAddress; // Start address of one single region
  241. UINTN Size;
  242. UINTN BlockSize;
  243. } NOR_FLASH_DESCRIPTION;
  244. EFI_STATUS
  245. NorFlashPlatformGetDevices (
  246. OUT NOR_FLASH_DESCRIPTION **NorFlashDevices,
  247. OUT UINT32 *Count
  248. );
  249. #define SPINOR_SR_WIP BIT0 // Write in progress
  250. #define SPINOR_FSR_READY BIT7 // Flag Status Register: ready
  251. #define SPINOR_OP_WREN 0x06 // Write enable
  252. #define SPINOR_OP_WRDIS 0x04 // Write enable
  253. #define SPINOR_OP_RDSR 0x05 // Read status register
  254. #define SPINOR_OP_WRSR 0x01 // Write status register 1 byte
  255. #define SPINOR_OP_RDSR2 0x3f // Read status register 2
  256. #define SPINOR_OP_WRSR2 0x3e // Write status register 2
  257. #define SPINOR_OP_READ 0x03 // Read data bytes (low frequency)
  258. #define SPINOR_OP_READ_FAST 0x0b // Read data bytes (high frequency)
  259. #define SPINOR_OP_READ_1_1_2 0x3b // Read data bytes (Dual Output SPI)
  260. #define SPINOR_OP_READ_1_2_2 0xbb // Read data bytes (Dual I/O SPI)
  261. #define SPINOR_OP_READ_1_1_4 0x6b // Read data bytes (Quad Output SPI)
  262. #define SPINOR_OP_READ_1_4_4 0xeb // Read data bytes (Quad I/O SPI)
  263. #define SPINOR_OP_PP 0x02 // Page program (up to 256 bytes)
  264. #define SPINOR_OP_PP_1_1_4 0x32 // Quad page program
  265. #define SPINOR_OP_PP_1_4_4 0x38 // Quad page program
  266. #define SPINOR_OP_BE_4K 0x20 // Erase 4KiB block
  267. #define SPINOR_OP_BE_4K_PMC 0xd7 // Erase 4KiB block on PMC chips
  268. #define SPINOR_OP_BE_32K 0x52 // Erase 32KiB block
  269. #define SPINOR_OP_CHIP_ERASE 0xc7 // Erase whole flash chip
  270. #define SPINOR_OP_BE 0xd8 // Block erase (usually 64KiB)
  271. #define SPINOR_OP_RDID 0x9f // Read JEDEC ID
  272. #define SPINOR_OP_RDSFDP 0x5a // Read SFDP
  273. #define SPINOR_OP_RDCR 0x35 // Read configuration register
  274. #define SPINOR_OP_RDFSR 0x70 // Read flag status register
  275. #define SPINOR_OP_READ_4B 0x13 // Read data bytes (low frequency)
  276. #define SPINOR_OP_READ_FAST_4B 0x0c // Read data bytes (high frequency)
  277. #define SPINOR_OP_READ_1_1_2_4B 0x3c // Read data bytes (Dual Output SPI)
  278. #define SPINOR_OP_READ_1_2_2_4B 0xbc // Read data bytes (Dual I/O SPI)
  279. #define SPINOR_OP_READ_1_1_4_4B 0x6c // Read data bytes (Quad Output SPI)
  280. #define SPINOR_OP_READ_1_4_4_4B 0xec // Read data bytes (Quad I/O SPI)
  281. #define SPINOR_OP_PP_4B 0x12 // Page program (up to 256 bytes)
  282. #define SPINOR_OP_PP_1_1_4_4B 0x34 // Quad page program
  283. #define SPINOR_OP_PP_1_4_4_4B 0x3e // Quad page program
  284. #define SPINOR_OP_BE_4K_4B 0x21 // Erase 4KiB block
  285. #define SPINOR_OP_BE_32K_4B 0x5c // Erase 32KiB block
  286. #define SPINOR_OP_BE_4B 0xdc // Block erase (usually 64KiB)
  287. #define SPINOR_OP_RD_ARRAY 0xe8 // Read array
  288. #define SPINOR_OP_RD_NVCFG 0xb5 // Read non-volatile config register
  289. #define SPINOR_OP_RD_VCR 0x85 // Read VCR register
  290. #define SPINOR_OP_RD_EVCR 0x65 // Read EVCR register
  291. #endif /* __NOR_FLASH_DXE_H__ */