SoftStrapFixup.c 5.4 KB

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  1. /** @file
  2. Soft Strap update.
  3. @copyright
  4. Copyright 2018 - 2021 Intel Corporation. <BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #include "PeiBoardInit.h"
  8. #include <Library/UbaSoftStrapUpdateLib.h>
  9. PLATFORM_PCH_SOFTSTRAP_FIXUP_ENTRY TypeBoardPortTemplateSoftStrapTable[] =
  10. {
  11. // SoftStrapNumber, LowBit, BitLength, Value
  12. {3, 1, 1, 0x1 }, // Intel QuickAssist Endpoint 2 (EP[2]) Primary Mux Select
  13. {4, 24, 1, 0x0 }, // 10 GbE MAC Power Gate Control
  14. {15, 4, 2, 0x3 }, // sSATA / PCIe Select for Port 2 (SATA_PCIE_SP2)
  15. {15, 6, 2, 0x1 }, // sSATA / PCIe Select for Port 3 (SATA_PCIE_SP3)
  16. {15, 18, 1, 0x1 }, // Polarity of GPP_H20 (GPIO polarity of Select between sSATA Port 2 and PCIe Port 8)
  17. {16, 4, 2, 0x3 }, // sSATA / PCIe GP Select for Port 2 (SATA_PCIE_GP2)
  18. {16, 6, 2, 0x1 }, // sSATA / PCIe GP Select for Port 3 (SATA_PCIE_GP3)
  19. {17, 6, 1, 0x0 }, // Intel (R) GbE Legacy PHY over PCIe Enabled
  20. {17, 12, 2, 0x3 }, // sSATA / PCIe Combo Port 2
  21. {18, 0, 2, 0x1 }, // sSATA / PCIe Combo Port 3
  22. {18, 6, 2, 0x3 }, // SATA / PCIe Combo Port 0
  23. {18, 8, 2, 0x3 }, // SATA / PCIe Combo Port 1
  24. {18, 10, 2, 0x3 }, // SATA / PCIe Combo Port 2
  25. {18, 12, 2, 0x3 }, // SATA / PCIe Combo Port 3
  26. {18, 14, 2, 0x3 }, // SATA / PCIe Combo Port 4
  27. {19, 2, 1, 0x1 }, // Polarity Select sSATA / PCIe Combo Port 2
  28. {19, 16, 2, 0x3 }, // SATA / PCIe Combo Port 5
  29. {19, 18, 2, 0x3 }, // SATA / PCIe Combo Port 6
  30. {19, 20, 2, 0x3 }, // SATA / PCIe Combo Port 7
  31. {19, 26, 1, 0x1 }, // Statically assign PCH PCIe NP8 Uplink to act as Downlink or Uplink(PCIEUDS)
  32. {33, 24, 7, 0x17}, // IE SMLink1 I2C Target Address
  33. {64, 24, 7, 0x17}, // ME SMLink1 I2C Target Address
  34. {84, 24, 1, 0x0 }, // SMS1 Gbe Legacy MAC SMBus Address Enable
  35. {85, 8, 3, 0x0 }, // SMS1 PMC SMBus Connect
  36. {88, 8, 2, 0x3 }, // Root Port Configuration 0
  37. {93, 0, 2, 0x3 }, // Flex IO Port 18 AUXILLARY Mux Select between SATA Port 0 and PCIe Port 12
  38. {93, 2, 2, 0x3 }, // Flex IO Port 19 AUXILLARY Mux Select between SATA Port 1 and PCIe Port 13
  39. {93, 4, 2, 0x3 }, // Flex IO Port 20 AUXILLARY Mux Select between SATA Port 2 and PCIe Port 14
  40. {94, 0, 2, 0x3 }, // Flex IO Port 21 AUXILLARY Mux Select between SATA Port 3 and PCIe Port 15
  41. {94, 2, 2, 0x3 }, // Flex IO Port 22 AUXILLARY Mux Select between SATA Port 4 and PCIe Port 16
  42. {94, 4, 2, 0x3 }, // Flex IO Port 23 AUXILLARY Mux Select between SATA Port 5 and PCIe Port 17
  43. {94, 6, 2, 0x3 }, // Flex IO Port 24 AUXILLARY Mux Select between SATA Port 6 and PCIe Port 18
  44. {94, 8, 2, 0x3 }, // Flex IO Port 25 AUXILLARY Mux Select between SATA Port 7 and PCIe Port 19
  45. {102, 0, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 0 and PCIe Port 12
  46. {102, 2, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 1 and PCIe Port 13
  47. {102, 4, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 2 and PCIe Port 14
  48. {102, 6, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 3 and PCIe Port 15
  49. {102, 8, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 4 and PCIe Port 16
  50. {102, 10, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 5 and PCIe Port 17
  51. {102, 12, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 6 and PCIe Port 18
  52. {102, 14, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 7 and PCIe Port 19
  53. {103, 16, 3, 0x0 }, // GbE Legacy PHY Smbus Connection
  54. {103, 26, 1, 0x0 }, // GbE Legacy LCD SMBus PHY Address Enabled
  55. {103, 27, 1, 0x0 }, // GbE Legacy LC SMBus Address Enabled
  56. // {133, 1, 1, 0x1 }, // Dual I/O Read Enabled
  57. // {133, 2, 1, 0x1 }, // Quad Output Read Enabled
  58. // {133, 3, 1, 0x1 }, // Quad I/O Read Enabled
  59. // {136, 10, 2, 0x3 }, // eSPI / EC Maximum I/O Mode
  60. // {136, 12, 1, 0x1 }, // Slave 1 (2nd eSPI device) Enable
  61. // {136, 16, 3, 0x4 }, // eSPI / EC Slave 1 Device Bus Frequency
  62. // {136, 19, 2, 0x3 }, // eSPI / EC Slave Device Maximum I/O Mode
  63. //
  64. // END OF LIST
  65. //
  66. {0, 0, 0, 0}
  67. };
  68. UINT32
  69. TypeBoardPortTemplateSystemBoardRevIdValue (VOID)
  70. {
  71. EFI_HOB_GUID_TYPE *GuidHob;
  72. EFI_PLATFORM_INFO *PlatformInfo;
  73. GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
  74. ASSERT(GuidHob != NULL);
  75. if (GuidHob == NULL) {
  76. return 0xFF;
  77. }
  78. PlatformInfo = GET_GUID_HOB_DATA(GuidHob);
  79. return PlatformInfo->TypeRevisionId;
  80. }
  81. VOID
  82. TypeBoardPortTemplatePlatformSpecificUpdate (
  83. IN OUT UINT8 *FlashDescriptorCopy
  84. )
  85. {
  86. }
  87. PLATFORM_PCH_SOFTSTRAP_UPDATE TypeBoardPortTemplateSoftStrapUpdate =
  88. {
  89. PLATFORM_SOFT_STRAP_UPDATE_SIGNATURE,
  90. PLATFORM_SOFT_STRAP_UPDATE_VERSION,
  91. TypeBoardPortTemplateSoftStrapTable,
  92. TypeBoardPortTemplatePlatformSpecificUpdate
  93. };
  94. EFI_STATUS
  95. TypeBoardPortTemplateInstallSoftStrapData (
  96. IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
  97. )
  98. {
  99. EFI_STATUS Status;
  100. Status = UbaConfigPpi->AddData (
  101. UbaConfigPpi,
  102. &gPlatformPchSoftStrapConfigDataGuid,
  103. &TypeBoardPortTemplateSoftStrapUpdate,
  104. sizeof(TypeBoardPortTemplateSoftStrapUpdate)
  105. );
  106. return Status;
  107. }