OpenBoardPkg.fdf 27 KB

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  1. ## @file
  2. # FDF file for the UpXtreme.
  3. #
  4. #
  5. # Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
  6. #
  7. # SPDX-License-Identifier: BSD-2-Clause-Patent
  8. #
  9. #
  10. ##
  11. [Defines]
  12. !include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf
  13. ################################################################################
  14. #
  15. # FD Section
  16. # The [FD] Section is made up of the definition statements and a
  17. # description of what goes into the Flash Device Image. Each FD section
  18. # defines one flash "device" image. A flash device image may be one of
  19. # the following: Removable media bootable image (like a boot floppy
  20. # image,) an Option ROM image (that would be "flashed" into an add-in
  21. # card,) a System "Flash" image (that would be burned into a system's
  22. # flash) or an Update ("Capsule") image that will be used to update and
  23. # existing system flash.
  24. #
  25. ################################################################################
  26. [FD.UpXtreme]
  27. #
  28. # FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks, cannot be
  29. # assigned with PCD values. Instead, it uses the definitions for its variety, which
  30. # are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS.
  31. #
  32. BaseAddress = $(FLASH_BASE) | gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress #The base address of the FLASH Device.
  33. Size = $(FLASH_SIZE) | gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize #The size in bytes of the FLASH Device
  34. ErasePolarity = 1
  35. BlockSize = $(FLASH_BLOCK_SIZE)
  36. NumBlocks = $(FLASH_NUM_BLOCKS)
  37. DEFINE SIPKG_DXE_SMM_BIN = INF
  38. DEFINE SIPKG_PEI_BIN = INF
  39. # Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macro expression is not supported.
  40. # So, PlatformSecLib uses PcdBiosAreaBaseAddress + PcdNemCodeCacheBase to get the real CodeCache base address.
  41. SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase = $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset)
  42. SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset)
  43. SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = $(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize)
  44. SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = $(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase) + 0x60
  45. SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = $(gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize) - 0x60
  46. SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x60
  47. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase
  48. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
  49. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset
  50. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress = gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
  51. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize = gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize
  52. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset)
  53. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset)
  54. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = $(gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset)
  55. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = gIntelSiliconPkgTokenSpaceGuid.PcdBiosAreaBaseAddress
  56. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = gIntelSiliconPkgTokenSpaceGuid.PcdBiosSize
  57. ################################################################################
  58. #
  59. # Following are lists of FD Region layout which correspond to the locations of different
  60. # images within the flash device.
  61. #
  62. # Regions must be defined in ascending order and may not overlap.
  63. #
  64. # A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
  65. # the pipe "|" character, followed by the size of the region, also in hex with the leading
  66. # "0x" characters. Like:
  67. # Offset|Size
  68. # PcdOffsetCName|PcdSizeCName
  69. # RegionType <FV, DATA, or FILE>
  70. # Fv Size can be adjusted
  71. #
  72. ################################################################################
  73. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  74. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  75. #NV_VARIABLE_STORE
  76. DATA = {
  77. ## This is the EFI_FIRMWARE_VOLUME_HEADER
  78. # ZeroVector []
  79. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  80. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  81. # FileSystemGuid
  82. 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
  83. 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
  84. # FvLength: 0x40000
  85. 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
  86. #Signature "_FVH" #Attributes
  87. 0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00,
  88. #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
  89. #
  90. # Be careful on CheckSum field.
  91. #
  92. 0x48, 0x00, 0x32, 0x09, 0x00, 0x00, 0x00, 0x02,
  93. #Blockmap[0]: 4 Blocks 0x10000 Bytes / Block
  94. 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
  95. #Blockmap[1]: End
  96. 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  97. ## This is the VARIABLE_STORE_HEADER
  98. !if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE
  99. # Signature: gEfiAuthenticatedVariableGuid = { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
  100. 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
  101. 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
  102. !else
  103. # Signature: gEfiVariableGuid = { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
  104. 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
  105. 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
  106. !endif
  107. #Size: 0x1E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0x1DFB8
  108. # This can speed up the Variable Dispatch a bit.
  109. 0xB8, 0xDF, 0x01, 0x00,
  110. #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
  111. 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  112. }
  113. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  114. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  115. #NV_FTW_WORKING
  116. DATA = {
  117. # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid =
  118. # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95 }}
  119. 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,
  120. 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,
  121. # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
  122. 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
  123. # WriteQueueSize: UINT64
  124. 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
  125. }
  126. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
  127. gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
  128. #NV_FTW_SPARE
  129. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  130. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  131. FV = FvAdvanced
  132. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  133. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  134. FV = FvSecurity
  135. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  136. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  137. FV = FvOsBoot
  138. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
  139. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
  140. FV = FvUefiBoot
  141. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  142. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  143. FV = FvPostMemory
  144. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  145. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  146. # FSP_S Section
  147. FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd
  148. gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
  149. gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize
  150. #Microcode
  151. FV = FvMicrocode
  152. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  153. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  154. # FSP_M Section
  155. FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd
  156. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  157. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  158. # FSP_T Section
  159. FILE = $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd
  160. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize
  161. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedPreMemorySize
  162. FV = FvAdvancedPreMemory
  163. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
  164. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
  165. FV = FvPreMemory
  166. ################################################################################
  167. #
  168. # FV Section
  169. #
  170. # [FV] section is used to define what components or modules are placed within a flash
  171. # device file. This section also defines order the components and modules are positioned
  172. # within the image. The [FV] section consists of define statements, set statements and
  173. # module statements.
  174. #
  175. ################################################################################
  176. [FV.FvMicrocode]
  177. BlockSize = $(FLASH_BLOCK_SIZE)
  178. FvAlignment = 16
  179. ERASE_POLARITY = 1
  180. MEMORY_MAPPED = TRUE
  181. STICKY_WRITE = TRUE
  182. LOCK_CAP = TRUE
  183. LOCK_STATUS = FALSE
  184. WRITE_DISABLED_CAP = TRUE
  185. WRITE_ENABLED_CAP = TRUE
  186. WRITE_STATUS = TRUE
  187. WRITE_LOCK_CAP = TRUE
  188. WRITE_LOCK_STATUS = TRUE
  189. READ_DISABLED_CAP = TRUE
  190. READ_ENABLED_CAP = TRUE
  191. READ_STATUS = FALSE
  192. READ_LOCK_CAP = TRUE
  193. READ_LOCK_STATUS = TRUE
  194. FILE RAW = 197DB236-F856-4924-90F8-CDF12FB875F3 {
  195. $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/X64/MicrocodeUpdates.bin
  196. }
  197. [FV.FvPreMemory]
  198. BlockSize = $(FLASH_BLOCK_SIZE)
  199. FvAlignment = 16
  200. ERASE_POLARITY = 1
  201. MEMORY_MAPPED = TRUE
  202. STICKY_WRITE = TRUE
  203. LOCK_CAP = TRUE
  204. LOCK_STATUS = TRUE
  205. WRITE_DISABLED_CAP = TRUE
  206. WRITE_ENABLED_CAP = TRUE
  207. WRITE_STATUS = TRUE
  208. WRITE_LOCK_CAP = TRUE
  209. WRITE_LOCK_STATUS = TRUE
  210. READ_DISABLED_CAP = TRUE
  211. READ_ENABLED_CAP = TRUE
  212. READ_STATUS = TRUE
  213. READ_LOCK_CAP = TRUE
  214. READ_LOCK_STATUS = TRUE
  215. FvNameGuid = FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D
  216. INF UefiCpuPkg/SecCore/SecCore.inf
  217. INF MdeModulePkg/Core/Pei/PeiMain.inf
  218. !include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf
  219. INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf
  220. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
  221. INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
  222. INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
  223. INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf
  224. [FV.FvPostMemoryUncompact]
  225. BlockSize = $(FLASH_BLOCK_SIZE)
  226. FvAlignment = 16
  227. ERASE_POLARITY = 1
  228. MEMORY_MAPPED = TRUE
  229. STICKY_WRITE = TRUE
  230. LOCK_CAP = TRUE
  231. LOCK_STATUS = TRUE
  232. WRITE_DISABLED_CAP = TRUE
  233. WRITE_ENABLED_CAP = TRUE
  234. WRITE_STATUS = TRUE
  235. WRITE_LOCK_CAP = TRUE
  236. WRITE_LOCK_STATUS = TRUE
  237. READ_DISABLED_CAP = TRUE
  238. READ_ENABLED_CAP = TRUE
  239. READ_STATUS = TRUE
  240. READ_LOCK_CAP = TRUE
  241. READ_LOCK_STATUS = TRUE
  242. FvNameGuid = 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7
  243. !include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf
  244. # Init Board Config PCD
  245. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
  246. INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
  247. INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMem.inf
  248. FILE RAW = C9505BC0-AA3D-4056-9995-870C8DE8594E {
  249. $(PLATFORM_SI_BIN_PACKAGE)/ChipsetInit/CnlPchLpChipsetInitTable_Dx.bin
  250. }
  251. !if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable == TRUE
  252. FILE FREEFORM =PCD(gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid) {
  253. SECTION RAW = $(PLATFORM_FSP_BIN_PACKAGE)/SampleCode/Vbt/Vbt.bin
  254. SECTION UI = "Vbt"
  255. }
  256. FILE FREEFORM = 7BB28B99-61BB-11D5-9A5D-0090273FC14D {
  257. SECTION RAW = MdeModulePkg/Logo/Logo.bmp
  258. }
  259. !endif # PcdPeiDisplayEnable
  260. [FV.FvPostMemory]
  261. BlockSize = $(FLASH_BLOCK_SIZE)
  262. FvAlignment = 16
  263. ERASE_POLARITY = 1
  264. MEMORY_MAPPED = TRUE
  265. STICKY_WRITE = TRUE
  266. LOCK_CAP = TRUE
  267. LOCK_STATUS = TRUE
  268. WRITE_DISABLED_CAP = TRUE
  269. WRITE_ENABLED_CAP = TRUE
  270. WRITE_STATUS = TRUE
  271. WRITE_LOCK_CAP = TRUE
  272. WRITE_LOCK_STATUS = TRUE
  273. READ_DISABLED_CAP = TRUE
  274. READ_ENABLED_CAP = TRUE
  275. READ_STATUS = TRUE
  276. READ_LOCK_CAP = TRUE
  277. READ_LOCK_STATUS = TRUE
  278. FvNameGuid = 9DFE49DB-8EF0-4D9C-B273-0036144DE917
  279. FILE FV_IMAGE = 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 {
  280. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  281. SECTION FV_IMAGE = FvPostMemoryUncompact
  282. }
  283. }
  284. [FV.FvUefiBootUncompact]
  285. BlockSize = $(FLASH_BLOCK_SIZE)
  286. FvAlignment = 16
  287. ERASE_POLARITY = 1
  288. MEMORY_MAPPED = TRUE
  289. STICKY_WRITE = TRUE
  290. LOCK_CAP = TRUE
  291. LOCK_STATUS = TRUE
  292. WRITE_DISABLED_CAP = TRUE
  293. WRITE_ENABLED_CAP = TRUE
  294. WRITE_STATUS = TRUE
  295. WRITE_LOCK_CAP = TRUE
  296. WRITE_LOCK_STATUS = TRUE
  297. READ_DISABLED_CAP = TRUE
  298. READ_ENABLED_CAP = TRUE
  299. READ_STATUS = TRUE
  300. READ_LOCK_CAP = TRUE
  301. READ_LOCK_STATUS = TRUE
  302. FvNameGuid = A881D567-6CB0-4eee-8435-2E72D33E45B5
  303. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf
  304. INF $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxeCnl.inf
  305. INF UefiCpuPkg/CpuDxe/CpuDxe.inf
  306. INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
  307. INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
  308. INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
  309. INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
  310. INF MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf
  311. INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
  312. INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
  313. INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
  314. #
  315. # eMMC/SD Card
  316. #
  317. INF MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.inf
  318. INF MdeModulePkg/Bus/Sd/EmmcDxe/EmmcDxe.inf
  319. INF MdeModulePkg/Bus/Sd/SdDxe/SdDxe.inf
  320. INF ShellPkg/Application/Shell/Shell.inf
  321. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
  322. INF $(PLATFORM_BOARD_PACKAGE)/Policy/PolicyInitDxe/PolicyInitDxe.inf
  323. INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf
  324. INF IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf
  325. INF $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf
  326. [FV.FvUefiBoot]
  327. BlockSize = $(FLASH_BLOCK_SIZE)
  328. FvAlignment = 16
  329. ERASE_POLARITY = 1
  330. MEMORY_MAPPED = TRUE
  331. STICKY_WRITE = TRUE
  332. LOCK_CAP = TRUE
  333. LOCK_STATUS = TRUE
  334. WRITE_DISABLED_CAP = TRUE
  335. WRITE_ENABLED_CAP = TRUE
  336. WRITE_STATUS = TRUE
  337. WRITE_LOCK_CAP = TRUE
  338. WRITE_LOCK_STATUS = TRUE
  339. READ_DISABLED_CAP = TRUE
  340. READ_ENABLED_CAP = TRUE
  341. READ_STATUS = TRUE
  342. READ_LOCK_CAP = TRUE
  343. READ_LOCK_STATUS = TRUE
  344. FvNameGuid = 0496D33D-EA79-495C-B65D-ABF607184E3B
  345. FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
  346. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  347. SECTION FV_IMAGE = FvUefiBootUncompact
  348. }
  349. }
  350. [FV.FvOsBootUncompact]
  351. BlockSize = $(FLASH_BLOCK_SIZE)
  352. FvAlignment = 16
  353. ERASE_POLARITY = 1
  354. MEMORY_MAPPED = TRUE
  355. STICKY_WRITE = TRUE
  356. LOCK_CAP = TRUE
  357. LOCK_STATUS = TRUE
  358. WRITE_DISABLED_CAP = TRUE
  359. WRITE_ENABLED_CAP = TRUE
  360. WRITE_STATUS = TRUE
  361. WRITE_LOCK_CAP = TRUE
  362. WRITE_LOCK_STATUS = TRUE
  363. READ_DISABLED_CAP = TRUE
  364. READ_ENABLED_CAP = TRUE
  365. READ_STATUS = TRUE
  366. READ_LOCK_CAP = TRUE
  367. READ_LOCK_STATUS = TRUE
  368. FvNameGuid = A0F04529-B715-44C6-BCA4-2DEBDD01EEEC
  369. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf
  370. !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
  371. INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf
  372. INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf
  373. INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf
  374. INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf
  375. INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf
  376. INF RuleOverride = DRIVER_ACPITABLE $(PLATFORM_BOARD_PACKAGE)/Acpi/BoardAcpiDxe/BoardAcpiDxe.inf
  377. INF $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
  378. !endif
  379. [FV.FvLateSilicon]
  380. BlockSize = $(FLASH_BLOCK_SIZE)
  381. FvAlignment = 16
  382. ERASE_POLARITY = 1
  383. MEMORY_MAPPED = TRUE
  384. STICKY_WRITE = TRUE
  385. LOCK_CAP = TRUE
  386. LOCK_STATUS = TRUE
  387. WRITE_DISABLED_CAP = TRUE
  388. WRITE_ENABLED_CAP = TRUE
  389. WRITE_STATUS = TRUE
  390. WRITE_LOCK_CAP = TRUE
  391. WRITE_LOCK_STATUS = TRUE
  392. READ_DISABLED_CAP = TRUE
  393. READ_ENABLED_CAP = TRUE
  394. READ_STATUS = TRUE
  395. READ_LOCK_CAP = TRUE
  396. READ_LOCK_STATUS = TRUE
  397. FvNameGuid = 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E
  398. !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
  399. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf
  400. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SmmAccess/Dxe/SmmAccess.inf
  401. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf
  402. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf
  403. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/Spi/Smm/PchSpiSmm.inf
  404. $(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf
  405. INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaAcpiTables.inf
  406. INF RuleOverride = ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf
  407. !endif
  408. [FV.FvOsBoot]
  409. BlockSize = $(FLASH_BLOCK_SIZE)
  410. FvAlignment = 16
  411. ERASE_POLARITY = 1
  412. MEMORY_MAPPED = TRUE
  413. STICKY_WRITE = TRUE
  414. LOCK_CAP = TRUE
  415. LOCK_STATUS = TRUE
  416. WRITE_DISABLED_CAP = TRUE
  417. WRITE_ENABLED_CAP = TRUE
  418. WRITE_STATUS = TRUE
  419. WRITE_LOCK_CAP = TRUE
  420. WRITE_LOCK_STATUS = TRUE
  421. READ_DISABLED_CAP = TRUE
  422. READ_ENABLED_CAP = TRUE
  423. READ_STATUS = TRUE
  424. READ_LOCK_CAP = TRUE
  425. READ_LOCK_STATUS = TRUE
  426. FvNameGuid = 13BF8810-75FD-4B1A-91E6-E16C4201F80A
  427. FILE FV_IMAGE = B9020753-84A8-4BB6-947C-CE7D41F5CE39 {
  428. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  429. SECTION FV_IMAGE = FvOsBootUncompact
  430. }
  431. }
  432. FILE FV_IMAGE = D4632741-510C-44E3-BE21-C3D6D7881485 {
  433. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  434. SECTION FV_IMAGE = FvLateSilicon
  435. }
  436. }
  437. [FV.FvSecurityPreMemory]
  438. BlockSize = $(FLASH_BLOCK_SIZE)
  439. FvAlignment = 16 #FV alignment and FV attributes setting.
  440. ERASE_POLARITY = 1
  441. MEMORY_MAPPED = TRUE
  442. STICKY_WRITE = TRUE
  443. LOCK_CAP = TRUE
  444. LOCK_STATUS = TRUE
  445. WRITE_DISABLED_CAP = TRUE
  446. WRITE_ENABLED_CAP = TRUE
  447. WRITE_STATUS = TRUE
  448. WRITE_LOCK_CAP = TRUE
  449. WRITE_LOCK_STATUS = TRUE
  450. READ_DISABLED_CAP = TRUE
  451. READ_ENABLED_CAP = TRUE
  452. READ_STATUS = TRUE
  453. READ_LOCK_CAP = TRUE
  454. READ_LOCK_STATUS = TRUE
  455. FvNameGuid = 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B
  456. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
  457. INF IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamplePei.inf
  458. INF IntelSiliconPkg/Feature/VTd/IntelVTdPmrPei/IntelVTdPmrPei.inf
  459. [FV.FvSecurityPostMemory]
  460. BlockSize = $(FLASH_BLOCK_SIZE)
  461. FvAlignment = 16 #FV alignment and FV attributes setting.
  462. ERASE_POLARITY = 1
  463. MEMORY_MAPPED = TRUE
  464. STICKY_WRITE = TRUE
  465. LOCK_CAP = TRUE
  466. LOCK_STATUS = TRUE
  467. WRITE_DISABLED_CAP = TRUE
  468. WRITE_ENABLED_CAP = TRUE
  469. WRITE_STATUS = TRUE
  470. WRITE_LOCK_CAP = TRUE
  471. WRITE_LOCK_STATUS = TRUE
  472. READ_DISABLED_CAP = TRUE
  473. READ_ENABLED_CAP = TRUE
  474. READ_STATUS = TRUE
  475. READ_LOCK_CAP = TRUE
  476. READ_LOCK_STATUS = TRUE
  477. FvNameGuid = 4199E560-54AE-45E5-91A4-F7BC3804E14A
  478. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf
  479. !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
  480. INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf
  481. !endif
  482. [FV.FvSecurityLate]
  483. BlockSize = $(FLASH_BLOCK_SIZE)
  484. FvAlignment = 16
  485. ERASE_POLARITY = 1
  486. MEMORY_MAPPED = TRUE
  487. STICKY_WRITE = TRUE
  488. LOCK_CAP = TRUE
  489. LOCK_STATUS = TRUE
  490. WRITE_DISABLED_CAP = TRUE
  491. WRITE_ENABLED_CAP = TRUE
  492. WRITE_STATUS = TRUE
  493. WRITE_LOCK_CAP = TRUE
  494. WRITE_LOCK_STATUS = TRUE
  495. READ_DISABLED_CAP = TRUE
  496. READ_ENABLED_CAP = TRUE
  497. READ_STATUS = TRUE
  498. READ_LOCK_CAP = TRUE
  499. READ_LOCK_STATUS = TRUE
  500. FvNameGuid = F753FE9A-EEFD-485B-840B-E032D538102C
  501. !include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf
  502. INF IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.inf
  503. !if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly == FALSE
  504. INF $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf
  505. !if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable == TRUE
  506. INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf
  507. !endif
  508. !endif
  509. [FV.FvSecurity]
  510. BlockSize = $(FLASH_BLOCK_SIZE)
  511. FvAlignment = 16
  512. ERASE_POLARITY = 1
  513. MEMORY_MAPPED = TRUE
  514. STICKY_WRITE = TRUE
  515. LOCK_CAP = TRUE
  516. LOCK_STATUS = TRUE
  517. WRITE_DISABLED_CAP = TRUE
  518. WRITE_ENABLED_CAP = TRUE
  519. WRITE_STATUS = TRUE
  520. WRITE_LOCK_CAP = TRUE
  521. WRITE_LOCK_STATUS = TRUE
  522. READ_DISABLED_CAP = TRUE
  523. READ_ENABLED_CAP = TRUE
  524. READ_STATUS = TRUE
  525. READ_LOCK_CAP = TRUE
  526. READ_LOCK_STATUS = TRUE
  527. FvNameGuid = 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF
  528. FILE FV_IMAGE = 757CC075-1428-423D-A73C-22639706C119 {
  529. SECTION FV_IMAGE = FvSecurityPreMemory
  530. }
  531. FILE FV_IMAGE = 80BB8482-44D5-4BEC-82B5-8D87A933830B {
  532. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  533. SECTION FV_IMAGE = FvSecurityPostMemory
  534. }
  535. }
  536. FILE FV_IMAGE = C83522D9-80A1-4D95-8C25-3F1370497406 {
  537. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  538. SECTION FV_IMAGE = FvSecurityLate
  539. }
  540. }
  541. #
  542. # Pre-memory Advanced Features
  543. #
  544. [FV.FvAdvancedPreMemory]
  545. FvAlignment = 16
  546. ERASE_POLARITY = 1
  547. MEMORY_MAPPED = TRUE
  548. STICKY_WRITE = TRUE
  549. LOCK_CAP = TRUE
  550. LOCK_STATUS = TRUE
  551. WRITE_DISABLED_CAP = TRUE
  552. WRITE_ENABLED_CAP = TRUE
  553. WRITE_STATUS = TRUE
  554. WRITE_LOCK_CAP = TRUE
  555. WRITE_LOCK_STATUS = TRUE
  556. READ_DISABLED_CAP = TRUE
  557. READ_ENABLED_CAP = TRUE
  558. READ_STATUS = TRUE
  559. READ_LOCK_CAP = TRUE
  560. READ_LOCK_STATUS = TRUE
  561. FvNameGuid = 6053D78A-457E-4490-A237-31D0FBE2F305
  562. !include AdvancedFeaturePkg/Include/PreMemory.fdf
  563. !if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
  564. INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Pei/PeiTbtInit.inf
  565. !endif
  566. #
  567. # Post-Memory Advanced Features
  568. #
  569. [FV.FvAdvancedUncompact]
  570. FvAlignment = 16
  571. ERASE_POLARITY = 1
  572. MEMORY_MAPPED = TRUE
  573. STICKY_WRITE = TRUE
  574. LOCK_CAP = TRUE
  575. LOCK_STATUS = TRUE
  576. WRITE_DISABLED_CAP = TRUE
  577. WRITE_ENABLED_CAP = TRUE
  578. WRITE_STATUS = TRUE
  579. WRITE_LOCK_CAP = TRUE
  580. WRITE_LOCK_STATUS = TRUE
  581. READ_DISABLED_CAP = TRUE
  582. READ_ENABLED_CAP = TRUE
  583. READ_STATUS = TRUE
  584. READ_LOCK_CAP = TRUE
  585. READ_LOCK_STATUS = TRUE
  586. FvNameGuid = BE3DF86F-E464-44A3-83F7-0D27E6B88C27
  587. !include AdvancedFeaturePkg/Include/PostMemory.fdf
  588. !if gWhiskeylakeOpenBoardPkgTokenSpaceGuid.PcdTbtEnable == TRUE
  589. INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Dxe/TbtDxe.inf
  590. INF $(PLATFORM_BOARD_PACKAGE)/Features/PciHotPlug/PciHotPlug.inf
  591. INF $(PLATFORM_BOARD_PACKAGE)/Features/Tbt/TbtInit/Smm/TbtSmm.inf
  592. !endif
  593. #
  594. # Compressed FV with Post-Memory Advanced Features
  595. #
  596. [FV.FvAdvanced]
  597. BlockSize = $(FLASH_BLOCK_SIZE)
  598. FvAlignment = 16
  599. ERASE_POLARITY = 1
  600. MEMORY_MAPPED = TRUE
  601. STICKY_WRITE = TRUE
  602. LOCK_CAP = TRUE
  603. LOCK_STATUS = TRUE
  604. WRITE_DISABLED_CAP = TRUE
  605. WRITE_ENABLED_CAP = TRUE
  606. WRITE_STATUS = TRUE
  607. WRITE_LOCK_CAP = TRUE
  608. WRITE_LOCK_STATUS = TRUE
  609. READ_DISABLED_CAP = TRUE
  610. READ_ENABLED_CAP = TRUE
  611. READ_STATUS = TRUE
  612. READ_LOCK_CAP = TRUE
  613. READ_LOCK_STATUS = TRUE
  614. FvNameGuid = B23E7388-9953-45C7-9201-0473DDE5487A
  615. FILE FV_IMAGE = 5248467B-B87B-4E74-AC02-398AF4BCB712 {
  616. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  617. SECTION FV_IMAGE = FvAdvancedUncompact
  618. }
  619. }
  620. ################################################################################
  621. #
  622. # Rules are use with the [FV] section's module INF type to define
  623. # how an FFS file is created for a given INF file. The following Rule are the default
  624. # rules for the different module type. User can add the customized rules to define the
  625. # content of the FFS file.
  626. #
  627. ################################################################################
  628. !include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf