OpenBoardPkgPcd.dsc 16 KB

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  1. ## @file
  2. # PCD configuration build description file for the TigerlakeURvp board.
  3. #
  4. # Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
  5. # SPDX-License-Identifier: BSD-2-Clause-Patent
  6. #
  7. ##
  8. ################################################################################
  9. #
  10. # Pcd Section - list of all PCD Entries used by this board.
  11. #
  12. ################################################################################
  13. [PcdsFixedAtBuild.common]
  14. ######################################
  15. # Key Boot Stage and FSP configuration
  16. ######################################
  17. #
  18. # Please select the Boot Stage here.
  19. # Stage 1 - enable debug (system deadloop after debug init)
  20. # Stage 2 - mem init (system deadloop after mem init)
  21. # Stage 3 - boot to shell only
  22. # Stage 4 - boot to OS
  23. # Stage 5 - boot to OS with security boot enabled
  24. # Stage 6 - boot with advanced features enabled
  25. #
  26. gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4
  27. #
  28. # 0: FSP Wrapper is running in Dispatch mode.
  29. # 1: FSP Wrapper is running in API mode.
  30. #
  31. gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0
  32. #
  33. # FALSE: The board is not a FSP wrapper (FSP binary not used)
  34. # TRUE: The board is a FSP wrapper (FSP binary is used)
  35. #
  36. gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
  37. #
  38. # FSP Base address PCD will be updated in FDF basing on flash map.
  39. #
  40. gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
  41. gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
  42. gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000
  43. gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00080000
  44. gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000
  45. gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000
  46. gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000
  47. #
  48. # PCD declared for TigerlakeSiliconPkg Fru
  49. #
  50. gSiPkgTokenSpaceGuid.PcdBiosGuardEnable|FALSE
  51. gSiPkgTokenSpaceGuid.PcdCpuPcieEnable|TRUE
  52. gSiPkgTokenSpaceGuid.PcdEmbeddedEnable|0x0
  53. gSiPkgTokenSpaceGuid.PcdThcEnable|TRUE
  54. gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported|TRUE
  55. ######################################
  56. # Silicon Configuration
  57. ######################################
  58. # Build switches
  59. gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE
  60. # CPU
  61. gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE
  62. # SA
  63. gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE
  64. gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE
  65. gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE
  66. gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE
  67. gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE
  68. # ME
  69. gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE
  70. gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE
  71. gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE
  72. # Others
  73. gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE
  74. gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE
  75. gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE
  76. gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE
  77. gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE
  78. gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE
  79. gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE
  80. gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE
  81. gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE
  82. gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE
  83. gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE
  84. gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE
  85. gSiPkgTokenSpaceGuid.PcdFspWrapperEnable|TRUE
  86. #
  87. # When sharing stack with boot loader, FSP only needs a small temp ram for heap
  88. #
  89. !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
  90. gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x00020000
  91. !else
  92. #
  93. # FSP Dispatch mode will not establish separate Stack or Heap.
  94. #
  95. gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0
  96. !endif
  97. #
  98. # Boot loader stack size has to be large enough for FSP execution
  99. #
  100. gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x30000
  101. gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xC0000000
  102. #!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
  103. gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
  104. #!endif
  105. gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x40000
  106. [PcdsFeatureFlag.common]
  107. ######################################
  108. # Edk2 Configuration
  109. ######################################
  110. gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst|FALSE
  111. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE
  112. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE
  113. gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
  114. ######################################
  115. # Platform Configuration
  116. ######################################
  117. gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
  118. gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
  119. gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
  120. gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE
  121. gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE
  122. gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE
  123. gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable|TRUE
  124. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 1
  125. gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE
  126. !endif
  127. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 2
  128. gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE
  129. gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE
  130. !endif
  131. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 3
  132. gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE
  133. gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE
  134. !endif
  135. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 4
  136. gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE
  137. !endif
  138. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 5
  139. gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE
  140. gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE
  141. !endif
  142. !if $(TARGET) == DEBUG
  143. gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
  144. !else
  145. gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE
  146. !endif
  147. ######################################
  148. # Board Configuration
  149. ######################################
  150. gBoardModuleTokenSpaceGuid.PcdIntelGopEnable|TRUE
  151. [PcdsFixedAtBuild.common]
  152. ######################################
  153. # Edk2 Configuration
  154. ######################################
  155. !if $(TARGET) == RELEASE
  156. gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
  157. gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3
  158. !else
  159. gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F
  160. gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
  161. !endif
  162. !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
  163. gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
  164. !endif
  165. gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE
  166. !if $(TARGET) == RELEASE
  167. gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
  168. !else
  169. gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
  170. !endif
  171. gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE
  172. gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01
  173. gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0
  174. gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800
  175. gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEMORY_ADDRESS)
  176. gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400
  177. !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
  178. gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
  179. !endif
  180. gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000
  181. gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE
  182. !if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable == TRUE
  183. gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1
  184. !endif
  185. gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
  186. !if $(TARGET) == DEBUG
  187. gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE
  188. !endif
  189. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80
  190. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00
  191. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0
  192. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F
  193. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44
  194. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2
  195. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800
  196. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC
  197. gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08
  198. # Specifies timeout value in microseconds for the BSP to detect all APs for the first time.
  199. gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000
  200. gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x0
  201. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
  202. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000
  203. #
  204. # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBuild
  205. # (They will be DynamicEx in FSP Dispatch mode)
  206. #
  207. ## Specifies the size of the microcode Region.
  208. # @Prompt Microcode Region size.
  209. gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0
  210. ## Specifies the AP wait loop state during POST phase.
  211. # The value is defined as below.
  212. # 1: Place AP in the Hlt-Loop state.
  213. # 2: Place AP in the Mwait-Loop state.
  214. # 3: Place AP in the Run-Loop state.
  215. # @Prompt The AP wait loop state.
  216. gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2
  217. ######################################
  218. # Platform Configuration
  219. ######################################
  220. gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1
  221. gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8
  222. gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2
  223. gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase|0xA0000000
  224. gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit|0xDFFFFFFF
  225. #
  226. # The PCDs are used to control the Windows SMM Security Mitigations Table - Protection Flags
  227. #
  228. # BIT0: If set, expresses that for all synchronous SMM entries,SMM will validate that input and output buffers lie entirely within the expected fixed memory regions.
  229. # BIT1: If set, expresses that for all synchronous SMM entries, SMM will validate that input and output pointers embedded within the fixed communication buffer only refer to address ranges \
  230. # that lie entirely within the expected fixed memory regions.
  231. # BIT2: Firmware setting this bit is an indication that it will not allow reconfiguration of system resources via non-architectural mechanisms.
  232. # BIT3-31: Reserved
  233. #
  234. gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
  235. gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0xCC
  236. gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0xA2
  237. gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x3100
  238. gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x2A
  239. gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xC4
  240. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 1
  241. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  242. !endif
  243. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 2
  244. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  245. !endif
  246. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 3
  247. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  248. !endif
  249. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 4
  250. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07, 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  251. !endif
  252. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage == 5
  253. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  254. !endif
  255. !if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >= 6
  256. gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F, 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
  257. !endif
  258. [PcdsFixedAtBuild.IA32]
  259. ######################################
  260. # Edk2 Configuration
  261. ######################################
  262. gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0
  263. gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148
  264. gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000
  265. ######################################
  266. # Platform Configuration
  267. ######################################
  268. gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000
  269. [PcdsFixedAtBuild.X64]
  270. ######################################
  271. # Edk2 Configuration
  272. ######################################
  273. # Default platform supported RFC 4646 languages: (American) English
  274. gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US"
  275. [PcdsPatchableInModule.common]
  276. ######################################
  277. # Edk2 Configuration
  278. ######################################
  279. gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0301
  280. gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046
  281. ######################################
  282. # Silicon Configuration
  283. ######################################
  284. !if $(TARGET) == DEBUG
  285. gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1
  286. !endif
  287. [PcdsDynamicDefault]
  288. ######################################
  289. # Edk2 Configuration
  290. ######################################
  291. gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE
  292. gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE
  293. ######################################
  294. # Silicon Configuration
  295. ######################################
  296. !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 1
  297. gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
  298. !endif
  299. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0
  300. gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0
  301. #gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
  302. #
  303. # Set video to native resolution as Windows 8 WHCK requirement.
  304. #
  305. gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0
  306. gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0
  307. gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum|0x00
  308. #
  309. # FSP Base address PCD will be updated in FDF basing on flash map.
  310. #
  311. gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0
  312. # Platform will pre-allocate UPD buffer and pass it to FspWrapper
  313. # Those dummy address will be patched before FspWrapper executing
  314. gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x0
  315. gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x0
  316. gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0
  317. gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16
  318. [PcdsDynamicHii.X64.DEFAULT]
  319. ######################################
  320. # Edk2 Configuration
  321. ######################################
  322. gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
  323. !if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable == TRUE
  324. gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"Timeout"
  325. !else
  326. gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
  327. !endif
  328. [PcdsDynamicExDefault]
  329. gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
  330. !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection == 0
  331. #
  332. # Include FSP PCD settings.
  333. #
  334. !include $(PLATFORM_FSP_BIN_PACKAGE)/TigerLakeFspPcds.dsc
  335. !endif