fu540-c000.dtsi 7.4 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /* Copyright (c) 2018-2019 SiFive, Inc */
  3. /dts-v1/;
  4. /*#include <dt-bindings/clock/sifive-fu540-prci.h>*/
  5. #include "sifive-fu540-prci.h"
  6. / {
  7. #address-cells = <2>;
  8. #size-cells = <2>;
  9. compatible = "sifive,fu540-c000", "sifive,fu540";
  10. aliases {
  11. serial0 = &uart0;
  12. serial1 = &uart1;
  13. ethernet0 = &eth0;
  14. };
  15. chosen {
  16. };
  17. cpus {
  18. #address-cells = <1>;
  19. #size-cells = <0>;
  20. cpu0: cpu@0 {
  21. compatible = "sifive,e51", "sifive,rocket0", "riscv";
  22. device_type = "cpu";
  23. i-cache-block-size = <64>;
  24. i-cache-sets = <128>;
  25. i-cache-size = <16384>;
  26. reg = <0>;
  27. riscv,isa = "rv64imac";
  28. status = "disabled";
  29. cpu0_intc: interrupt-controller {
  30. #interrupt-cells = <1>;
  31. compatible = "riscv,cpu-intc";
  32. interrupt-controller;
  33. };
  34. };
  35. cpu1: cpu@1 {
  36. compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  37. d-cache-block-size = <64>;
  38. d-cache-sets = <64>;
  39. d-cache-size = <32768>;
  40. d-tlb-sets = <1>;
  41. d-tlb-size = <32>;
  42. device_type = "cpu";
  43. i-cache-block-size = <64>;
  44. i-cache-sets = <64>;
  45. i-cache-size = <32768>;
  46. i-tlb-sets = <1>;
  47. i-tlb-size = <32>;
  48. mmu-type = "riscv,sv39";
  49. reg = <1>;
  50. riscv,isa = "rv64imafdc";
  51. tlb-split;
  52. next-level-cache = <&l2cache>;
  53. cpu1_intc: interrupt-controller {
  54. #interrupt-cells = <1>;
  55. compatible = "riscv,cpu-intc";
  56. interrupt-controller;
  57. };
  58. };
  59. cpu2: cpu@2 {
  60. compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  61. d-cache-block-size = <64>;
  62. d-cache-sets = <64>;
  63. d-cache-size = <32768>;
  64. d-tlb-sets = <1>;
  65. d-tlb-size = <32>;
  66. device_type = "cpu";
  67. i-cache-block-size = <64>;
  68. i-cache-sets = <64>;
  69. i-cache-size = <32768>;
  70. i-tlb-sets = <1>;
  71. i-tlb-size = <32>;
  72. mmu-type = "riscv,sv39";
  73. reg = <2>;
  74. riscv,isa = "rv64imafdc";
  75. tlb-split;
  76. next-level-cache = <&l2cache>;
  77. cpu2_intc: interrupt-controller {
  78. #interrupt-cells = <1>;
  79. compatible = "riscv,cpu-intc";
  80. interrupt-controller;
  81. };
  82. };
  83. cpu3: cpu@3 {
  84. compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  85. d-cache-block-size = <64>;
  86. d-cache-sets = <64>;
  87. d-cache-size = <32768>;
  88. d-tlb-sets = <1>;
  89. d-tlb-size = <32>;
  90. device_type = "cpu";
  91. i-cache-block-size = <64>;
  92. i-cache-sets = <64>;
  93. i-cache-size = <32768>;
  94. i-tlb-sets = <1>;
  95. i-tlb-size = <32>;
  96. mmu-type = "riscv,sv39";
  97. reg = <3>;
  98. riscv,isa = "rv64imafdc";
  99. tlb-split;
  100. next-level-cache = <&l2cache>;
  101. cpu3_intc: interrupt-controller {
  102. #interrupt-cells = <1>;
  103. compatible = "riscv,cpu-intc";
  104. interrupt-controller;
  105. };
  106. };
  107. cpu4: cpu@4 {
  108. compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  109. d-cache-block-size = <64>;
  110. d-cache-sets = <64>;
  111. d-cache-size = <32768>;
  112. d-tlb-sets = <1>;
  113. d-tlb-size = <32>;
  114. device_type = "cpu";
  115. i-cache-block-size = <64>;
  116. i-cache-sets = <64>;
  117. i-cache-size = <32768>;
  118. i-tlb-sets = <1>;
  119. i-tlb-size = <32>;
  120. mmu-type = "riscv,sv39";
  121. reg = <4>;
  122. riscv,isa = "rv64imafdc";
  123. tlb-split;
  124. next-level-cache = <&l2cache>;
  125. cpu4_intc: interrupt-controller {
  126. #interrupt-cells = <1>;
  127. compatible = "riscv,cpu-intc";
  128. interrupt-controller;
  129. };
  130. };
  131. };
  132. soc {
  133. #address-cells = <2>;
  134. #size-cells = <2>;
  135. compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
  136. ranges;
  137. plic0: interrupt-controller@c000000 {
  138. #interrupt-cells = <1>;
  139. compatible = "sifive,plic-1.0.0";
  140. reg = <0x0 0xc000000 0x0 0x4000000>;
  141. riscv,ndev = <53>;
  142. interrupt-controller;
  143. interrupts-extended = <
  144. &cpu0_intc 0xffffffff
  145. &cpu1_intc 0xffffffff &cpu1_intc 9
  146. &cpu2_intc 0xffffffff &cpu2_intc 9
  147. &cpu3_intc 0xffffffff &cpu3_intc 9
  148. &cpu4_intc 0xffffffff &cpu4_intc 9>;
  149. };
  150. prci: clock-controller@10000000 {
  151. compatible = "sifive,fu540-c000-prci";
  152. reg = <0x0 0x10000000 0x0 0x1000>;
  153. clocks = <&hfclk>, <&rtcclk>;
  154. #clock-cells = <1>;
  155. };
  156. uart0: serial@10010000 {
  157. compatible = "sifive,fu540-c000-uart", "sifive,uart0";
  158. reg = <0x0 0x10010000 0x0 0x1000>;
  159. interrupt-parent = <&plic0>;
  160. interrupts = <4>;
  161. clocks = <&prci PRCI_CLK_TLCLK>;
  162. status = "disabled";
  163. };
  164. dma: dma@3000000 {
  165. compatible = "sifive,fu540-c000-pdma";
  166. reg = <0x0 0x3000000 0x0 0x8000>;
  167. interrupt-parent = <&plic0>;
  168. interrupts = <23 24 25 26 27 28 29 30>;
  169. #dma-cells = <1>;
  170. };
  171. uart1: serial@10011000 {
  172. compatible = "sifive,fu540-c000-uart", "sifive,uart0";
  173. reg = <0x0 0x10011000 0x0 0x1000>;
  174. interrupt-parent = <&plic0>;
  175. interrupts = <5>;
  176. clocks = <&prci PRCI_CLK_TLCLK>;
  177. status = "disabled";
  178. };
  179. i2c0: i2c@10030000 {
  180. compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
  181. reg = <0x0 0x10030000 0x0 0x1000>;
  182. interrupt-parent = <&plic0>;
  183. interrupts = <50>;
  184. clocks = <&prci PRCI_CLK_TLCLK>;
  185. reg-shift = <2>;
  186. reg-io-width = <1>;
  187. #address-cells = <1>;
  188. #size-cells = <0>;
  189. status = "disabled";
  190. };
  191. qspi0: spi@10040000 {
  192. compatible = "sifive,fu540-c000-spi", "sifive,spi0";
  193. reg = <0x0 0x10040000 0x0 0x1000
  194. 0x0 0x20000000 0x0 0x10000000>;
  195. interrupt-parent = <&plic0>;
  196. interrupts = <51>;
  197. clocks = <&prci PRCI_CLK_TLCLK>;
  198. #address-cells = <1>;
  199. #size-cells = <0>;
  200. status = "disabled";
  201. };
  202. qspi1: spi@10041000 {
  203. compatible = "sifive,fu540-c000-spi", "sifive,spi0";
  204. reg = <0x0 0x10041000 0x0 0x1000
  205. 0x0 0x30000000 0x0 0x10000000>;
  206. interrupt-parent = <&plic0>;
  207. interrupts = <52>;
  208. clocks = <&prci PRCI_CLK_TLCLK>;
  209. #address-cells = <1>;
  210. #size-cells = <0>;
  211. status = "disabled";
  212. };
  213. qspi2: spi@10050000 {
  214. compatible = "sifive,fu540-c000-spi", "sifive,spi0";
  215. reg = <0x0 0x10050000 0x0 0x1000>;
  216. interrupt-parent = <&plic0>;
  217. interrupts = <6>;
  218. clocks = <&prci PRCI_CLK_TLCLK>;
  219. #address-cells = <1>;
  220. #size-cells = <0>;
  221. status = "disabled";
  222. };
  223. eth0: ethernet@10090000 {
  224. compatible = "sifive,fu540-c000-gem";
  225. interrupt-parent = <&plic0>;
  226. interrupts = <53>;
  227. reg = <0x0 0x10090000 0x0 0x2000
  228. 0x0 0x100a0000 0x0 0x1000>;
  229. local-mac-address = [00 00 00 00 00 00];
  230. clock-names = "pclk", "hclk";
  231. clocks = <&prci PRCI_CLK_GEMGXLPLL>,
  232. <&prci PRCI_CLK_GEMGXLPLL>;
  233. #address-cells = <1>;
  234. #size-cells = <0>;
  235. status = "disabled";
  236. };
  237. pwm0: pwm@10020000 {
  238. compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
  239. reg = <0x0 0x10020000 0x0 0x1000>;
  240. interrupt-parent = <&plic0>;
  241. interrupts = <42 43 44 45>;
  242. clocks = <&prci PRCI_CLK_TLCLK>;
  243. #pwm-cells = <3>;
  244. status = "disabled";
  245. };
  246. pwm1: pwm@10021000 {
  247. compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
  248. reg = <0x0 0x10021000 0x0 0x1000>;
  249. interrupt-parent = <&plic0>;
  250. interrupts = <46 47 48 49>;
  251. clocks = <&prci PRCI_CLK_TLCLK>;
  252. #pwm-cells = <3>;
  253. status = "disabled";
  254. };
  255. l2cache: cache-controller@2010000 {
  256. compatible = "sifive,fu540-c000-ccache", "cache";
  257. cache-block-size = <64>;
  258. cache-level = <2>;
  259. cache-sets = <1024>;
  260. cache-size = <2097152>;
  261. cache-unified;
  262. interrupt-parent = <&plic0>;
  263. interrupts = <1 2 3>;
  264. reg = <0x0 0x2010000 0x0 0x1000>;
  265. };
  266. gpio: gpio@10060000 {
  267. compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
  268. interrupt-parent = <&plic0>;
  269. interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>,
  270. <14>, <15>, <16>, <17>, <18>, <19>, <20>,
  271. <21>, <22>;
  272. reg = <0x0 0x10060000 0x0 0x1000>;
  273. gpio-controller;
  274. #gpio-cells = <2>;
  275. interrupt-controller;
  276. #interrupt-cells = <2>;
  277. clocks = <&prci PRCI_CLK_TLCLK>;
  278. status = "disabled";
  279. };
  280. };
  281. };