SmbiosPlatformDxe.c 19 KB

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  1. /** @file
  2. This driver installs SMBIOS information for Socionext SynQuacer platforms
  3. Copyright (c) 2015, ARM Limited. All rights reserved.
  4. Copyright (c) 2018, Linaro, Ltd. All rights reserved.
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. #include <PiDxe.h>
  8. #include <IndustryStandard/SmBios.h>
  9. #include <Library/BaseLib.h>
  10. #include <Library/BaseMemoryLib.h>
  11. #include <Library/DebugLib.h>
  12. #include <Library/HobLib.h>
  13. #include <Library/MemoryAllocationLib.h>
  14. #include <Library/UefiBootServicesTableLib.h>
  15. #include <Protocol/Smbios.h>
  16. STATIC EFI_SMBIOS_PROTOCOL *mSmbios;
  17. //
  18. // Type definition and contents of the default SMBIOS table.
  19. // This table covers only the minimum structures required by
  20. // the SMBIOS specification (section 6.2, version 3.0)
  21. //
  22. #pragma pack(1)
  23. typedef struct {
  24. SMBIOS_TABLE_TYPE0 Base;
  25. CHAR8 Strings[];
  26. } ARM_TYPE0;
  27. typedef struct {
  28. SMBIOS_TABLE_TYPE1 Base;
  29. CHAR8 Strings[];
  30. } ARM_TYPE1;
  31. typedef struct {
  32. SMBIOS_TABLE_TYPE2 Base;
  33. CHAR8 Strings[];
  34. } ARM_TYPE2;
  35. typedef struct {
  36. SMBIOS_TABLE_TYPE3 Base;
  37. CHAR8 Strings[];
  38. } ARM_TYPE3;
  39. typedef struct {
  40. SMBIOS_TABLE_TYPE4 Base;
  41. CHAR8 Strings[];
  42. } ARM_TYPE4;
  43. typedef struct {
  44. SMBIOS_TABLE_TYPE7 Base;
  45. CHAR8 Strings[];
  46. } ARM_TYPE7;
  47. typedef struct {
  48. SMBIOS_TABLE_TYPE9 Base;
  49. CHAR8 Strings[];
  50. } ARM_TYPE9;
  51. typedef struct {
  52. SMBIOS_TABLE_TYPE16 Base;
  53. CHAR8 Strings[];
  54. } ARM_TYPE16;
  55. typedef struct {
  56. SMBIOS_TABLE_TYPE17 Base;
  57. CHAR8 Strings[];
  58. } ARM_TYPE17;
  59. typedef struct {
  60. SMBIOS_TABLE_TYPE19 Base;
  61. CHAR8 Strings[];
  62. } ARM_TYPE19;
  63. typedef struct {
  64. SMBIOS_TABLE_TYPE32 Base;
  65. CHAR8 Strings[];
  66. } ARM_TYPE32;
  67. #pragma pack()
  68. enum {
  69. SMBIOS_HANDLE_A53_L1I = 0x1000,
  70. SMBIOS_HANDLE_A53_L1D,
  71. SMBIOS_HANDLE_A53_L2,
  72. SMBIOS_HANDLE_A53_L3,
  73. SMBIOS_HANDLE_MOTHERBOARD,
  74. SMBIOS_HANDLE_CHASSIS,
  75. SMBIOS_HANDLE_A53_CLUSTER,
  76. SMBIOS_HANDLE_MEMORY,
  77. };
  78. // BIOS information (section 7.1)
  79. STATIC CONST ARM_TYPE0 mArmDefaultType0 = {
  80. {
  81. { // SMBIOS_STRUCTURE Hdr
  82. EFI_SMBIOS_TYPE_BIOS_INFORMATION,
  83. sizeof (SMBIOS_TABLE_TYPE0),
  84. SMBIOS_HANDLE_PI_RESERVED,
  85. },
  86. 1, // Vendor
  87. 2, // BiosVersion
  88. 0xE800, // BiosSegment
  89. 3, // BiosReleaseDate
  90. (FixedPcdGet32 (PcdFdSize) - 1) / SIZE_64KB, // BiosSize
  91. {
  92. 0, 0, 0, 0, 0, 0,
  93. 1, // PCI supported
  94. 0,
  95. 1, // PNP supported
  96. 0,
  97. 1, // BIOS upgradable
  98. 0, 0, 0,
  99. 1, // Boot from CD
  100. 1, // Selectable boot
  101. },
  102. { 0x3, 0xC, }, // BIOSCharacteristicsExtensionBytes[2]
  103. FixedPcdGet32 (PcdFirmwareRevision) >> 16, // SystemBiosMajorRelease
  104. FixedPcdGet32 (PcdFirmwareRevision) & 0xff, // SystemBiosMinorRelease
  105. 0xFF, // EmbeddedControllerFirmwareMajorRelease
  106. 0xFF // EmbeddedControllerFirmwareMinorRelease
  107. }, {
  108. FIRMWARE_VENDOR " \0"
  109. "build #" BUILD_NUMBER "\0"
  110. __DATE__ "\0"
  111. }
  112. };
  113. // System information (section 7.2)
  114. STATIC CONST ARM_TYPE1 mArmDefaultType1 = {
  115. {
  116. { // SMBIOS_STRUCTURE Hdr
  117. EFI_SMBIOS_TYPE_SYSTEM_INFORMATION,
  118. sizeof(SMBIOS_TABLE_TYPE1),
  119. SMBIOS_HANDLE_PI_RESERVED,
  120. },
  121. 1, // Manufacturer
  122. 2, // Product Name
  123. 0, // Version
  124. 0, // Serial
  125. { 0xbf4ec78a, 0x431d, 0x4eb6, { 0xbb, 0xc9, 0x0c, 0x06, 0x19, 0x05, 0xca, 0x13 }},
  126. 6, // Wakeup type
  127. 0, // SKU
  128. 0, // Family
  129. }, {
  130. "Socionext\0"
  131. "SynQuacer E-series DeveloperBox\0"
  132. }
  133. };
  134. // Enclosure
  135. STATIC CONST ARM_TYPE3 mArmDefaultType3 = {
  136. {
  137. { // SMBIOS_STRUCTURE Hdr
  138. EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE,
  139. sizeof (SMBIOS_TABLE_TYPE3),
  140. SMBIOS_HANDLE_CHASSIS,
  141. },
  142. 1, // Manufacturer
  143. 4, // Enclosure type (low profile desktop)
  144. 2, // Version
  145. 0, // Serial
  146. 0, // Asset tag
  147. ChassisStateUnknown, // boot chassis state
  148. ChassisStateSafe, // power supply state
  149. ChassisStateSafe, // thermal state
  150. ChassisSecurityStatusNone, // security state
  151. { 0, 0, 0, 0 }, // OEM defined
  152. 1, // 1U height
  153. 1, // number of power cords
  154. 0, // no contained elements
  155. }, {
  156. "InWin\0"
  157. "BK623\0"
  158. }
  159. };
  160. STATIC CONST ARM_TYPE4 mArmDefaultType4 = {
  161. {
  162. { // SMBIOS_STRUCTURE Hdr
  163. EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION,
  164. sizeof (SMBIOS_TABLE_TYPE4),
  165. SMBIOS_HANDLE_A53_CLUSTER,
  166. },
  167. 0, // socket type
  168. 3, // processor type CPU
  169. ProcessorFamilyIndicatorFamily2, // processor family, acquire from field2
  170. 1, // manufacturer
  171. {}, // processor id
  172. 2, // version
  173. { 0, 0, 0, 0, 0, 1 }, // voltage
  174. 0, // external clock
  175. 1000, // max speed
  176. 1000, // current speed
  177. 0x41, // status
  178. ProcessorUpgradeNone,
  179. SMBIOS_HANDLE_A53_L1D, // l1 cache handle
  180. SMBIOS_HANDLE_A53_L2, // l2 cache handle
  181. SMBIOS_HANDLE_A53_L3, // l3 cache handle
  182. 0, // serial not set
  183. 0, // asset not set
  184. 3, // part number
  185. 24, // core count in socket
  186. 24, // enabled core count in socket
  187. 24, // threads per socket
  188. 0xEC, // processor characteristics
  189. ProcessorFamilyARM, // ARM core
  190. }, {
  191. "ARM Ltd.\0"
  192. "Cortex-A53\0"
  193. "0xd03\0"
  194. }
  195. };
  196. STATIC CONST ARM_TYPE7 mArmDefaultType7_l1i = {
  197. {
  198. { // SMBIOS_STRUCTURE Hdr
  199. EFI_SMBIOS_TYPE_CACHE_INFORMATION,
  200. sizeof (SMBIOS_TABLE_TYPE7),
  201. SMBIOS_HANDLE_A53_L1I,
  202. },
  203. 1,
  204. 0x380, // L1 enabled
  205. 32, // 32k i cache max
  206. 32, // 32k installed
  207. { 0, 1 }, // SRAM type
  208. { 0, 1 }, // SRAM type
  209. 0, // unknown speed
  210. CacheErrorParity,
  211. CacheTypeInstruction,
  212. CacheAssociativity2Way,
  213. }, {
  214. "L1 Instruction\0"
  215. }
  216. };
  217. STATIC CONST ARM_TYPE7 mArmDefaultType7_l1d = {
  218. {
  219. { // SMBIOS_STRUCTURE Hdr
  220. EFI_SMBIOS_TYPE_CACHE_INFORMATION,
  221. sizeof (SMBIOS_TABLE_TYPE7),
  222. SMBIOS_HANDLE_A53_L1D,
  223. },
  224. 1,
  225. 0x180, // L1 enabled, WB
  226. 32, // 32k d cache max
  227. 32, // 32k installed
  228. { 0, 1 }, // SRAM type
  229. { 0, 1 }, // SRAM type
  230. 0, // unknown speed
  231. CacheErrorSingleBit,
  232. CacheTypeData,
  233. CacheAssociativity4Way,
  234. }, {
  235. "L1 Data\0"
  236. }
  237. };
  238. STATIC CONST ARM_TYPE7 mArmDefaultType7_l2 = {
  239. {
  240. { // SMBIOS_STRUCTURE Hdr
  241. EFI_SMBIOS_TYPE_CACHE_INFORMATION,
  242. sizeof (SMBIOS_TABLE_TYPE7),
  243. SMBIOS_HANDLE_A53_L2,
  244. },
  245. 1,
  246. 0x181, // L2 enabled, WB
  247. 256, // 256 KB cache max
  248. 256, // 256 KB installed
  249. { 0, 1 }, // SRAM type
  250. { 0, 1 }, // SRAM type
  251. 0, // unknown speed
  252. CacheErrorSingleBit,
  253. CacheTypeUnified,
  254. CacheAssociativity16Way,
  255. }, {
  256. "L2\0"
  257. }
  258. };
  259. STATIC CONST ARM_TYPE7 mArmDefaultType7_l3 = {
  260. {
  261. { // SMBIOS_STRUCTURE Hdr
  262. EFI_SMBIOS_TYPE_CACHE_INFORMATION,
  263. sizeof (SMBIOS_TABLE_TYPE7),
  264. SMBIOS_HANDLE_A53_L3,
  265. },
  266. 1,
  267. 0x182, // L3 enabled, WB
  268. 4096, // 4M cache max
  269. 4096, // 4M installed
  270. { 0, 1 }, // SRAM type
  271. { 0, 1 }, // SRAM type
  272. 0, // unknown speed
  273. CacheErrorSingleBit,
  274. CacheTypeUnified,
  275. CacheAssociativity16Way,
  276. }, {
  277. "L3\0"
  278. }
  279. };
  280. // Slots
  281. STATIC CONST ARM_TYPE9 mArmDefaultType9_0 = {
  282. {
  283. { // SMBIOS_STRUCTURE Hdr
  284. EFI_SMBIOS_TYPE_SYSTEM_SLOTS,
  285. sizeof (SMBIOS_TABLE_TYPE9),
  286. SMBIOS_HANDLE_PI_RESERVED,
  287. },
  288. 1,
  289. SlotTypePciExpressGen2X16,
  290. SlotDataBusWidth4X,
  291. SlotUsageUnknown,
  292. SlotLengthLong,
  293. 0,
  294. { 1 },
  295. {},
  296. 1,
  297. 0,
  298. 0,
  299. }, {
  300. "J-PCIEX16\0"
  301. }
  302. };
  303. STATIC CONST ARM_TYPE9 mArmDefaultType9_1 = {
  304. {
  305. { // SMBIOS_STRUCTURE Hdr
  306. EFI_SMBIOS_TYPE_SYSTEM_SLOTS,
  307. sizeof (SMBIOS_TABLE_TYPE9),
  308. SMBIOS_HANDLE_PI_RESERVED,
  309. },
  310. 1,
  311. SlotTypePciExpressGen2X1,
  312. SlotDataBusWidth1X,
  313. SlotUsageUnknown,
  314. SlotLengthShort,
  315. 0,
  316. { 1 },
  317. {},
  318. 0x0,
  319. 0x3,
  320. 0x0,
  321. }, {
  322. "J-PCIE1\0"
  323. }
  324. };
  325. STATIC CONST ARM_TYPE9 mArmDefaultType9_2 = {
  326. {
  327. { // SMBIOS_STRUCTURE Hdr
  328. EFI_SMBIOS_TYPE_SYSTEM_SLOTS,
  329. sizeof (SMBIOS_TABLE_TYPE9),
  330. SMBIOS_HANDLE_PI_RESERVED,
  331. },
  332. 1,
  333. SlotTypePciExpressGen2X1,
  334. SlotDataBusWidth1X,
  335. SlotUsageUnknown,
  336. SlotLengthShort,
  337. 0,
  338. { 1 },
  339. {},
  340. 0x0,
  341. 0x5,
  342. 0x0,
  343. }, {
  344. "J-PCIE2\0"
  345. }
  346. };
  347. // Memory array
  348. STATIC CONST ARM_TYPE16 mArmDefaultType16 = {
  349. {
  350. { // SMBIOS_STRUCTURE Hdr
  351. EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY,
  352. sizeof (SMBIOS_TABLE_TYPE16),
  353. SMBIOS_HANDLE_MEMORY,
  354. },
  355. MemoryArrayLocationSystemBoard, // on motherboard
  356. MemoryArrayUseSystemMemory, // system RAM
  357. MemoryErrorCorrectionNone,
  358. 0x4000000, // max 64 GB
  359. 0xFFFE, // No error information structure
  360. 4, // 4 DIMMs
  361. }, {
  362. "\0"
  363. }
  364. };
  365. // Memory device
  366. STATIC CONST ARM_TYPE17 mArmDefaultType17_1 = {
  367. {
  368. { // SMBIOS_STRUCTURE Hdr
  369. EFI_SMBIOS_TYPE_MEMORY_DEVICE,
  370. sizeof (SMBIOS_TABLE_TYPE17),
  371. SMBIOS_HANDLE_PI_RESERVED,
  372. },
  373. SMBIOS_HANDLE_MEMORY, // array to which this module belongs
  374. 0xFFFE, // no errors
  375. 72, // single DIMM with ECC
  376. 64, // data width of this device (64-bits)
  377. 0xFFFF, // size unknown
  378. 0x09, // DIMM
  379. 1, // part of a set
  380. 1, // device locator
  381. 0, // bank locator
  382. MemoryTypeDdr4, // DDR4
  383. {}, // type detail
  384. 0, // ? MHz
  385. 0, // manufacturer
  386. 0, // serial
  387. 0, // asset tag
  388. 0, // part number
  389. 0, // rank
  390. }, {
  391. "DIMM1\0"
  392. }
  393. };
  394. STATIC CONST ARM_TYPE17 mArmDefaultType17_2 = {
  395. {
  396. { // SMBIOS_STRUCTURE Hdr
  397. EFI_SMBIOS_TYPE_MEMORY_DEVICE,
  398. sizeof (SMBIOS_TABLE_TYPE17),
  399. SMBIOS_HANDLE_PI_RESERVED,
  400. },
  401. SMBIOS_HANDLE_MEMORY, // array to which this module belongs
  402. 0xFFFE, // no errors
  403. 72, // single DIMM with ECC
  404. 64, // data width of this device (64-bits)
  405. 0xFFFF, // size unknown
  406. 0x09, // DIMM
  407. 1, // part of a set
  408. 1, // device locator
  409. 0, // bank locator
  410. MemoryTypeDdr4, // DDR4
  411. {}, // type detail
  412. 0, // ? MHz
  413. 0, // manufacturer
  414. 0, // serial
  415. 0, // asset tag
  416. 0, // part number
  417. 0, // rank
  418. }, {
  419. "DIMM2\0"
  420. }
  421. };
  422. STATIC CONST ARM_TYPE17 mArmDefaultType17_3 = {
  423. {
  424. { // SMBIOS_STRUCTURE Hdr
  425. EFI_SMBIOS_TYPE_MEMORY_DEVICE,
  426. sizeof (SMBIOS_TABLE_TYPE17),
  427. SMBIOS_HANDLE_PI_RESERVED,
  428. },
  429. SMBIOS_HANDLE_MEMORY, // array to which this module belongs
  430. 0xFFFE, // no errors
  431. 72, // single DIMM with ECC
  432. 64, // data width of this device (64-bits)
  433. 0xFFFF, // size unknown
  434. 0x09, // DIMM
  435. 1, // part of a set
  436. 1, // device locator
  437. 0, // bank locator
  438. MemoryTypeDdr4, // DDR4
  439. {}, // type detail
  440. 0, // ? MHz
  441. 0, // manufacturer
  442. 0, // serial
  443. 0, // asset tag
  444. 0, // part number
  445. 0, // rank
  446. }, {
  447. "DIMM3\0"
  448. }
  449. };
  450. STATIC CONST ARM_TYPE17 mArmDefaultType17_4 = {
  451. {
  452. { // SMBIOS_STRUCTURE Hdr
  453. EFI_SMBIOS_TYPE_MEMORY_DEVICE,
  454. sizeof (SMBIOS_TABLE_TYPE17),
  455. SMBIOS_HANDLE_PI_RESERVED,
  456. },
  457. SMBIOS_HANDLE_MEMORY, // array to which this module belongs
  458. 0xFFFE, // no errors
  459. 72, // single DIMM with ECC
  460. 64, // data width of this device (64-bits)
  461. 0xFFFF, // size unknown
  462. 0x09, // DIMM
  463. 1, // part of a set
  464. 1, // device locator
  465. 0, // bank locator
  466. MemoryTypeDdr4, // DDR4
  467. {}, // type detail
  468. 0, // ? MHz
  469. 0, // manufacturer
  470. 0, // serial
  471. 0, // asset tag
  472. 0, // part number
  473. 0, // rank
  474. }, {
  475. "DIMM4\0"
  476. }
  477. };
  478. // Memory array mapped address, this structure
  479. // is overridden by InstallMemoryStructure
  480. STATIC CONST ARM_TYPE19 mArmDefaultType19 = {
  481. {
  482. { // SMBIOS_STRUCTURE Hdr
  483. EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS,
  484. sizeof (SMBIOS_TABLE_TYPE19),
  485. SMBIOS_HANDLE_PI_RESERVED,
  486. },
  487. 0xFFFFFFFF, // invalid, look at extended addr field
  488. 0xFFFFFFFF,
  489. SMBIOS_HANDLE_MEMORY, // handle
  490. 1,
  491. 0x0,
  492. 0x0,
  493. }, {
  494. "\0"
  495. }
  496. };
  497. // System boot info
  498. STATIC CONST ARM_TYPE32 mArmDefaultType32 = {
  499. {
  500. { // SMBIOS_STRUCTURE Hdr
  501. EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION,
  502. sizeof (SMBIOS_TABLE_TYPE32),
  503. SMBIOS_HANDLE_PI_RESERVED,
  504. },
  505. {},
  506. BootInformationStatusNoError,
  507. }, {
  508. "\0"
  509. }
  510. };
  511. STATIC SMBIOS_STRUCTURE * CONST FixedTables[] = {
  512. (SMBIOS_STRUCTURE *)&mArmDefaultType0.Base.Hdr,
  513. (SMBIOS_STRUCTURE *)&mArmDefaultType1.Base.Hdr,
  514. (SMBIOS_STRUCTURE *)&mArmDefaultType3.Base.Hdr,
  515. (SMBIOS_STRUCTURE *)&mArmDefaultType7_l1i.Base.Hdr,
  516. (SMBIOS_STRUCTURE *)&mArmDefaultType7_l1d.Base.Hdr,
  517. (SMBIOS_STRUCTURE *)&mArmDefaultType7_l2.Base.Hdr,
  518. (SMBIOS_STRUCTURE *)&mArmDefaultType7_l3.Base.Hdr,
  519. (SMBIOS_STRUCTURE *)&mArmDefaultType4.Base.Hdr,
  520. (SMBIOS_STRUCTURE *)&mArmDefaultType9_0.Base.Hdr,
  521. (SMBIOS_STRUCTURE *)&mArmDefaultType9_1.Base.Hdr,
  522. (SMBIOS_STRUCTURE *)&mArmDefaultType9_2.Base.Hdr,
  523. (SMBIOS_STRUCTURE *)&mArmDefaultType16.Base.Hdr,
  524. (SMBIOS_STRUCTURE *)&mArmDefaultType17_1.Base.Hdr,
  525. (SMBIOS_STRUCTURE *)&mArmDefaultType17_2.Base.Hdr,
  526. (SMBIOS_STRUCTURE *)&mArmDefaultType17_3.Base.Hdr,
  527. (SMBIOS_STRUCTURE *)&mArmDefaultType17_4.Base.Hdr,
  528. (SMBIOS_STRUCTURE *)&mArmDefaultType32.Base.Hdr,
  529. };
  530. STATIC
  531. EFI_STATUS
  532. InstallMemoryStructure (
  533. IN UINT64 StartingAddress,
  534. IN UINT64 RegionLength
  535. )
  536. {
  537. EFI_SMBIOS_HANDLE SmbiosHandle;
  538. CHAR8 Buffer[sizeof (mArmDefaultType19)];
  539. ARM_TYPE19 *Descriptor;
  540. CopyMem (Buffer, &mArmDefaultType19, sizeof (Buffer));
  541. Descriptor = (ARM_TYPE19 *)Buffer;
  542. Descriptor->Base.ExtendedStartingAddress = StartingAddress;
  543. Descriptor->Base.ExtendedEndingAddress = StartingAddress + RegionLength;
  544. SmbiosHandle = Descriptor->Base.Hdr.Handle;
  545. return mSmbios->Add (mSmbios, NULL, &SmbiosHandle, &Descriptor->Base.Hdr);
  546. }
  547. STATIC
  548. VOID
  549. InstallAllStructures (
  550. VOID
  551. )
  552. {
  553. EFI_STATUS Status;
  554. EFI_SMBIOS_HANDLE SmbiosHandle;
  555. UINTN Idx;
  556. EFI_PEI_HOB_POINTERS Hob;
  557. for (Idx = 0; Idx < ARRAY_SIZE (FixedTables); Idx++) {
  558. SmbiosHandle = FixedTables[Idx]->Handle;
  559. Status = mSmbios->Add (mSmbios, NULL, &SmbiosHandle, FixedTables[Idx]);
  560. if (EFI_ERROR(Status)) {
  561. DEBUG ((DEBUG_WARN, "%a: failed to add SMBIOS type %u table - %r\n",
  562. __FUNCTION__, FixedTables[Idx]->Type, Status));
  563. break;
  564. }
  565. }
  566. for (Hob.Raw = GetHobList ();
  567. !END_OF_HOB_LIST (Hob);
  568. Hob.Raw = GET_NEXT_HOB (Hob)) {
  569. if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR &&
  570. Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) {
  571. Status = InstallMemoryStructure (Hob.ResourceDescriptor->PhysicalStart,
  572. Hob.ResourceDescriptor->ResourceLength);
  573. if (EFI_ERROR(Status)) {
  574. DEBUG ((DEBUG_WARN, "%a: failed to add SMBIOS type 19 table - %r\n",
  575. __FUNCTION__, Status));
  576. break;
  577. }
  578. }
  579. }
  580. }
  581. /**
  582. Installs SMBIOS information for SynQuacer platform
  583. @param ImageHandle Module's image handle
  584. @param SystemTable Pointer of EFI_SYSTEM_TABLE
  585. @retval EFI_SUCCESS Smbios data successfully installed
  586. @retval Other Smbios data was not installed
  587. **/
  588. EFI_STATUS
  589. EFIAPI
  590. SmbiosPlatformDxeEntryPoint (
  591. IN EFI_HANDLE ImageHandle,
  592. IN EFI_SYSTEM_TABLE *SystemTable
  593. )
  594. {
  595. EFI_STATUS Status;
  596. Status = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL,
  597. (VOID **)&mSmbios);
  598. ASSERT_EFI_ERROR (Status);
  599. InstallAllStructures ();
  600. return EFI_SUCCESS;
  601. }