PlatformPkg.fdf 41 KB

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  1. ## @file
  2. # FDF file of platform with 64-bit DXE
  3. # This package provides platform specific modules and flash layout information.
  4. #
  5. # @copyright
  6. # Copyright 2006 - 2021 Intel Corporation. <BR>
  7. #
  8. # SPDX-License-Identifier: BSD-2-Clause-Patent
  9. ##
  10. [Defines]
  11. DEFINE PLATFORM_PKG = MinPlatformPkg
  12. # 0x00000060 = (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_FFS_FILE_HEADER))
  13. DEFINE FDF_FIRMWARE_HEADER_SIZE = 0x00000060
  14. DEFINE MICROCODE_HEADER_SIZE = 0x00000090
  15. DEFINE VPD_HEADER_SIZE = 0x00000090
  16. !if $(FSP_MODE) == 0
  17. DEFINE FSP_BIN_DIR = Api
  18. !else
  19. DEFINE FSP_BIN_DIR = Dispatch
  20. !endif
  21. #
  22. # Note: FlashNv PCD naming conventions are as follows:
  23. # Note: This should be 100% true of all PCD's in the gCpPlatFlashTokenSpaceGuid space, and for
  24. # Others should be examined with an effort to work toward this guideline.
  25. # PcdFlash*Base is an address, usually in the range of 0xf* of FD's, note change in FDF spec
  26. # PcdFlash*Size is a hex count of the length of the FD or FV
  27. # All Fv will have the form 'PcdFlashFv', and all Fd will have the form 'PcdFlashFd'
  28. #
  29. # Also all values will have a PCD assigned so that they can be used in the system, and
  30. # the FlashMap edit tool can be used to change the values here, without effecting the code.
  31. # This requires all code to only use the PCD tokens to recover the values.
  32. #
  33. # 16MiB Total FLASH Image (visible in memory mapped IO)
  34. #
  35. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = 0xFF000000
  36. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = 0x01000000
  37. ################################################################################
  38. #
  39. # FD SECPEI
  40. #
  41. # Contains all the SEC and PEI modules
  42. #
  43. # Layout: (Low address to high address)
  44. #
  45. # FvBsp for board specific components
  46. # FvPostMemory for compressed post memory MinPlatform spec required components
  47. # FvFspS for compressed post memory silicon initialization components
  48. # FvPostMemorySilicon for silicon components
  49. # FvFspM for pre memory silicon initialization components
  50. # FvPreMemorySilicon for silicon components
  51. # FvFspT for temp RAM silicon initilization components
  52. # FvBspPreMemory for board specific components required to intialize memory
  53. # FvAdvancedPreMemory FV for advanced features components
  54. # FvPreMemory for components required by MinPlatform spec and to initialize memory
  55. # FvPreMemorySecurity FV for stage 6 required components
  56. # Contains reset vector
  57. #
  58. ################################################################################
  59. [FD.SecPei]
  60. BaseAddress = 0xFFCA0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase #The base address of the FLASH Device
  61. Size = 0x00360000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize #The size in bytes of the FLASH Device
  62. ErasePolarity = 1
  63. BlockSize = 0x1000
  64. NumBlocks = 0x360
  65. #
  66. # These must add up to the FD Size.
  67. # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
  68. # At this time, the FSP FV must be aligned at the same address they were built to, 0xFFD00000
  69. # This will be corrected in the future.
  70. #
  71. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize = 0x00010000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must = 0xFFD00000
  72. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00010000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must = 0xFFD00000
  73. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = 0x00040000 # Size must match WhitleyFspPkg.fdf content
  74. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize = 0x00221000 # Size must match WhitleyFspPkg.fdf content
  75. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize = 0x00006000 # Size must match WhitleyFspPkg.fdf content
  76. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize = 0x00001000
  77. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
  78. #
  79. # Calculate Offsets Once (Do not modify)
  80. # This layout is specified by the EDK II Minimum Platform Archicture specification.
  81. # Each offset is the prior region's offset plus the prior region's size.
  82. #
  83. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset = 0x00000000
  84. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
  85. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  86. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  87. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  88. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  89. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
  90. #
  91. # FV Layout (Do not modify)
  92. # This layout is specified by the EDK II Minimum Platform Archicture specification.
  93. #
  94. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
  95. FV = FvBsp
  96. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  97. FV = FvPostMemory
  98. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  99. FILE = $(FSP_BIN_PKG)/Fsp_Rebased_S.fd
  100. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  101. FILE = $(FSP_BIN_PKG)/Fsp_Rebased_M.fd
  102. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  103. FILE = $(FSP_BIN_PKG)/Fsp_Rebased_T.fd
  104. #
  105. # Shared FV layout
  106. #
  107. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
  108. FV = FvBspPreMemory
  109. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
  110. FV = FvPreMemory
  111. #
  112. # Calculate base addresses (Do not modify)
  113. # This layout is specified by the EDK II Minimum Platform Archicture specification.
  114. # Each base is the prior region's base plus the prior region's size.
  115. #
  116. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset
  117. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
  118. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
  119. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
  120. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  121. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
  122. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
  123. #
  124. # Set duplicate PCD
  125. # These should not need to be changed
  126. #
  127. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
  128. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
  129. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase
  130. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
  131. #
  132. # For FSP Dispatch Mode, specify the FV containing the PEI core.
  133. #
  134. !if $(FSP_MODE) == 1
  135. #
  136. # Tell SEC to use PEI Core from outside FSP for additional debug message control.
  137. #
  138. SET gSiPkgTokenSpaceGuid.PcdPeiCoreFv = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase
  139. !endif
  140. #
  141. # For API mode, wrappers have some duplicate PCD as well
  142. #
  143. !if $(FSP_MODE) == 0
  144. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
  145. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase
  146. SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase
  147. !endif
  148. ################################################################################
  149. #
  150. # FD Main
  151. #
  152. # All DXE modules and other regions
  153. #
  154. # Layout: (Low address to high address)
  155. #
  156. # FvAdvanced for advanced feature components
  157. # Assorted advanced feature FV
  158. # FvSecurity for MinPlatform spec required components needed to boot securely
  159. # FvOsBoot for MinPlatform spec required components needed to boot OS
  160. # FvLateSilicon for silicon specific components
  161. # FvUefiBoot for MinPlatform spec required components needed to boot to UEFI shell
  162. #
  163. ################################################################################
  164. [FD.Main]
  165. BaseAddress = 0xFF2E0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase # The base address of the FLASH Device
  166. Size = 0x009C0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize # The size in bytes of the FLASH Device
  167. ErasePolarity = 1
  168. BlockSize = 0x1000
  169. NumBlocks = 0x9C0
  170. #
  171. # These must add up to the FD Size.
  172. # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
  173. # These are out of flash layout order because FvAdvanced gets any remaining space
  174. #
  175. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00010000
  176. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00230000
  177. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x0004C000
  178. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  179. #
  180. # Calculate Offsets Once (Do not modify)
  181. # This layout is specified by the EDK II Minimum Platform Archicture specification.
  182. # Each offset is the prior region's offset plus the prior region's size.
  183. #
  184. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00000000
  185. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  186. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  187. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  188. #
  189. # FV Layout (Do not modify)
  190. # This layout is specified by the EDK II Minimum Platform Archicture specification.
  191. #
  192. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  193. FV = FvAdvanced
  194. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  195. FV = FvSecurity
  196. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  197. FV = FvOsBoot
  198. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
  199. FV = FvUefiBoot
  200. #
  201. # Calculate base addresses (Do not modify)
  202. # This layout is specified by the EDK II Minimum Platform Archicture specification.
  203. # Each base is the prior region's base plus the prior region's size.
  204. #
  205. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset
  206. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
  207. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
  208. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
  209. ################################################################################
  210. #
  211. # FD BINARY
  212. #
  213. # Contains the OPROM and other binary modules
  214. #
  215. # Layout: (Low address to high address)
  216. #
  217. # FvOpRom containing pre-built components
  218. # FvAcmRegion containing ACM related content
  219. # FV Header + Blank Space (1K)
  220. # Policy block (3K)
  221. # Blank space to align ACM on 64K boundary (60K)
  222. # ACM binary
  223. # FvMicrocode containing microcode update patches
  224. # Unformatted region for PCI Gen 3 Data
  225. # FvVpd containing PCD VPD data
  226. # FvWhea for WHEA data recording
  227. # FvNvStorageVariable for UEFI Variable storage
  228. # FvNvStorageEventLog for NV Store management
  229. # FvNvStorageFtwWorking for Fault Tolerant Write solution
  230. # FvNvStorageFtwSpare for Fault Tolerant Write solution
  231. #
  232. ################################################################################
  233. [FD.Binary]
  234. BaseAddress = 0xFF000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase
  235. Size = 0x002E0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinarySize
  236. ErasePolarity = 1
  237. BlockSize = 0x1000
  238. NumBlocks = 0x2E0
  239. #
  240. # These must add up to the FD Size.
  241. # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
  242. #
  243. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize = 0x00100000
  244. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize = 0x00050000
  245. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = 0x000D0000
  246. SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize = 0x00010000
  247. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize = 0x00030000
  248. #
  249. # These four items are tightly coupled.
  250. # The spare area size must be >= the first three areas.
  251. #
  252. # There isn't really a benefit to a larger spare area unless the FLASH device
  253. # block size is larger than the size specified.
  254. #
  255. SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0x0003C000
  256. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize = 0x00002000
  257. SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = 0x00002000
  258. SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  259. #
  260. # Calculate Offsets Once (You should not need to modify this section)
  261. # Each offset is the prior region's offset plus the prior region's size.
  262. #
  263. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset = 0x00000000
  264. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
  265. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
  266. SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
  267. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset = gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize
  268. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
  269. SET gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  270. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
  271. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  272. #
  273. # Set gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress dynamically
  274. #
  275. SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + $(MICROCODE_HEADER_SIZE)
  276. #
  277. # FV Layout (You should not need to modify this section)
  278. #
  279. gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
  280. FV = FvOprom
  281. gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
  282. FV = FvAcm
  283. gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
  284. FV = FvMicrocode
  285. gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize
  286. FV = FvVPD
  287. gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
  288. FV = FvWhea
  289. #
  290. # Do not modify.
  291. # See comments in size discussion above. These four areas are tightly coupled and should be modified with utmost care.
  292. #
  293. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  294. !include WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.fdf
  295. gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
  296. DATA = { 0xFF } # Hack to ensure build doesn't treat the next PCD as Base/Size to be written
  297. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  298. !include WhitleyOpenBoardPkg/Include/Fdf/CommonNvStorageFtwWorking.fdf
  299. gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
  300. DATA = { 0xFF } # Hack to ensure build doesn't treat the next PCD as Base/Size to be written
  301. #
  302. # Calculate base addresses (You should not need to modify this section)
  303. # Each base is the prior region's base plus the prior region's size.
  304. #
  305. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset
  306. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
  307. SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
  308. SET gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + $(VPD_HEADER_SIZE)
  309. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase = gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize - $(VPD_HEADER_SIZE)
  310. SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
  311. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
  312. SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
  313. SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
  314. #
  315. # ACM details
  316. #
  317. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicyBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x1000
  318. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicySize = 0x3000
  319. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x10000
  320. SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize = 0x00040000
  321. #
  322. # Other duplicate PCD
  323. #
  324. SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
  325. SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
  326. ################################################################################
  327. #
  328. # FD FPGA
  329. #
  330. # Contains the FPGA modules
  331. #
  332. ################################################################################
  333. [FD.Fpga]
  334. BaseAddress = 0xFD000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaBase #The base address of the FPGA Device ( 4G - 48M )
  335. Size = 0x02000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaSize #The size in bytes of the FPGA Device ( 32M )
  336. ErasePolarity = 1
  337. BlockSize = 0x1000
  338. NumBlocks = 0x2000
  339. 0x00000000|0x02000000
  340. gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsBase | gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsSize
  341. FV = FvFpga
  342. ################################################################################
  343. #
  344. # FV Section
  345. #
  346. # [FV] section is used to define what components or modules are placed within a flash
  347. # device file. This section also defines order the components and modules are positioned
  348. # within the image. The [FV] section consists of define statements, set statements and
  349. # module statements.
  350. #
  351. ################################################################################
  352. [FV.FvSecurityPreMemory]
  353. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  354. FvNameGuid = 40ab290f-8494-41cf-b302-31b178b4ce0b
  355. [FV.FvPreMemory]
  356. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  357. FvNameGuid = 6522280D-28F9-4131-ADC4-F40EBFA45864
  358. FILE SEC = 1BA0062E-C779-4582-8566-336AE8F78F09 {
  359. SECTION UI = "SecCore"
  360. SECTION VERSION = "1.0"
  361. SECTION Align = 16 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/1BA0062E-C779-4582-8566-336AE8F78F09SecCore.efi
  362. SECTION Align = 16 RAW = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ResetVec.bin
  363. }
  364. INF MdeModulePkg/Core/Pei/PeiMain.inf
  365. INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
  366. INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.inf
  367. INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.inf
  368. INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf
  369. INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
  370. INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
  371. INF WhitleyOpenBoardPkg/BiosInfo/BiosInfo.inf
  372. FILE PEIM = 0043A734-CB11-4274-B363-E165F958CB5F {
  373. SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/0043A734-CB11-4274-B363-E165F958CB5FMultiPch.depex
  374. SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/0043A734-CB11-4274-B363-E165F958CB5FMultiPch.efi
  375. SECTION UI = "MultiPch"
  376. }
  377. FILE PEIM = ac4b7f1b-e057-47d3-b2b5-1137493c0f38 {
  378. SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.depex
  379. SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.efi
  380. SECTION UI = "DynamicSiLibraryPei"
  381. }
  382. INF WhitleyOpenBoardPkg/Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei.inf
  383. INF WhitleyOpenBoardPkg/Platform/Pei/EmulationPlatformInit/EmulationPlatformInit.inf
  384. INF WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.inf
  385. #
  386. # UBA common and board specific components
  387. #
  388. !include WhitleyOpenBoardPkg/Uba/UbaPei.fdf
  389. INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
  390. INF MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf
  391. FILE PEIM = ca8efb69-d7dc-4e94-aad6-9fb373649161 {
  392. SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.depex
  393. SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.efi
  394. SECTION UI = "SiliconPolicyInitPreAndPostMem"
  395. }
  396. INF MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
  397. !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfrastructurePreMemory.fdf
  398. INF WhitleyOpenBoardPkg/Universal/PeiInterposerToSvidMap/PeiInterposerToSvidMap.inf
  399. INF UefiCpuPkg/CpuMpPei/CpuMpPei.inf
  400. !if $(FSP_MODE) == 0
  401. FILE PEIM = 8F7F3D20-9823-42DD-9FF7-53DAC93EF407 {
  402. SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.depex
  403. SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.efi
  404. SECTION UI = "CsrPseudoOffsetInitPeim"
  405. }
  406. FILE PEIM = 2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352 {
  407. SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.depex
  408. SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.efi
  409. SECTION UI = "RegAccessPeim"
  410. }
  411. FILE PEIM = C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67F {
  412. SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.depex
  413. SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.efi
  414. SECTION UI = "SiliconDataInitPeim"
  415. }
  416. INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
  417. INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
  418. INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
  419. INF WhitleyOpenBoardPkg/Platform/Pei/DummyPchSpi/DummyPchSpi.inf
  420. !endif
  421. FILE FV_IMAGE = 40ab290f-8494-41cf-b302-31b178b4ce0b {
  422. SECTION FV_IMAGE = FvSecurityPreMemory
  423. }
  424. [FV.FvAdvancedPreMemory]
  425. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  426. FvNameGuid = 09f25d44-b2ef-4225-8b2e-e0e094b51775
  427. [FV.FvBspPreMemory]
  428. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  429. FvNameGuid = e6c65995-8c2d-4119-a52d-7dbf1acb45a1
  430. FILE FV_IMAGE = 09f25d44-b2ef-4225-8b2e-e0e094b51775 {
  431. SECTION FV_IMAGE = FvAdvancedPreMemory
  432. }
  433. #
  434. # FvPostMemory includes common hardware, common core variable services, load and invoke DXE etc
  435. #
  436. [FV.FvPostMemoryUncompressed]
  437. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  438. FvNameGuid = B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA
  439. [FV.FvPostMemory]
  440. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  441. FvNameGuid = 3298afc4-c484-47f1-a65a-5917a54b5e8c
  442. FILE FV_IMAGE = B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA {
  443. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  444. SECTION FV_IMAGE = FvPostMemoryUncompressed
  445. }
  446. }
  447. #
  448. # FvBsp includes board specific components
  449. #
  450. [FV.FvBspUncompressed]
  451. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  452. FvNameGuid = e4c65347-fd90-4143-8a41-113e1015fe07
  453. [FV.FvBsp]
  454. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  455. FvNameGuid = 9e151cf3-ca90-444f-b33b-a9941cbc772f
  456. FILE FV_IMAGE = e4c65347-fd90-4143-8a41-113e1015fe07 {
  457. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  458. SECTION FV_IMAGE = FvBspUncompressed
  459. }
  460. }
  461. [FV.FvUefiBootUncompressed]
  462. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  463. FvNameGuid = C4D3B0E2-FB26-44f8-A05B-E95895FCB960
  464. INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
  465. INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
  466. INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
  467. INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
  468. INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
  469. INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
  470. INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
  471. INF MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDxe.inf
  472. INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
  473. INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
  474. INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
  475. INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
  476. INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
  477. INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
  478. INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
  479. INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
  480. INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
  481. INF MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf
  482. #ATA for IDE/AHCI/RAID support
  483. INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
  484. INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
  485. INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
  486. INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
  487. [FV.FvUefiBoot]
  488. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  489. FvNameGuid = ab9fe87b-1e37-440c-91cc-9aea03ce7bec
  490. FILE FV_IMAGE = C4D3B0E2-FB26-44f8-A05B-E95895FCB960 {
  491. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  492. SECTION FV_IMAGE = FvUefiBootUncompressed
  493. }
  494. }
  495. [FV.FvOsBootUncompressed]
  496. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  497. FvNameGuid = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0
  498. #
  499. # DXE Phase modules
  500. #
  501. INF MdeModulePkg/Core/Dxe/DxeMain.inf
  502. INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
  503. INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
  504. INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
  505. FILE FV_IMAGE = B7C9F0CB-15D8-26FC-CA3F-C63947B12831 {
  506. SECTION UI = "FvLateSilicon"
  507. SECTION FV_IMAGE = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateSilicon.fv
  508. }
  509. INF MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf
  510. !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfrastructurePostMemory.fdf
  511. #
  512. # UBA DXE common and board specific components
  513. #
  514. !include WhitleyOpenBoardPkg/Uba/UbaDxeCommon.fdf
  515. !include WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
  516. INF WhitleyOpenBoardPkg/Platform/Dxe/PlatformType/PlatformType.inf
  517. INF MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
  518. !if ($(FSP_MODE) == 1)
  519. INF WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSave.inf
  520. !else
  521. INF MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
  522. !endif
  523. INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
  524. INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
  525. INF WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf
  526. INF UefiCpuPkg/CpuDxe/CpuDxe.inf
  527. INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
  528. FILE FV_IMAGE = a0277d07-a725-4823-90f9-6cba00782111 {
  529. SECTION UI = "FvLateOpenBoard"
  530. SECTION FV_IMAGE = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateOpenBoard.fv
  531. }
  532. INF MdeModulePkg/Universal/Metronome/Metronome.inf
  533. INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
  534. INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
  535. INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
  536. INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciHostBridge.inf
  537. INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
  538. INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
  539. INF RuleOverride = UI MdeModulePkg/Application/UiApp/UiApp.inf
  540. INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf
  541. INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
  542. #TPM when TPM enable, SecurityStubDxe needs to be removed from this FV.
  543. INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
  544. INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
  545. INF FatPkg/EnhancedFatDxe/Fat.inf
  546. INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
  547. INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPlatform.inf
  548. INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
  549. INF ShellPkg/Application/Shell/Shell.inf
  550. INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
  551. INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
  552. INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
  553. INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf
  554. INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf
  555. INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
  556. INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
  557. INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
  558. INF MinPlatformPkg/Flash/SpiFvbService/SpiFvbServiceSmm.inf
  559. INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
  560. INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf
  561. INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf
  562. INF MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf
  563. INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
  564. INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
  565. # UEFI USB stack
  566. INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
  567. INF MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf
  568. INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
  569. INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
  570. INF MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
  571. INF MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf
  572. [FV.FvOsBoot]
  573. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  574. FvNameGuid = c7488640-5f51-4969-b63b-89fc369e1725
  575. FILE FV_IMAGE = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0 {
  576. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  577. SECTION FV_IMAGE = FvOsBootUncompressed
  578. }
  579. }
  580. [FV.FvSecuritySilicon]
  581. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  582. FvNameGuid = AD262F8D-BDED-4668-A8D4-8BC73516652F
  583. [FV.FvSecurityUncompressed]
  584. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  585. FvNameGuid = 03E25550-89A5-4ee6-AF60-DB0553D91FD2
  586. FILE FV_IMAGE = 81F80AEA-91EB-4AD9-A563-7CEBAA167B25 {
  587. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  588. SECTION FV_IMAGE = FvSecuritySilicon
  589. }
  590. }
  591. [FV.FvSecurity]
  592. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  593. FvNameGuid = 68134833-2ff6-4d22-973b-575d0eae8ffd
  594. FILE FV_IMAGE = 03E25550-89A5-4ee6-AF60-DB0553D91FD2 {
  595. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  596. SECTION FV_IMAGE = FvSecurityUncompressed
  597. }
  598. }
  599. [FV.FvAdvancedUncompressed]
  600. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  601. FvNameGuid = 70aeaf57-4997-49ce-a4f7-122980745670
  602. [FV.FvAdvanced]
  603. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  604. FvNameGuid = f21ee7a1-53a9-453d-aee3-b6a5c25bada5
  605. FILE FV_IMAGE = 70aeaf57-4997-49ce-a4f7-122980745670 {
  606. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  607. SECTION FV_IMAGE = FvAdvancedUncompressed
  608. }
  609. }
  610. #
  611. # FV for all Microcode Updates.
  612. #
  613. [FV.FvMicrocode]
  614. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  615. LOCK_STATUS = FALSE
  616. FvNameGuid = D2C29BA7-3809-480F-9C3D-DE389C61425A
  617. !if $(CPUTARGET) == "CPX"
  618. INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/CpxMicrocode/MicrocodeUpdates.inf
  619. !else
  620. INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/IcxMicrocode/MicrocodeUpdates.inf
  621. !endif
  622. [FV.FvVPD]
  623. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  624. LOCK_STATUS = FALSE
  625. FvNameGuid = FFC29BA7-3809-480F-9C3D-DE389C61425A
  626. FILE RAW = FF7DB236-F856-4924-90F8-CDF12FB875F3 {
  627. $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/8C3D856A-9BE6-468E-850A-24F7A8D38E08.bin
  628. }
  629. #
  630. # Various Vendor UEFI Drivers (OROMs).
  631. #
  632. [FV.FvOpromUncompressed]
  633. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  634. FvNameGuid = B6EDE22C-DE30-45fa-BB09-CA202C1654B7
  635. [FV.FvOprom]
  636. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  637. FvNameGuid = 983BCAB5-BF10-42ce-B85D-CB805DCB1EFD
  638. FILE FV_IMAGE = B6EDE22C-DE30-45fa-BB09-CA202C1654B7 {
  639. SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
  640. SECTION FV_IMAGE = FvOpromUncompressed
  641. }
  642. }
  643. [FV.FvWhea]
  644. BlockSize = 0x1000
  645. NumBlocks = 0x30
  646. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  647. FvNameGuid = d6a1cd70-4b33-4994-a6ea-375f2ccc5437
  648. #
  649. # FV For ACM Binary.
  650. #
  651. [FV.FvAcm]
  652. BlockSize = 0x1000
  653. NumBlocks = 0x50
  654. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  655. FvNameGuid = 11668261-8A8D-47ca-9893-052D24435E59
  656. [FV.FvFpga]
  657. !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
  658. FvNameGuid = 974650E7-6DFE-4998-A124-CEDEC5C9B47D
  659. ################################################################################
  660. #
  661. # Rules are use with the [FV] section's module INF type to define
  662. # how an FFS file is created for a given INF file. The following Rule are the default
  663. # rules for the different module type. User can add the customized rules to define the
  664. # content of the FFS file.
  665. #
  666. ################################################################################
  667. !include MinPlatformPkg/Include/Fdf/RuleInclude.fdf
  668. [Rule.Common.USER_DEFINED.ACPITABLE]
  669. FILE FREEFORM = $(NAMED_GUID) {
  670. RAW ACPI Optional |.acpi
  671. RAW ASL Optional |.aml
  672. }
  673. [Rule.Common.DXE_RUNTIME_DRIVER.DRIVER_ACPITABLE]
  674. FILE DRIVER = $(NAMED_GUID) {
  675. DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
  676. PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
  677. RAW ACPI Optional |.acpi
  678. RAW ASL Optional |.aml
  679. UI STRING="$(MODULE_NAME)" Optional
  680. VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
  681. }