BoardSaInitPreMemLib.c 14 KB

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  1. /** @file
  2. Source code for the board SA configuration Pcd init functions in Pre-Memory init phase.
  3. Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include "BoardSaConfigPreMem.h"
  7. #include "SaPolicyCommon.h"
  8. #include "CometlakeURvpInit.h"
  9. #include <PlatformBoardConfig.h>
  10. #include <Library/CpuPlatformLib.h>
  11. //
  12. // LPDDR3 178b 8Gb die, DDP, x32
  13. // Micron MT52L512M32D2PF-093
  14. // 2133, 16-20-20-45
  15. // 2 ranks per channel, 2 SDRAMs per rank, 4x8Gb = 4GB total per channel
  16. //
  17. GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mLpddr3Ddp8Gb178b2133Spd[] = {
  18. 0x24, // 512 SPD bytes used, 512 total
  19. 0x01, // SPD Revision 0.1
  20. 0x0F, // DRAM Type: LPDDR3 SDRAM
  21. 0x0E, // Module Type: Non-DIMM Solution
  22. 0x15, // 8 Banks, 8 Gb SDRAM density
  23. 0x19, // 15 Rows, 10 Columns
  24. 0x90, // SDRAM Package Type: DDP, 1 Channel per package
  25. 0x00, // SDRAM Optional Features: none, tMAW = 8192 * tREFI
  26. 0x00, // SDRAM Thermal / Refresh options: none
  27. 0x00, // Other SDRAM Optional Features: none
  28. 0x00, // Reserved
  29. 0x0B, // Module Nominal Voltage, VDD = 1.2v
  30. 0x0B, // SDRAM width: 32 bits, 2 Ranks
  31. 0x03, // SDRAM bus width: 1 Channel, 64 bits channel width
  32. 0x00, // Module Thermal Sensor: none
  33. 0x00, // Extended Module Type: Reserved
  34. 0x00, // Signal Loading: Unspecified
  35. 0x00, // MTB = 0.125ns, FTB = 1 ps
  36. 0x08, // tCKmin = 0.938 ns (LPDDR3-2133)
  37. 0xFF, // tCKmax = 32.002 ns
  38. 0xD4, // CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (First Byte)
  39. 0x01, // CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (Second Byte)
  40. 0x00, // CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (Third Byte)
  41. 0x00, // CAS Latencies supported (tCK): 16, 14, 12, 10, 8 (Fourth Byte)
  42. 0x78, // Minimum CAS Latency (tAAmin) = 15.008 ns
  43. 0x00, // Read and Write Latency Set options: none
  44. 0x90, // Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
  45. 0xA8, // Row precharge time for all banks (tRPab) = 21 ns
  46. 0x90, // Minimum row precharge time (tRPmin) = 18 ns
  47. 0x90, // tRFCab = 210 ns (8 Gb)
  48. 0x06, // tRFCab MSB
  49. 0xD0, // tRFCpb = 90 ns (8 Gb)
  50. 0x02, // tRFCpb MSB
  51. 0, 0, 0, 0, 0, 0, 0, // 33-39
  52. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 40-49
  53. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 50-59
  54. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 60-69
  55. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 70-79
  56. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 80-89
  57. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 90-99
  58. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 100-109
  59. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 110-119
  60. 0x00, // FTB for Row precharge time per bank (tRPpb) = 18 ns
  61. 0x00, // FTB for Row precharge time for all banks (tRPab) = 21 ns
  62. 0x00, // FTB for Minimum RAS-to-CAS delay (tRCDmin) = 18 ns
  63. 0x08, // FTB for tAAmin = 15.008 ns (LPDDR3-2133)
  64. 0x7F, // FTB for tCKmax = 32.002 ns
  65. 0xC2, // FTB for tCKmin = 0.938 ns (LPDDR3-2133)
  66. 0, 0, 0, 0, // 126-129
  67. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 130-139
  68. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 140-149
  69. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 150-159
  70. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 160-169
  71. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 170-179
  72. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 180-189
  73. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 190-199
  74. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 200-209
  75. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 210-219
  76. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 220-229
  77. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 230-239
  78. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 240-249
  79. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 250-259
  80. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 260-269
  81. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 270-279
  82. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 280-289
  83. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 290-299
  84. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 300-309
  85. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 310-319
  86. 0, 0, 0, 0, 0, // 320-324
  87. 0x55, 0, 0, 0, // 325-328: Module ID: Module Serial Number
  88. 0x20, 0x20, 0x20, 0x20, 0x20, // 329-333: Module Part Number: Unused bytes coded as ASCII Blanks (0x20)
  89. 0x20, 0x20, 0x20, 0x20, 0x20, // 334-338: Module Part Number
  90. 0x20, 0x20, 0x20, 0x20, 0x20, // 339-343: Module Part Number
  91. 0x20, 0x20, 0x20, 0x20, 0x20, // 344-348: Module Part Number
  92. 0x00, // 349 Module Revision Code
  93. 0x00, // 350 DRAM Manufacturer ID Code, Least Significant Byte
  94. 0x00, // 351 DRAM Manufacturer ID Code, Most Significant Byte
  95. 0x00, // 352 DRAM Stepping
  96. 0, 0, 0, 0, 0, 0, 0, // 353 - 359
  97. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 360 - 369
  98. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 370 - 379
  99. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 380 - 389
  100. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 390 - 399
  101. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 400 - 409
  102. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 410 - 419
  103. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 420 - 429
  104. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 430 - 439
  105. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 440 - 449
  106. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 450 - 459
  107. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 460 - 469
  108. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 470 - 479
  109. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 480 - 489
  110. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 490 - 499
  111. 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, // 500 - 509
  112. 0, 0 // 510 - 511
  113. };
  114. //
  115. // Display DDI settings for WHL ERB
  116. //
  117. GLOBAL_REMOVE_IF_UNREFERENCED const UINT8 mWhlErbRowDisplayDdiConfig[9] = {
  118. DdiPortAEdp, // DDI Port A Config : DdiPortADisabled = Disabled, DdiPortAEdp = eDP, DdiPortAMipiDsi = MIPI DSI
  119. DdiHpdEnable, // DDI Port B HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
  120. DdiHpdEnable, // DDI Port C HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
  121. DdiHpdDisable, // DDI Port D HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
  122. DdiHpdDisable, // DDI Port F HPD : DdiHpdDisable = Disable, DdiHpdEnable = Enable HPD
  123. DdiDdcEnable, // DDI Port B DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
  124. DdiDdcEnable, // DDI Port C DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
  125. DdiDdcEnable, // DDI Port D DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
  126. DdiDisable // DDI Port F DDC : DdiDisable = Disable, DdiDdcEnable = Enable DDC
  127. };
  128. /**
  129. MRC configuration init function for PEI pre-memory phase.
  130. @param[in] BoardId An unsigned integer represent the board id.
  131. @retval EFI_SUCCESS The function completed successfully.
  132. **/
  133. EFI_STATUS
  134. SaMiscConfigInit (
  135. IN UINT16 BoardId
  136. )
  137. {
  138. //
  139. // UserBd
  140. //
  141. switch (BoardId) {
  142. case BoardIdCometLakeULpddr3Rvp:
  143. //
  144. // Assign UserBd to 5 which is assigned to MrcInputs->BoardType btUser4 for ULT platforms.
  145. // This is required to skip Memory voltage programming based on GPIO's in MRC
  146. //
  147. PcdSet8S (PcdSaMiscUserBd, 5); // MrcBoardType btUser4 for ULT platform
  148. break;
  149. default:
  150. // MiscPeiPreMemConfig.UserBd = 0 by default.
  151. break;
  152. }
  153. PcdSet16S (PcdSaDdrFreqLimit, 0);
  154. return EFI_SUCCESS;
  155. }
  156. /**
  157. Board Memory Init related configuration init function for PEI pre-memory phase.
  158. @param[in] BoardId An unsigned integrer represent the board id.
  159. @retval EFI_SUCCESS The function completed successfully.
  160. **/
  161. EFI_STATUS
  162. MrcConfigInit (
  163. IN UINT16 BoardId
  164. )
  165. {
  166. CPU_FAMILY CpuFamilyId;
  167. CpuFamilyId = GetCpuFamily();
  168. if (CpuFamilyId == EnumCpuCflDtHalo) {
  169. PcdSetBoolS (PcdDualDimmPerChannelBoardType, TRUE);
  170. } else {
  171. PcdSetBoolS (PcdDualDimmPerChannelBoardType, FALSE);
  172. }
  173. //
  174. // Example policy for DIMM slots implementation boards:
  175. // 1. Assign Smbus address of DIMMs and SpdData will be updated later
  176. // by reading from DIMM SPD.
  177. // 2. No need to apply hardcoded SpdData buffers here for such board.
  178. //
  179. // Comet Lake U LP3 has removable DIMM slots.
  180. // So assign all Smbus address of DIMMs and leave PcdMrcSpdData set to 0.
  181. // Example:
  182. // PcdMrcSpdData = 0
  183. // PcdMrcSpdDataSize = 0
  184. // PcdMrcSpdAddressTable0 = 0xA0
  185. // PcdMrcSpdAddressTable1 = 0xA2
  186. // PcdMrcSpdAddressTable2 = 0xA4
  187. // PcdMrcSpdAddressTable3 = 0xA6
  188. //
  189. // If a board has soldered down memory. It should use the following settings.
  190. // Example:
  191. // PcdMrcSpdAddressTable0 = 0
  192. // PcdMrcSpdAddressTable1 = 0
  193. // PcdMrcSpdAddressTable2 = 0
  194. // PcdMrcSpdAddressTable3 = 0
  195. // PcdMrcSpdData = static data buffer
  196. // PcdMrcSpdDataSize = sizeof (static data buffer)
  197. //
  198. //
  199. // SPD Address Table
  200. //
  201. PcdSet32S (PcdMrcSpdData, (UINTN)mLpddr3Ddp8Gb178b2133Spd);
  202. PcdSet16S (PcdMrcSpdDataSize, sizeof(mLpddr3Ddp8Gb178b2133Spd));
  203. PcdSet8S (PcdMrcSpdAddressTable0, 0);
  204. PcdSet8S (PcdMrcSpdAddressTable1, 0);
  205. PcdSet8S (PcdMrcSpdAddressTable2, 0);
  206. PcdSet8S (PcdMrcSpdAddressTable3, 0);
  207. //
  208. // DRAM SPD Data & related configuration
  209. //
  210. // Setting the PCD's to default value (CML LP3). It will be overriden to board specific settings below.
  211. PcdSet32S(PcdMrcDqByteMap, (UINTN) DqByteMapCmlULpddr3Rvp);
  212. PcdSet16S (PcdMrcDqByteMapSize, sizeof (DqByteMapCmlULpddr3Rvp));
  213. PcdSet32S(PcdMrcDqsMapCpu2Dram, (UINTN) DqsMapCpu2DramCmlULpddr3Rvp);
  214. PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (DqsMapCpu2DramCmlULpddr3Rvp));
  215. switch (BoardId) {
  216. case BoardIdCometLakeULpddr3Rvp:
  217. PcdSet32S(PcdMrcRcompResistor, (UINTN)RcompResistorCmlULpKc);
  218. PcdSet32S(PcdMrcRcompTarget, (UINTN)RcompTargetCmlULpKc);
  219. PcdSetBoolS(PcdMrcDqPinsInterleavedControl, TRUE);
  220. PcdSetBoolS(PcdMrcDqPinsInterleaved, FALSE);
  221. break;
  222. default:
  223. break;
  224. }
  225. //
  226. // CA Vref routing: board-dependent
  227. // 0 - VREF_CA goes to both CH_A and CH_B (LPDDR3/DDR3L)
  228. // 1 - VREF_CA to CH_A, VREF_DQ_A to CH_B (should not be used)
  229. // 2 - VREF_CA to CH_A, VREF_DQ_B to CH_B (DDR4)
  230. //
  231. switch (BoardId) {
  232. case BoardIdCometLakeULpddr3Rvp:
  233. PcdSet8S (PcdMrcCaVrefConfig, 0); // All DDR3L/LPDDR3/LPDDR4 boards
  234. break;
  235. default:
  236. PcdSet8S (PcdMrcCaVrefConfig, 2); // DDR4 boards
  237. break;
  238. }
  239. return EFI_SUCCESS;
  240. }
  241. /**
  242. Board SA related GPIO configuration init function for PEI pre-memory phase.
  243. @param[in] BoardId An unsigned integer represent the board id.
  244. @retval EFI_SUCCESS The function completed successfully.
  245. **/
  246. EFI_STATUS
  247. SaGpioConfigInit (
  248. IN UINT16 BoardId
  249. )
  250. {
  251. //
  252. // Update board's GPIO for PEG slot reset
  253. //
  254. PcdSetBoolS (PcdPegGpioResetControl, TRUE);
  255. PcdSetBoolS (PcdPegGpioResetSupoort, FALSE);
  256. PcdSet32S (PcdPeg0ResetGpioPad, 0);
  257. PcdSetBoolS (PcdPeg0ResetGpioActive, FALSE);
  258. PcdSet32S (PcdPeg3ResetGpioPad, 0);
  259. PcdSetBoolS (PcdPeg3ResetGpioActive, FALSE);
  260. //
  261. // PCIE RTD3 GPIO
  262. //
  263. switch (BoardId) {
  264. case BoardIdCometLakeULpddr3Rvp:
  265. PcdSet8S(PcdRootPortIndex, 4);
  266. PcdSet8S (PcdPcie0GpioSupport, PchGpio);
  267. PcdSet32S (PcdPcie0WakeGpioNo, 0);
  268. PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
  269. PcdSet32S (PcdPcie0HoldRstGpioNo, GPIO_CNL_LP_GPP_C15);
  270. PcdSetBoolS (PcdPcie0HoldRstActive, FALSE);
  271. PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
  272. PcdSet32S (PcdPcie0PwrEnableGpioNo, GPIO_CNL_LP_GPP_C14);
  273. PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
  274. PcdSet8S (PcdPcie1GpioSupport, NotSupported);
  275. PcdSet32S (PcdPcie1WakeGpioNo, 0);
  276. PcdSet8S (PcdPcie1HoldRstExpanderNo, 0);
  277. PcdSet32S (PcdPcie1HoldRstGpioNo, 0);
  278. PcdSetBoolS (PcdPcie1HoldRstActive, FALSE);
  279. PcdSet8S (PcdPcie1PwrEnableExpanderNo, 0);
  280. PcdSet32S (PcdPcie1PwrEnableGpioNo, 0);
  281. PcdSetBoolS (PcdPcie1PwrEnableActive, FALSE);
  282. PcdSet8S (PcdPcie2GpioSupport, NotSupported);
  283. PcdSet32S (PcdPcie2WakeGpioNo, 0);
  284. PcdSet8S (PcdPcie2HoldRstExpanderNo, 0);
  285. PcdSet32S (PcdPcie2HoldRstGpioNo, 0);
  286. PcdSetBoolS (PcdPcie2HoldRstActive, FALSE);
  287. PcdSet8S (PcdPcie2PwrEnableExpanderNo, 0);
  288. PcdSet32S (PcdPcie2PwrEnableGpioNo, 0);
  289. PcdSetBoolS (PcdPcie2PwrEnableActive, FALSE);
  290. break;
  291. default:
  292. PcdSet8S(PcdRootPortIndex, 0xFF);
  293. PcdSet8S (PcdPcie0GpioSupport, NotSupported);
  294. PcdSet32S (PcdPcie0WakeGpioNo, 0);
  295. PcdSet8S (PcdPcie0HoldRstExpanderNo, 0);
  296. PcdSet32S (PcdPcie0HoldRstGpioNo, 0);
  297. PcdSetBoolS (PcdPcie0HoldRstActive, FALSE);
  298. PcdSet8S (PcdPcie0PwrEnableExpanderNo, 0);
  299. PcdSet32S (PcdPcie0PwrEnableGpioNo, 0);
  300. PcdSetBoolS (PcdPcie0PwrEnableActive, FALSE);
  301. PcdSet8S (PcdPcie1GpioSupport, NotSupported);
  302. PcdSet32S (PcdPcie1WakeGpioNo, 0);
  303. PcdSet8S (PcdPcie1HoldRstExpanderNo, 0);
  304. PcdSet32S (PcdPcie1HoldRstGpioNo, 0);
  305. PcdSetBoolS (PcdPcie1HoldRstActive, FALSE);
  306. PcdSet8S (PcdPcie1PwrEnableExpanderNo, 0);
  307. PcdSet32S (PcdPcie1PwrEnableGpioNo, 0);
  308. PcdSetBoolS (PcdPcie1PwrEnableActive, FALSE);
  309. PcdSet8S (PcdPcie2GpioSupport, NotSupported);
  310. PcdSet32S (PcdPcie2WakeGpioNo, 0);
  311. PcdSet8S (PcdPcie2HoldRstExpanderNo, 0);
  312. PcdSet32S (PcdPcie2HoldRstGpioNo, 0);
  313. PcdSetBoolS (PcdPcie2HoldRstActive, FALSE);
  314. PcdSet8S (PcdPcie2PwrEnableExpanderNo, 0);
  315. PcdSet32S (PcdPcie2PwrEnableGpioNo, 0);
  316. PcdSetBoolS (PcdPcie2PwrEnableActive, FALSE);
  317. break;
  318. }
  319. return EFI_SUCCESS;
  320. }
  321. /**
  322. SA Display DDI configuration init function for PEI pre-memory phase.
  323. @param[in] BoardId An unsigned integer represent the board id.
  324. @retval EFI_SUCCESS The function completed successfully.
  325. **/
  326. EFI_STATUS
  327. SaDisplayConfigInit (
  328. IN UINT16 BoardId
  329. )
  330. {
  331. //
  332. // Update Display DDI Config
  333. //
  334. switch (BoardId) {
  335. case BoardIdCometLakeULpddr3Rvp:
  336. PcdSet32S (PcdSaDisplayConfigTable, (UINTN) mWhlErbRowDisplayDdiConfig);
  337. PcdSet16S (PcdSaDisplayConfigTableSize, sizeof (mWhlErbRowDisplayDdiConfig));
  338. break;
  339. default:
  340. break;
  341. }
  342. return EFI_SUCCESS;
  343. }