PlatformEarlyInit.c 32 KB

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  1. /** @file
  2. Copyright (c) 2004 - 2019, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. Module Name:
  5. PlatformEarlyInit.c
  6. Abstract:
  7. Do platform specific PEI stage initializations.
  8. --*/
  9. #include "PlatformEarlyInit.h"
  10. #ifdef __GNUC__
  11. #pragma GCC push_options
  12. #pragma GCC optimize ("O0")
  13. #else
  14. #pragma optimize ("", off)
  15. #endif
  16. static EFI_PEI_STALL_PPI mStallPpi = {
  17. PEI_STALL_RESOLUTION,
  18. Stall
  19. };
  20. static EFI_PEI_PPI_DESCRIPTOR mInstallStallPpi = {
  21. EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  22. &gEfiPeiStallPpiGuid,
  23. &mStallPpi
  24. };
  25. //
  26. // The reserved SMBus addresses are defined in PlatformDxe.h file.
  27. //
  28. static UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;
  29. static PEI_SMBUS_POLICY_PPI mSmbusPolicyPpi = {
  30. SMBUS_BASE_ADDRESS,
  31. SMBUS_BUS_DEV_FUNC,
  32. PLATFORM_NUM_SMBUS_RSVD_ADDRESSES,
  33. mSmbusRsvdAddresses
  34. };
  35. static EFI_PEI_PPI_DESCRIPTOR mInstallSmbusPolicyPpi = {
  36. EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  37. &gPeiSmbusPolicyPpiGuid,
  38. &mSmbusPolicyPpi
  39. };
  40. static PEI_SPEAKER_IF_PPI mSpeakerInterfacePpi = {
  41. ProgramToneFrequency,
  42. GenerateBeepTone
  43. };
  44. static EFI_PEI_PPI_DESCRIPTOR mInstallSpeakerInterfacePpi = {
  45. EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
  46. &gPeiSpeakerInterfacePpiGuid,
  47. &mSpeakerInterfacePpi
  48. };
  49. static EFI_PEI_RESET_PPI mResetPpi = { IchReset };
  50. static EFI_PEI_PPI_DESCRIPTOR mPpiList[] = {
  51. {
  52. EFI_PEI_PPI_DESCRIPTOR_PPI,
  53. &gEfiPeiMasterBootModePpiGuid,
  54. NULL
  55. },
  56. {
  57. (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
  58. &gEfiPeiResetPpiGuid,
  59. &mResetPpi
  60. }
  61. };
  62. static EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList[] = {
  63. {
  64. EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK,
  65. &gEfiEndOfPeiSignalPpiGuid,
  66. (EFI_PEIM_NOTIFY_ENTRY_POINT)EndOfPeiPpiNotifyCallback
  67. },
  68. {
  69. (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK| EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
  70. &gEfiPeiMemoryDiscoveredPpiGuid,
  71. (EFI_PEIM_NOTIFY_ENTRY_POINT)MemoryDiscoveredPpiNotifyCallback
  72. }
  73. };
  74. /**
  75. Parse the status registers for figuring out the wake-up event and save it into
  76. an GUID HOB which will be referenced later. However, modification is required
  77. to meet the chipset register definition and the practical hardware design. Thus,
  78. this is just an example.
  79. @param PeiServices pointer to the PEI Service Table
  80. @param EFI_SUCCESS Always return Success
  81. @retval None
  82. **/
  83. EFI_STATUS
  84. EFIAPI
  85. GetWakeupEventAndSaveToHob (
  86. IN CONST EFI_PEI_SERVICES **PeiServices
  87. )
  88. {
  89. UINT16 Pm1Sts;
  90. UINTN Gpe0Sts;
  91. UINTN WakeEventData;
  92. //
  93. // Read the ACPI registers
  94. //
  95. Pm1Sts = IoRead16 (ACPI_BASE_ADDRESS + R_PCH_ACPI_PM1_STS);
  96. Gpe0Sts = IoRead32 (ACPI_BASE_ADDRESS + R_PCH_ACPI_GPE0a_STS);
  97. //
  98. // Figure out the wake-up event
  99. //
  100. if ((Pm1Sts & B_PCH_ACPI_PM1_STS_PWRBTN) != 0) {
  101. WakeEventData = SMBIOS_WAKEUP_TYPE_POWER_SWITCH;
  102. } else if (((Pm1Sts & B_PCH_ACPI_PM1_STS_WAK) != 0)) {
  103. WakeEventData = SMBIOS_WAKEUP_TYPE_PCI_PME;
  104. } else if (Gpe0Sts != 0) {
  105. WakeEventData = SMBIOS_WAKEUP_TYPE_OTHERS;
  106. } else {
  107. WakeEventData = SMBIOS_WAKEUP_TYPE_UNKNOWN;
  108. }
  109. DEBUG ((EFI_D_ERROR, "ACPI Wake Status Register: %04x\n", Pm1Sts));
  110. DEBUG ((EFI_D_ERROR, "ACPI Wake Event Data: %02x\n", WakeEventData));
  111. return EFI_SUCCESS;
  112. }
  113. EFI_STATUS
  114. GetSetupVariable (
  115. IN CONST EFI_PEI_SERVICES **PeiServices,
  116. IN SYSTEM_CONFIGURATION *SystemConfiguration
  117. )
  118. {
  119. UINTN VariableSize;
  120. EFI_STATUS Status;
  121. EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable;
  122. VariableSize = sizeof (SYSTEM_CONFIGURATION);
  123. ZeroMem (SystemConfiguration, sizeof (SYSTEM_CONFIGURATION));
  124. Status = (*PeiServices)->LocatePpi (
  125. PeiServices,
  126. &gEfiPeiReadOnlyVariable2PpiGuid,
  127. 0,
  128. NULL,
  129. (void **)&Variable
  130. );
  131. ASSERT_EFI_ERROR (Status);
  132. //
  133. // Use normal setup default from NVRAM variable,
  134. // the Platform Mode (manufacturing/safe/normal) is handle in PeiGetVariable.
  135. //
  136. VariableSize = sizeof(SYSTEM_CONFIGURATION);
  137. Status = Variable->GetVariable (
  138. Variable,
  139. L"Setup",
  140. &gEfiSetupVariableGuid,
  141. NULL,
  142. &VariableSize,
  143. SystemConfiguration
  144. );
  145. if (EFI_ERROR (Status)) {
  146. return Status;
  147. }
  148. if (VariableSize != sizeof(SYSTEM_CONFIGURATION)) {
  149. //
  150. // The setup variable is corrupted
  151. //
  152. return EFI_NOT_FOUND;
  153. }
  154. return EFI_SUCCESS;
  155. }
  156. EFI_STATUS
  157. VlvPolicyInit (
  158. IN CONST EFI_PEI_SERVICES **PeiServices,
  159. IN SYSTEM_CONFIGURATION *SystemConfiguration
  160. )
  161. {
  162. EFI_STATUS Status;
  163. EFI_PEI_PPI_DESCRIPTOR *mVlvPolicyPpiDesc;
  164. VLV_POLICY_PPI *mVlvPolicyPpi;
  165. Status = (*PeiServices)->AllocatePool(
  166. PeiServices,
  167. sizeof (EFI_PEI_PPI_DESCRIPTOR),
  168. (void **)&mVlvPolicyPpiDesc
  169. );
  170. ASSERT_EFI_ERROR (Status);
  171. Status = (*PeiServices)->AllocatePool(
  172. PeiServices,
  173. sizeof (VLV_POLICY_PPI),
  174. (void **)&mVlvPolicyPpi
  175. );
  176. ASSERT_EFI_ERROR (Status);
  177. //
  178. // Initialize PPI
  179. //
  180. (*PeiServices)->SetMem ((VOID *)mVlvPolicyPpi, sizeof (VLV_POLICY_PPI), 0);
  181. mVlvPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
  182. mVlvPolicyPpiDesc->Guid = &gVlvPolicyPpiGuid;
  183. mVlvPolicyPpiDesc->Ppi = mVlvPolicyPpi;
  184. mVlvPolicyPpi->GtConfig.PrimaryDisplay = SystemConfiguration->PrimaryVideoAdaptor;
  185. mVlvPolicyPpi->GtConfig.IgdDvmt50PreAlloc = SystemConfiguration->IgdDvmt50PreAlloc;
  186. mVlvPolicyPpi->GtConfig.ApertureSize = SystemConfiguration->IgdApertureSize;
  187. mVlvPolicyPpi->GtConfig.GttSize = SystemConfiguration->GTTSize;
  188. if (SystemConfiguration->PrimaryVideoAdaptor != 2) {
  189. mVlvPolicyPpi->GtConfig.InternalGraphics = SystemConfiguration->Igd;
  190. } else {
  191. mVlvPolicyPpi->GtConfig.InternalGraphics = 0;
  192. }
  193. mVlvPolicyPpi->GtConfig.IgdTurboEn = 1;
  194. mVlvPolicyPpi->PlatformData.FastBoot = SystemConfiguration->FastBoot;
  195. mVlvPolicyPpi->PlatformData.DynSR = 1;
  196. DEBUG ((EFI_D_ERROR, "Setup Option ISPEn: 0x%x\n", SystemConfiguration->ISPEn));
  197. mVlvPolicyPpi->ISPEn = SystemConfiguration->ISPEn;
  198. DEBUG ((EFI_D_ERROR, "Setup Option ISPDevSel: 0x%x\n", SystemConfiguration->ISPDevSel));
  199. mVlvPolicyPpi->ISPPciDevConfig = SystemConfiguration->ISPDevSel;
  200. if (SystemConfiguration->ISPEn == 0) {
  201. mVlvPolicyPpi->ISPPciDevConfig = 0;
  202. DEBUG ((EFI_D_ERROR, "Update Setup Option ISPDevSel: 0x%x\n", mVlvPolicyPpi->ISPPciDevConfig));
  203. }
  204. Status = (*PeiServices)->InstallPpi(
  205. PeiServices,
  206. mVlvPolicyPpiDesc
  207. );
  208. ASSERT_EFI_ERROR (Status);
  209. return EFI_SUCCESS;
  210. }
  211. EFI_STATUS
  212. ConfigureSoCGpio (
  213. IN SYSTEM_CONFIGURATION *SystemConfiguration
  214. )
  215. {
  216. DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------start\n"));
  217. if (SystemConfiguration->eMMCBootMode== 1) {// Auto detection mode
  218. DEBUG ((EFI_D_ERROR, "Auto detection mode------------start\n"));
  219. //
  220. //Silicon Steppings
  221. //
  222. switch (PchStepping()) {
  223. case PchA0: // SOC A0 and A1
  224. case PchA1:
  225. DEBUG ((EFI_D_ERROR, "SOC A0/A1: eMMC 4.41 GPIO Configuration\n"));
  226. SystemConfiguration->LpsseMMCEnabled = 1;
  227. SystemConfiguration->LpsseMMC45Enabled = 0;
  228. break;
  229. case PchB0: // SOC B0 and later
  230. default:
  231. DEBUG ((EFI_D_ERROR, "SOC B0 and later: eMMC 4.5 GPIO Configuration\n"));
  232. SystemConfiguration->LpsseMMCEnabled = 0;
  233. SystemConfiguration->LpsseMMC45Enabled = 1;
  234. break;
  235. }
  236. } else if (SystemConfiguration->eMMCBootMode == 2) { // eMMC 4.41
  237. DEBUG ((EFI_D_ERROR, "Force to eMMC 4.41 GPIO Configuration\n"));
  238. SystemConfiguration->LpsseMMCEnabled = 1;
  239. SystemConfiguration->LpsseMMC45Enabled = 0;
  240. } else if (SystemConfiguration->eMMCBootMode == 3) { // eMMC 4.5
  241. DEBUG ((EFI_D_ERROR, "Force to eMMC 4.5 GPIO Configuration\n"));
  242. SystemConfiguration->LpsseMMCEnabled = 0;
  243. SystemConfiguration->LpsseMMC45Enabled = 1;
  244. } else { // Disable eMMC controllers
  245. DEBUG ((EFI_D_ERROR, "Disable eMMC GPIO controllers\n"));
  246. SystemConfiguration->LpsseMMCEnabled = 0;
  247. SystemConfiguration->LpsseMMC45Enabled = 0;
  248. }
  249. /*
  250. 20.1.1 EMMC
  251. SDMMC1_CLK - write 0x2003ED01 to IOBASE + 0x03E0
  252. SDMMC1_CMD - write 0x2003EC81 to IOBASE + 0x0390
  253. SDMMC1_D0 - write 0x2003EC81 to IOBASE + 0x03D0
  254. SDMMC1_D1 - write 0x2003EC81 to IOBASE + 0x0400
  255. SDMMC1_D2 - write 0x2003EC81 to IOBASE + 0x03B0
  256. SDMMC1_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0360
  257. MMC1_D4_SD_WE - write 0x2003EC81 to IOBASE + 0x0380
  258. MMC1_D5 - write 0x2003EC81 to IOBASE + 0x03C0
  259. MMC1_D6 - write 0x2003EC81 to IOBASE + 0x0370
  260. MMC1_D7 - write 0x2003EC81 to IOBASE + 0x03F0
  261. MMC1_RESET_B - write 0x2003ED01 to IOBASE + 0x0330
  262. */
  263. if (SystemConfiguration->LpsseMMCEnabled== 1) {
  264. MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED01); //EMMC 4.41
  265. MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC81);
  266. MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC81);
  267. MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC81);
  268. MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC81);
  269. MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC81);
  270. MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC81);
  271. MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC81);
  272. MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC81);
  273. MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC81);
  274. MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED01);
  275. }
  276. /*
  277. eMMC 4.5 controller
  278. SDMMC1_CLK - write 0x2003ED03 to IOBASE + 0x03E0
  279. SDMMC1_CMD - write 0x2003EC83 to IOBASE + 0x0390
  280. SDMMC1_D0 - write 0x2003EC83 to IOBASE + 0x03D0
  281. SDMMC1_D1 - write 0x2003EC83 to IOBASE + 0x0400
  282. SDMMC1_D2 - write 0x2003EC83 to IOBASE + 0x03B0
  283. SDMMC1_D3_CD_B - write 0x2003EC83 to IOBASE + 0x0360
  284. MMC1_D4_SD_WE - write 0x2003EC83 to IOBASE + 0x0380
  285. MMC1_D5 - write 0x2003EC83 to IOBASE + 0x03C0
  286. MMC1_D6 - write 0x2003EC83 to IOBASE + 0x0370
  287. MMC1_D7 - write 0x2003EC83 to IOBASE + 0x03F0
  288. MMC1_RESET_B - write 0x2003ED03 to IOBASE + 0x0330
  289. */
  290. if (SystemConfiguration->LpsseMMC45Enabled== 1) {
  291. MmioWrite32 (IO_BASE_ADDRESS + 0x03E0, 0x2003ED03); // EMMC 4.5
  292. MmioWrite32 (IO_BASE_ADDRESS + 0x0390, 0x2003EC83);
  293. MmioWrite32 (IO_BASE_ADDRESS + 0x03D0, 0x2003EC83);
  294. MmioWrite32 (IO_BASE_ADDRESS + 0x0400, 0x2003EC83);
  295. MmioWrite32 (IO_BASE_ADDRESS + 0x03B0, 0x2003EC83);
  296. MmioWrite32 (IO_BASE_ADDRESS + 0x0360, 0x2003EC83);
  297. MmioWrite32 (IO_BASE_ADDRESS + 0x0380, 0x2003EC83);
  298. MmioWrite32 (IO_BASE_ADDRESS + 0x03C0, 0x2003EC83);
  299. MmioWrite32 (IO_BASE_ADDRESS + 0x0370, 0x2003EC83);
  300. MmioWrite32 (IO_BASE_ADDRESS + 0x03F0, 0x2003EC83);
  301. MmioWrite32 (IO_BASE_ADDRESS + 0x0330, 0x2003ED03);
  302. }
  303. //
  304. // Change GPIOC_0 setting to allow MMIO access under Android.
  305. //
  306. IoWrite32 (GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL,
  307. (IoRead32(GPIO_BASE_ADDRESS + R_PCH_GPIO_SC_USE_SEL) & (UINT32)~BIT0));
  308. DEBUG ((EFI_D_ERROR, "ConfigureSoCGpio------------end\n"));
  309. return EFI_SUCCESS;
  310. }
  311. EFI_STATUS
  312. MeasuredBootInit (
  313. IN CONST EFI_PEI_SERVICES **PeiServices,
  314. IN SYSTEM_CONFIGURATION *SystemConfiguration
  315. )
  316. {
  317. if (SystemConfiguration->MeasuredBootEnable) {
  318. PcdSetBool (PcdMeasuredBootEnable, TRUE);
  319. } else {
  320. PcdSetBool (PcdMeasuredBootEnable, FALSE);
  321. }
  322. return EFI_SUCCESS;
  323. }
  324. EFI_STATUS
  325. ConfigureLpssAndSccGpio (
  326. IN SYSTEM_CONFIGURATION *SystemConfiguration,
  327. IN EFI_PLATFORM_INFO_HOB *PlatformInfo
  328. )
  329. {
  330. /*One time configuration to each GPIO controller PSB_CONF register should be done before starting pad configuration:
  331. GPIO SCORE - write 0x01001002 to IOBASE + 0x0700
  332. GPIO NCORE - write 0x01001002 to IOBASE + 0x0F00
  333. GPIO SSUS - write 0x01001002 to IOBASE + 0x1700
  334. */
  335. DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------start\n"));
  336. /*
  337. 19.1.1 PWM0
  338. PWM0 - write 0x2003CD01 to IOBASE + 0x00A0
  339. 19.1.2 PWM1
  340. PWM0 - write 0x2003CD01 to IOBASE + 0x00B0
  341. */
  342. if (SystemConfiguration->LpssPwm0Enabled== 1) {
  343. MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD01);
  344. } else if (SystemConfiguration->LpssPwm0Enabled== 0) {
  345. MmioWrite32 (IO_BASE_ADDRESS + 0x00A0, 0x2003CD00);
  346. }
  347. if (SystemConfiguration->LpssPwm1Enabled== 1) {
  348. MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CC01);
  349. } else if (SystemConfiguration->LpssPwm1Enabled== 0) {
  350. MmioWrite32 (IO_BASE_ADDRESS + 0x00B0, 0x2003CD00);
  351. }
  352. /*
  353. 19.1.3 UART1
  354. UART1_RXD-L - write 0x2003CC81 to IOBASE + 0x0020
  355. UART1_TXD-0 - write 0x2003CC81 to IOBASE + 0x0010
  356. UART1_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0000
  357. UART1_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0040
  358. */
  359. if (SystemConfiguration->LpssHsuart0Enabled== 1) {
  360. MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC81); // uart1
  361. MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC81);
  362. if (SystemConfiguration->LpssHsuart0FlowControlEnabled== 0) {
  363. DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[0]\n"));
  364. MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC80);
  365. MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC80);
  366. } else {
  367. DEBUG ((EFI_D_ERROR, "LpssHsuart0FlowControlEnabled[1]\n"));
  368. MmioWrite32 (IO_BASE_ADDRESS + 0x0000, 0x2003CC81);
  369. MmioWrite32 (IO_BASE_ADDRESS + 0x0040, 0x2003CC01);//W/A HSD 4752617 0x2003CC81
  370. }
  371. } else if (SystemConfiguration->LpssHsuart0Enabled== 0) {
  372. MmioWrite32 (IO_BASE_ADDRESS + 0x0020, 0x2003CC80); // uart1
  373. MmioWrite32 (IO_BASE_ADDRESS + 0x0010, 0x2003CC80);
  374. }
  375. /*
  376. 19.1.4 UART2
  377. UART2_RTS_B-1 - write 0x2003CC81 to IOBASE + 0x0090
  378. UART2_CTS_B-H - write 0x2003CC81 to IOBASE + 0x0080
  379. UART2_RXD-H - write 0x2003CC81 to IOBASE + 0x0060
  380. UART2_TXD-0 - write 0x2003CC81 to IOBASE + 0x0070
  381. */
  382. if (SystemConfiguration->LpssHsuart1Enabled== 1) {
  383. MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC81);
  384. MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC81);
  385. if (SystemConfiguration->LpssHsuart1FlowControlEnabled== 0) {
  386. DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[0]\n"));
  387. MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC80); // UART2_RTS_B
  388. MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC80); // UART2_CTS_B
  389. } else {
  390. DEBUG ((EFI_D_ERROR, "LpssHsuart1FlowControlEnabled[1]\n"));
  391. MmioWrite32 (IO_BASE_ADDRESS + 0x0090, 0x2003CC81); // uart2
  392. MmioWrite32 (IO_BASE_ADDRESS + 0x0080, 0x2003CC01); //W/A HSD 4752617 0x2003CC81
  393. }
  394. } else if (SystemConfiguration->LpssHsuart1Enabled== 0) {
  395. MmioWrite32 (IO_BASE_ADDRESS + 0x0060, 0x2003CC80);
  396. MmioWrite32 (IO_BASE_ADDRESS + 0x0070, 0x2003CC80);
  397. }
  398. /*
  399. 19.1.5 SPI
  400. SPI1_CS0_B - write 0x2003CC81 to IOBASE + 0x0110
  401. SPI1_CLK - write 0x2003CD01 to IOBASE + 0x0100
  402. SPI1_MOSI - write 0x2003CC81 to IOBASE + 0x0130
  403. SPI1_MISO - write 0x2003CC81 to IOBASE + 0x0120
  404. */
  405. if (SystemConfiguration->LpssSpiEnabled== 1) {
  406. MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003CC81); // SPI
  407. MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003CD01);
  408. MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003CC81);
  409. MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003CC81);
  410. } else if (SystemConfiguration->LpssSpiEnabled== 0) {
  411. MmioWrite32 (IO_BASE_ADDRESS + 0x0110, 0x2003cc80);
  412. MmioWrite32 (IO_BASE_ADDRESS + 0x0100, 0x2003cc80);
  413. MmioWrite32 (IO_BASE_ADDRESS + 0x0130, 0x2003cc80);
  414. MmioWrite32 (IO_BASE_ADDRESS + 0x0120, 0x2003cc80);
  415. }
  416. /*
  417. 19.1.6 I2C0
  418. I2C0_SDA-OD-O - write 0x2003CC81 to IOBASE + 0x0210
  419. I2C0_SCL-OD-O - write 0x2003CC81 to IOBASE + 0x0200
  420. */
  421. if (SystemConfiguration->LpssI2C0Enabled== 1) {
  422. MmioWrite32 (IO_BASE_ADDRESS + 0x0210, 0x2003C881);
  423. MmioWrite32 (IO_BASE_ADDRESS + 0x0200, 0x2003C881);
  424. }
  425. /*
  426. 19.1.7 I2C1
  427. I2C1_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01F0
  428. I2C1_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01E0
  429. */
  430. if (SystemConfiguration->LpssI2C1Enabled== 1) {
  431. MmioWrite32 (IO_BASE_ADDRESS + 0x01F0, 0x2003C881);
  432. MmioWrite32 (IO_BASE_ADDRESS + 0x01E0, 0x2003C881);
  433. }
  434. /*
  435. 19.1.8 I2C2
  436. I2C2_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01D0
  437. I2C2_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01B0
  438. */
  439. if (SystemConfiguration->LpssI2C2Enabled== 1) {
  440. MmioWrite32 (IO_BASE_ADDRESS + 0x01D0, 0x2003C881);
  441. MmioWrite32 (IO_BASE_ADDRESS + 0x01B0, 0x2003C881);
  442. }
  443. /*
  444. 19.1.9 I2C3
  445. I2C3_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0190
  446. I2C3_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x01C0
  447. */
  448. if (SystemConfiguration->LpssI2C3Enabled== 1) {
  449. MmioWrite32 (IO_BASE_ADDRESS + 0x0190, 0x2003C881);
  450. MmioWrite32 (IO_BASE_ADDRESS + 0x01C0, 0x2003C881);
  451. }
  452. /*
  453. 19.1.10 I2C4
  454. I2C4_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x01A0
  455. I2C4_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0170
  456. */
  457. if (SystemConfiguration->LpssI2C4Enabled== 1) {
  458. MmioWrite32 (IO_BASE_ADDRESS + 0x01A0, 0x2003C881);
  459. MmioWrite32 (IO_BASE_ADDRESS + 0x0170, 0x2003C881);
  460. }
  461. /*
  462. 19.1.11 I2C5
  463. I2C5_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0150
  464. I2C5_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0140
  465. */
  466. //touch 1.7M support on i2c5(from 0) need 2k PULL-UP.
  467. if (SystemConfiguration->LpssI2C5Enabled== 1) {
  468. MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C881);
  469. MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C881);
  470. } else if(SystemConfiguration->LpssI2C5Enabled== 0) {
  471. MmioWrite32 (IO_BASE_ADDRESS + 0x0150, 0x2003C880);
  472. MmioWrite32 (IO_BASE_ADDRESS + 0x0140, 0x2003C880);
  473. }
  474. /*
  475. 19.1.12 I2C6
  476. I2C6_SDA-OD-O/I - write 0x2003CC81 to IOBASE + 0x0180
  477. I2C6_SCL-OD-O/I - write 0x2003CC81 to IOBASE + 0x0160
  478. */
  479. if (SystemConfiguration->LpssI2C6Enabled== 1) {
  480. MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C881);
  481. MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C881);
  482. } else if (SystemConfiguration->LpssI2C6Enabled== 0) {
  483. MmioWrite32 (IO_BASE_ADDRESS + 0x0180, 0x2003C880);
  484. MmioWrite32 (IO_BASE_ADDRESS + 0x0160, 0x2003C880);
  485. }
  486. /*
  487. 20.1.2 SDIO
  488. SDMMC2_CLK - write 0x2003ED01 to IOBASE + 0x0320
  489. SDMMC2_CMD - write 0x2003EC81 to IOBASE + 0x0300
  490. SDMMC2_D0 - write 0x2003EC81 to IOBASE + 0x0350
  491. SDMMC2_D1 - write 0x2003EC81 to IOBASE + 0x02F0
  492. SDMMC2_D2 - write 0x2003EC81 to IOBASE + 0x0340
  493. SDMMC2_D3_CD_B - write 0x2003EC81 to IOBASE + 0x0310
  494. */
  495. if (SystemConfiguration->LpssSdioEnabled== 1) {
  496. MmioWrite32 (IO_BASE_ADDRESS + 0x0320, 0x2003ED01);//SDIO
  497. MmioWrite32 (IO_BASE_ADDRESS + 0x0300, 0x2003EC81);
  498. MmioWrite32 (IO_BASE_ADDRESS + 0x0350, 0x2003EC81);
  499. MmioWrite32 (IO_BASE_ADDRESS + 0x02F0, 0x2003EC81);
  500. MmioWrite32 (IO_BASE_ADDRESS + 0x0340, 0x2003EC81);
  501. MmioWrite32 (IO_BASE_ADDRESS + 0x0310, 0x2003EC81);
  502. }
  503. /*
  504. 20.1.3 SD Card
  505. SDMMC3_1P8_EN - write 0x2003CD01 to IOBASE + 0x03F0
  506. SDMMC3_CD_B - write 0x2003CC81 to IOBASE + 0x03A0
  507. SDMMC3_CLK - write 0x2003CD01 to IOBASE + 0x02B0
  508. SDMMC3_CMD - write 0x2003CC81 to IOBASE + 0x02C0
  509. SDMMC3_D0 - write 0x2003CC81 to IOBASE + 0x02E0
  510. SDMMC3_D1 - write 0x2003CC81 to IOBASE + 0x0290
  511. SDMMC3_D2 - write 0x2003CC81 to IOBASE + 0x02D0
  512. SDMMC3_D3 - write 0x2003CC81 to IOBASE + 0x02A0
  513. SDMMC3_PWR_EN_B - write 0x2003CC81 to IOBASE + 0x0690
  514. SDMMC3_WP - write 0x2003CC82 to IOBASE + 0x0160
  515. */
  516. if (SystemConfiguration->LpssSdcardEnabled == 1) {
  517. if (!((PlatformInfo->BoardId == BOARD_ID_BL_FFRD && PlatformInfo->BoardRev== PR11) && (SystemConfiguration->CfioPnpSettings == 1))) {
  518. MmioWrite32 (IO_BASE_ADDRESS + 0x05F0, 0x2003CD01);//SDCARD
  519. MmioWrite32 (IO_BASE_ADDRESS + 0x02B0, 0x2003CD01);
  520. MmioWrite32 (IO_BASE_ADDRESS + 0x02C0, 0x2003CC81);
  521. MmioWrite32 (IO_BASE_ADDRESS + 0x02E0, 0x2003CC81);
  522. MmioWrite32 (IO_BASE_ADDRESS + 0x0290, 0x2003CC81);
  523. MmioWrite32 (IO_BASE_ADDRESS + 0x02D0, 0x2003CC81);
  524. MmioWrite32 (IO_BASE_ADDRESS + 0x02A0, 0x2003CC81);
  525. MmioWrite32 (IO_BASE_ADDRESS + 0x0690, 0x2003CC81);
  526. MmioWrite32 (IO_BASE_ADDRESS + 0x0650, 0x2003CC82); //GPIOC_7 set to WP Pin
  527. }
  528. }
  529. DEBUG ((EFI_D_ERROR, "ConfigureLpssAndSccGpio------------end\n"));
  530. return EFI_SUCCESS;
  531. }
  532. EFI_STATUS
  533. ConfigureLpeGpio (
  534. IN SYSTEM_CONFIGURATION *SystemConfiguration
  535. )
  536. {
  537. DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------start\n"));
  538. if (SystemConfiguration->PchAzalia == 0) {
  539. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x220, (UINT32)~(0x7), (UINT32) (0x01));
  540. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x250, (UINT32)~(0x7), (UINT32) (0x01));
  541. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x240, (UINT32)~(0x7), (UINT32) (0x01));
  542. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x260, (UINT32)~(0x7), (UINT32) (0x01));
  543. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x270, (UINT32)~(0x7), (UINT32) (0x01));
  544. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x230, (UINT32)~(0x7), (UINT32) (0x01));
  545. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x280, (UINT32)~(0x7), (UINT32) (0x01));
  546. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x540, (UINT32)~(0x7), (UINT32) (0x01));
  547. }
  548. DEBUG ((EFI_D_ERROR, "ConfigureLpeGpio------------end\n"));
  549. return EFI_SUCCESS;
  550. }
  551. EFI_STATUS
  552. ConfigureSciSmiGpioRout (
  553. IN EFI_PLATFORM_INFO_HOB *PlatformInfo)
  554. {
  555. UINT32 GPI_Routing;
  556. GPI_Routing = MmioRead32 (PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT);
  557. //
  558. // For FAB3, Route GPIO_CORE 0 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI
  559. //
  560. if(PlatformInfo->BoardRev == 3) {
  561. GPI_Routing = GPI_Routing & 0xfffc3ffc;
  562. GPI_Routing = GPI_Routing | 0x00024002;
  563. }
  564. //
  565. // For FAB2/1, Route GPIO_CORE 7 to cause Runtime SCI, GPIO_SUS 0 to cause Wake SCI and GPIO_SUS 7 to cause EXTSMI
  566. //
  567. else {
  568. GPI_Routing = GPI_Routing & 0x3fff3ffc;
  569. GPI_Routing = GPI_Routing | 0x80004002;
  570. }
  571. MmioWrite32((PMC_BASE_ADDRESS + R_PCH_PMC_GPI_ROUT), GPI_Routing);
  572. return EFI_SUCCESS;
  573. }
  574. EFI_STATUS
  575. ConfigureMipiCsi (
  576. VOID)
  577. {
  578. //
  579. //Configure the platform clock for MIPI-CSI usage
  580. //PLT_CLK0
  581. //
  582. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x6a0, (UINT32)~(0x7), (UINT32) (0x01));
  583. //
  584. //PLT_CLK1
  585. //
  586. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x570, (UINT32)~(0x7), (UINT32) (0x01));
  587. //
  588. //PLT_CLK2
  589. //
  590. MmioAndThenOr32 (IO_BASE_ADDRESS + 0x5B0, (UINT32)~(0x7), (UINT32) (0x01));
  591. return EFI_SUCCESS;
  592. }
  593. EFI_STATUS
  594. ConfigureUSBULPI (
  595. VOID)
  596. {
  597. //
  598. //Configure USB ULPI
  599. //USB_ULPI_0_CLK
  600. //
  601. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x338, (UINT32)~(0x7), (UINT32) (GPI));
  602. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x330, (UINT32)~(0x187), (UINT32) (0x101));
  603. //
  604. //USB_ULPI_0_DATA0
  605. //
  606. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x388, (UINT32)~(0x7), (UINT32) (GPI));
  607. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x380, (UINT32)~(0x187), (UINT32) (0x101));
  608. //
  609. //USB_ULPI_0_DATA1
  610. //
  611. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x368, (UINT32)~(0x7), (UINT32) (GPI));
  612. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x360, (UINT32)~(0x187), (UINT32) (0x101));
  613. //
  614. //USB_ULPI_0_DATA2
  615. //
  616. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x318, (UINT32)~(0x7), (UINT32) (GPI));
  617. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x310, (UINT32)~(0x187), (UINT32) (0x101));
  618. //
  619. //USB_ULPI_0_DATA3
  620. //
  621. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x378, (UINT32)~(0x7), (UINT32) (GPI));
  622. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x370, (UINT32)~(0x187), (UINT32) (0x101));
  623. //
  624. //USB_ULPI_0_DATA4
  625. //
  626. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x308, (UINT32)~(0x7), (UINT32) (GPI));
  627. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x300, (UINT32)~(0x187), (UINT32) (0x101));
  628. //
  629. //USB_ULPI_0_DATA5
  630. //
  631. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x398, (UINT32)~(0x7), (UINT32) (GPI));
  632. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x390, (UINT32)~(0x187), (UINT32) (0x101));
  633. //
  634. //USB_ULPI_0_DATA6
  635. //
  636. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x328, (UINT32)~(0x7), (UINT32) (GPI));
  637. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x320, (UINT32)~(0x187), (UINT32) (0x101));
  638. //
  639. //USB_ULPI_0_DATA7
  640. //
  641. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a8, (UINT32)~(0x7), (UINT32) (GPI));
  642. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3a0, (UINT32)~(0x187), (UINT32) (0x101));
  643. //
  644. //USB_ULPI_0_DIR
  645. //
  646. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x348, (UINT32)~(0x7), (UINT32) (GPI));
  647. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x340, (UINT32)~(0x187), (UINT32) (0x81));
  648. //
  649. //USB_ULPI_0_NXT
  650. //
  651. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x358, (UINT32)~(0x7), (UINT32) (GPI));
  652. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x350, (UINT32)~(0x187), (UINT32) (0x101));
  653. //
  654. //USB_ULPI_0_STP
  655. //
  656. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b8, (UINT32)~(0x7), (UINT32) (GPI));
  657. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x3b0, (UINT32)~(0x187), (UINT32) (0x81));
  658. //
  659. //USB_ULPI_0_REFCLK
  660. //
  661. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x288, (UINT32)~(0x7), (UINT32) (GPI));
  662. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x280, (UINT32)~(0x187), (UINT32) (0x101));
  663. return EFI_SUCCESS;
  664. }
  665. EFI_STATUS
  666. DisableRTD3 (
  667. VOID)
  668. {
  669. //
  670. //Disable RTD3
  671. //
  672. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x210, (UINT32)~(0x0f000007), (UINT32) (0x00));
  673. MmioAndThenOr32 (IO_BASE_ADDRESS + GPIO_SSUS_OFFSET + 0x1e0, (UINT32)~(0x0f000007), (UINT32) (0x00));
  674. return EFI_SUCCESS;
  675. }
  676. /**
  677. Platform specific initializations in stage1.
  678. @param FfsHeader Pointer to the PEIM FFS file header.
  679. @param PeiServices General purpose services available to every PEIM.
  680. @retval EFI_SUCCESS Operation completed successfully.
  681. @retval Otherwise Platform initialization failed.
  682. **/
  683. EFI_STATUS
  684. EFIAPI
  685. PlatformEarlyInitEntry (
  686. IN EFI_PEI_FILE_HANDLE FileHandle,
  687. IN CONST EFI_PEI_SERVICES **PeiServices
  688. )
  689. {
  690. EFI_STATUS Status;
  691. SYSTEM_CONFIGURATION SystemConfiguration;
  692. EFI_PLATFORM_INFO_HOB *PlatformInfo;
  693. EFI_PEI_HOB_POINTERS Hob;
  694. EFI_PLATFORM_CPU_INFO PlatformCpuInfo;
  695. //
  696. // Initialize SmbusPolicy PPI
  697. //
  698. Status = (*PeiServices)->InstallPpi(PeiServices, &mInstallSmbusPolicyPpi);
  699. ASSERT_EFI_ERROR (Status);
  700. //
  701. // Initialize Stall PPIs
  702. //
  703. Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallStallPpi);
  704. ASSERT_EFI_ERROR (Status);
  705. //
  706. // Initialize platform PPIs
  707. //
  708. Status = (*PeiServices)->InstallPpi (PeiServices, &mInstallSpeakerInterfacePpi);
  709. ASSERT_EFI_ERROR (Status);
  710. //
  711. // Variable initialization
  712. //
  713. ZeroMem(&PlatformCpuInfo, sizeof(EFI_PLATFORM_CPU_INFO));
  714. //
  715. // Set the some PCI and chipset range as UC
  716. // And align to 1M at leaset
  717. //
  718. Hob.Raw = GetFirstGuidHob (&gEfiPlatformInfoGuid);
  719. ASSERT (Hob.Raw != NULL);
  720. PlatformInfo = GET_GUID_HOB_DATA(Hob.Raw);
  721. //
  722. // Initialize PlatformInfo HOB
  723. //
  724. MultiPlatformInfoInit(PeiServices, PlatformInfo);
  725. //
  726. // Do basic MCH init
  727. //
  728. MchInit (PeiServices);
  729. //
  730. // Set the new boot mode
  731. //
  732. Status = UpdateBootMode (PeiServices, PlatformInfo);
  733. ASSERT_EFI_ERROR (Status);
  734. SetPlatformBootMode (PeiServices, PlatformInfo);
  735. //
  736. // Get setup variable. This can only be done after BootMode is updated
  737. //
  738. Status = GetSetupVariable (PeiServices, &SystemConfiguration);
  739. if (EFI_ERROR (Status)) {
  740. DEBUG ((DEBUG_INFO, "PlatformEarlyInitEntry: Setup Variable does not exist.\n"));
  741. DEBUG ((DEBUG_INFO, "PlatformEarlyInitEntry: Set PcdNvStoreDefaultId to STANDARD\n"));
  742. //
  743. // Set the default NV store to STANDARD defaults
  744. //
  745. PcdSet16S (PcdSetNvStoreDefaultId, 0x0000);
  746. //
  747. // Get setup variable. Must succeed at this point.
  748. //
  749. Status = GetSetupVariable (PeiServices, &SystemConfiguration);
  750. ASSERT_EFI_ERROR (Status);
  751. }
  752. CheckOsSelection(PeiServices, &SystemConfiguration);
  753. //
  754. // Update PlatformInfo HOB according to setup variable
  755. //
  756. PlatformInfoUpdate(PeiServices, PlatformInfo, &SystemConfiguration);
  757. InitializePlatform (PeiServices, PlatformInfo, &SystemConfiguration);
  758. //
  759. // Initialize VlvPolicy PPI
  760. //
  761. Status = VlvPolicyInit (PeiServices, &SystemConfiguration);
  762. ASSERT_EFI_ERROR (Status);
  763. //
  764. // Soc specific GPIO setting
  765. //
  766. ConfigureSoCGpio(&SystemConfiguration);
  767. //
  768. // Baylake Board specific.
  769. //
  770. if (PlatformInfo->BoardId == BOARD_ID_BL_RVP ||
  771. PlatformInfo->BoardId == BOARD_ID_BL_FFRD ||
  772. PlatformInfo->BoardId == BOARD_ID_BL_FFRD8 ||
  773. PlatformInfo->BoardId == BOARD_ID_BL_RVP_DDR3L ||
  774. PlatformInfo->BoardId == BOARD_ID_BL_STHI ||
  775. PlatformInfo->BoardId == BOARD_ID_BB_RVP ||
  776. PlatformInfo->BoardId == BOARD_ID_BS_RVP ||
  777. PlatformInfo->BoardId == BOARD_ID_MINNOW2 ||
  778. PlatformInfo->BoardId == BOARD_ID_MINNOW2_TURBOT||
  779. PlatformInfo->BoardId == BOARD_ID_CVH) {
  780. ConfigureLpssAndSccGpio(&SystemConfiguration, PlatformInfo);
  781. }
  782. //
  783. // Configure LPE
  784. // Alpine Valley and Bayley Bay board specific
  785. //
  786. ConfigureLpeGpio(&SystemConfiguration);
  787. //
  788. // Bayley Bay Board specific.
  789. //
  790. ConfigureSciSmiGpioRout(PlatformInfo);
  791. if (SystemConfiguration.LpssI2C3Enabled == 1) {
  792. ConfigureMipiCsi();
  793. }
  794. //
  795. // Do basic CPU init
  796. //
  797. Status = PlatformCpuInit (PeiServices, &SystemConfiguration, &PlatformCpuInfo);
  798. //
  799. // Perform basic SSA related platform initialization
  800. //
  801. PlatformSsaInit (&SystemConfiguration,PeiServices);
  802. //
  803. // Do basic PCH init
  804. //
  805. Status = PlatformPchInit (&SystemConfiguration, PeiServices, PlatformInfo->PlatformType);
  806. ASSERT_EFI_ERROR (Status);
  807. //
  808. // Initialize platform PPIs
  809. //
  810. Status = (*PeiServices)->InstallPpi (PeiServices, &mPpiList[0]);
  811. ASSERT_EFI_ERROR (Status);
  812. if (PlatformInfo->BoardId != BOARD_ID_CVH) {
  813. InstallPlatformClocksNotify (PeiServices);
  814. InstallPlatformSysCtrlGPIONotify(PeiServices);
  815. }
  816. //
  817. // Initialize platform PPIs
  818. //
  819. Status = (*PeiServices)->NotifyPpi(PeiServices, &mNotifyList[0]);
  820. ASSERT_EFI_ERROR (Status);
  821. //
  822. // Initialize Measured Boot
  823. //
  824. Status = MeasuredBootInit (PeiServices, &SystemConfiguration);
  825. ASSERT_EFI_ERROR (Status);
  826. return Status;
  827. }
  828. EFI_STATUS
  829. EFIAPI
  830. CpuOnlyReset (
  831. IN CONST EFI_PEI_SERVICES **PeiServices
  832. )
  833. {
  834. // MsgBus32Write(CDV_UNIT_PUNIT, PUNIT_CPU_RST, 0x01)
  835. #ifdef __GNUC__
  836. __asm__
  837. (
  838. "xorl %ecx, %ecx\n"
  839. "1:hlt; hlt; hlt\n"
  840. "jmp 1b\n"
  841. );
  842. #else
  843. _asm {
  844. xor ecx, ecx
  845. HltLoop:
  846. hlt
  847. hlt
  848. hlt
  849. loop HltLoop
  850. }
  851. #endif
  852. //
  853. // If we get here we need to mark it as a failure.
  854. //
  855. return EFI_UNSUPPORTED;
  856. }
  857. #ifdef __GNUC__
  858. #pragma GCC pop_options
  859. #else
  860. #pragma optimize ("", on)
  861. #endif