TbtSmiHandler.h 3.4 KB

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  1. /** @file
  2. Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
  3. SPDX-License-Identifier: BSD-2-Clause-Patent
  4. **/
  5. #ifndef _TBT_SMI_HANDLER_H_
  6. #define _TBT_SMI_HANDLER_H_
  7. #include <Library/TbtCommonLib.h>
  8. #include <Library/IoLib.h>
  9. #include <IndustryStandard/Pci.h>
  10. #ifdef PROGRESS_CODE
  11. #undef PROGRESS_CODE
  12. #endif
  13. #define MAX_TBT_DEPTH 6
  14. #define P2P_BRIDGE (((PCI_CLASS_BRIDGE) << 8) | (PCI_CLASS_BRIDGE_P2P))
  15. #define BAR_ALIGN(v, a) ((((v) - 1) | (a)) + 1)
  16. #define CMD_BUS_MASTER BIT2
  17. #define CMD_BM_IO (CMD_BUS_MASTER | BIT0)
  18. #define CMD_BM_MEM (CMD_BUS_MASTER | BIT1)
  19. #define CMD_BM_MEM_IO (CMD_BUS_MASTER | BIT1 | BIT0)
  20. #define DEF_CACHE_LINE_SIZE 0x20
  21. #define DEF_RES_IO_PER_DEV 4
  22. #define DEF_RES_MEM_PER_DEV 32
  23. #define DEF_RES_PMEM_PER_DEV 32
  24. #define DOCK_BUSSES 8
  25. #define DISBL_IO_REG1C 0x01F1
  26. #define DISBL_MEM32_REG20 0x0000FFF0
  27. #define DISBL_PMEM_REG24 0x0001FFF1
  28. #define count(x) (sizeof (x) / sizeof ((x)[0]))
  29. #define PCIE_CAP_ID_SSID_SSVID 0x0D
  30. #define INVALID_PCI_DEVICE 0xFFFFFFFF
  31. #define PCI_TBT_VESC_REG2 0x510
  32. typedef struct _PortInfo {
  33. UINT8 IoBase;
  34. UINT8 IoLimit;
  35. UINT16 MemBase;
  36. UINT16 MemLimit;
  37. UINT64 PMemBase64;
  38. UINT64 PMemLimit64;
  39. UINT8 BusNumLimit;
  40. UINT8 ConfedEP;
  41. } PORT_INFO;
  42. typedef struct _MEM_REGS {
  43. UINT32 Base;
  44. UINT32 Limit;
  45. } MEM_REGS;
  46. typedef struct _PMEM_REGS {
  47. UINT64 Base64;
  48. UINT64 Limit64;
  49. } PMEM_REGS;
  50. typedef struct _IO_REGS {
  51. UINT16 Base;
  52. UINT16 Limit;
  53. } IO_REGS;
  54. typedef struct _BRDG_RES_CONFIG {
  55. UINT8 Cmd;
  56. UINT8 Cls;
  57. UINT8 IoBase;
  58. UINT8 IoLimit;
  59. UINT16 MemBase;
  60. UINT16 MemLimit;
  61. UINT64 PMemBase64;
  62. UINT64 PMemLimit64;
  63. } BRDG_RES_CONFIG;
  64. typedef struct _BRDG_CONFIG {
  65. DEV_ID DevId;
  66. UINT8 PBus;
  67. UINT8 SBus;
  68. UINT8 SubBus;
  69. BOOLEAN IsDSBridge;
  70. BRDG_RES_CONFIG Res;
  71. } BRDG_CONFIG;
  72. enum {
  73. HR_US_PORT,
  74. HR_DS_PORT0,
  75. HR_DS_PORT3,
  76. HR_DS_PORT4,
  77. HR_DS_PORT5,
  78. HR_DS_PORT6,
  79. MAX_CFG_PORTS
  80. };
  81. enum {
  82. HR_DS_PORT1 = HR_DS_PORT3
  83. };
  84. //
  85. // Alpine Ridge
  86. //
  87. enum {
  88. AR_DS_PORT1 = HR_DS_PORT3,
  89. AR_DS_PORT2,
  90. AR_DS_PORT3,
  91. AR_DS_PORT4
  92. };
  93. typedef struct _HR_CONFIG {
  94. UINT16 DeviceId;
  95. UINT8 HRBus;
  96. UINT8 MinDSNumber;
  97. UINT8 MaxDSNumber;
  98. UINT8 BridgeLoops;
  99. } HR_CONFIG;
  100. STATIC const BRDG_RES_CONFIG NOT_IN_USE_BRIDGE = {
  101. CMD_BUS_MASTER,
  102. 0,
  103. DISBL_IO_REG1C & 0xFF,
  104. DISBL_IO_REG1C >> 8,
  105. DISBL_MEM32_REG20 & 0xFFFF,
  106. DISBL_MEM32_REG20 >> 16,
  107. DISBL_PMEM_REG24 & 0xFFFF,
  108. DISBL_PMEM_REG24 >> 16
  109. };
  110. typedef union _BRDG_CIO_MAP_REG {
  111. UINT32 AB_REG;
  112. struct {
  113. UINT32 NumOfDSPorts : 5;
  114. UINT32 CioPortMap : 27;
  115. } Bits;
  116. } BRDG_CIO_MAP_REG;
  117. //
  118. // Functions
  119. //
  120. VOID
  121. ThunderboltCallback (
  122. IN UINT8 Type
  123. );
  124. VOID
  125. TbtDisablePCIDevicesAndBridges (
  126. IN UINT8 Type
  127. );
  128. VOID
  129. EndOfThunderboltCallback(
  130. IN UINTN RpSegment,
  131. IN UINTN RpBus,
  132. IN UINTN RpDevice,
  133. IN UINTN RpFunction
  134. );
  135. VOID
  136. ConfigureTbtAspm(
  137. IN UINT8 Type,
  138. IN UINT16 Aspm
  139. );
  140. UINT8
  141. PcieFindCapId (
  142. IN UINT8 Segment,
  143. IN UINT8 Bus,
  144. IN UINT8 Device,
  145. IN UINT8 Function,
  146. IN UINT8 CapId
  147. );
  148. #endif