Tbt.asl 45 KB

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  1. /** @file
  2. Thunderbolt ACPI methods
  3. Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #define DTBT_CONTROLLER 0x00
  7. #define DTBT_TYPE_PCH 0x01
  8. #define DTBT_TYPE_PEG 0x02
  9. #define DTBT_SMI_HANDLER_NUMBER 0xF7
  10. #define TBT_SMI_ENUMERATION_FUNCTION 21
  11. #define TBT_SMI_RESET_SWITCH_FUNCTION 22
  12. #define TBT_SMI_DISABLE_MSI_FUNCTION 23
  13. #ifndef BIT29
  14. #define BIT29 0x20000000
  15. #endif
  16. Name(LDLY, 300) //300 ms
  17. Name (TNVB, 0xFFFF0000) // TBT NVS Base address
  18. Name (TNVL, 0xAA55) // TBT NVS Length
  19. Include ("Acpi/TbtNvs.asl")
  20. External(\_SB.PCI0.RP02.L23D, MethodObj)
  21. External(\_SB.PCI0.RP03.L23D, MethodObj)
  22. External(\_SB.PCI0.RP04.L23D, MethodObj)
  23. External(\_SB.PCI0.RP05.L23D, MethodObj)
  24. External(\_SB.PCI0.RP06.L23D, MethodObj)
  25. External(\_SB.PCI0.RP07.L23D, MethodObj)
  26. External(\_SB.PCI0.RP08.L23D, MethodObj)
  27. External(\_SB.PCI0.RP09.L23D, MethodObj)
  28. External(\_SB.PCI0.RP10.L23D, MethodObj)
  29. External(\_SB.PCI0.RP11.L23D, MethodObj)
  30. External(\_SB.PCI0.RP12.L23D, MethodObj)
  31. External(\_SB.PCI0.RP13.L23D, MethodObj)
  32. External(\_SB.PCI0.RP14.L23D, MethodObj)
  33. External(\_SB.PCI0.RP15.L23D, MethodObj)
  34. External(\_SB.PCI0.RP16.L23D, MethodObj)
  35. External(\_SB.PCI0.RP17.L23D, MethodObj)
  36. External(\_SB.PCI0.RP18.L23D, MethodObj)
  37. External(\_SB.PCI0.RP19.L23D, MethodObj)
  38. External(\_SB.PCI0.RP20.L23D, MethodObj)
  39. External(\_SB.PCI0.RP21.L23D, MethodObj)
  40. External(\_SB.PCI0.RP22.L23D, MethodObj)
  41. External(\_SB.PCI0.RP23.L23D, MethodObj)
  42. External(\_SB.PCI0.RP24.L23D, MethodObj)
  43. External(\_SB.PCI0.RP01.DL23, MethodObj)
  44. External(\_SB.PCI0.RP02.DL23, MethodObj)
  45. External(\_SB.PCI0.RP03.DL23, MethodObj)
  46. External(\_SB.PCI0.RP04.DL23, MethodObj)
  47. External(\_SB.PCI0.RP05.DL23, MethodObj)
  48. External(\_SB.PCI0.RP06.DL23, MethodObj)
  49. External(\_SB.PCI0.RP07.DL23, MethodObj)
  50. External(\_SB.PCI0.RP08.DL23, MethodObj)
  51. External(\_SB.PCI0.RP09.DL23, MethodObj)
  52. External(\_SB.PCI0.RP10.DL23, MethodObj)
  53. External(\_SB.PCI0.RP11.DL23, MethodObj)
  54. External(\_SB.PCI0.RP12.DL23, MethodObj)
  55. External(\_SB.PCI0.RP13.DL23, MethodObj)
  56. External(\_SB.PCI0.RP14.DL23, MethodObj)
  57. External(\_SB.PCI0.RP15.DL23, MethodObj)
  58. External(\_SB.PCI0.RP16.DL23, MethodObj)
  59. External(\_SB.PCI0.RP17.DL23, MethodObj)
  60. External(\_SB.PCI0.RP18.DL23, MethodObj)
  61. External(\_SB.PCI0.RP19.DL23, MethodObj)
  62. External(\_SB.PCI0.RP20.DL23, MethodObj)
  63. External(\_SB.PCI0.RP21.DL23, MethodObj)
  64. External(\_SB.PCI0.RP22.DL23, MethodObj)
  65. External(\_SB.PCI0.RP23.DL23, MethodObj)
  66. External(\_SB.PCI0.RP24.DL23, MethodObj)
  67. External(\_SB.PCI0.RTEN, MethodObj)
  68. External(\_SB.PCI0.RTDS, MethodObj)
  69. External(\_SB.PCI0.RP01.PON, MethodObj)
  70. External(\_SB.PCI0.RP02.PON, MethodObj)
  71. External(\_SB.PCI0.RP03.PON, MethodObj)
  72. External(\_SB.PCI0.RP04.PON, MethodObj)
  73. External(\_SB.PCI0.RP05.PON, MethodObj)
  74. External(\_SB.PCI0.RP06.PON, MethodObj)
  75. External(\_SB.PCI0.RP07.PON, MethodObj)
  76. External(\_SB.PCI0.RP08.PON, MethodObj)
  77. External(\_SB.PCI0.RP09.PON, MethodObj)
  78. External(\_SB.PCI0.RP10.PON, MethodObj)
  79. External(\_SB.PCI0.RP11.PON, MethodObj)
  80. External(\_SB.PCI0.RP12.PON, MethodObj)
  81. External(\_SB.PCI0.RP13.PON, MethodObj)
  82. External(\_SB.PCI0.RP14.PON, MethodObj)
  83. External(\_SB.PCI0.RP15.PON, MethodObj)
  84. External(\_SB.PCI0.RP16.PON, MethodObj)
  85. External(\_SB.PCI0.RP17.PON, MethodObj)
  86. External(\_SB.PCI0.RP18.PON, MethodObj)
  87. External(\_SB.PCI0.RP19.PON, MethodObj)
  88. External(\_SB.PCI0.RP20.PON, MethodObj)
  89. External(\_SB.PCI0.RP21.PON, MethodObj)
  90. External(\_SB.PCI0.RP22.PON, MethodObj)
  91. External(\_SB.PCI0.RP23.PON, MethodObj)
  92. External(\_SB.PCI0.RP24.PON, MethodObj)
  93. External(\_SB.PCI0.PEG0.PG00._ON, MethodObj)
  94. External(\_SB.PCI0.PEG1.PG01._ON, MethodObj)
  95. External(\_SB.PCI0.PEG2.PG02._ON, MethodObj)
  96. Name(TRDO, 0) // 1 during TBT RTD3 _ON
  97. Name(TRD3, 0) // 1 during TBT RTD3 _OFF
  98. Name(TBPE, 0) // Reflects RTD3_PWR_EN value
  99. Name(TOFF, 0) // param to TBT _OFF method
  100. Method (TBON, 0, Serialized) {
  101. // TBT On process before entering Sx state.
  102. Store(1, TRDO)
  103. Switch (ToInteger(\RPS0)) { // TBT Root port Selector
  104. Case (1) {
  105. If (CondRefOf(\_SB.PCI0.RP01.PON)) {
  106. \_SB.PCI0.RP01.PON()
  107. }
  108. }
  109. Case (2) {
  110. If (CondRefOf(\_SB.PCI0.RP02.PON)) {
  111. \_SB.PCI0.RP02.PON()
  112. }
  113. }
  114. Case (3) {
  115. If (CondRefOf(\_SB.PCI0.RP03.PON)) {
  116. \_SB.PCI0.RP03.PON()
  117. }
  118. }
  119. Case (4) {
  120. If (CondRefOf(\_SB.PCI0.RP04.PON)) {
  121. \_SB.PCI0.RP04.PON()
  122. }
  123. }
  124. Case (5) {
  125. If (CondRefOf(\_SB.PCI0.RP05.PON)) {
  126. \_SB.PCI0.RP05.PON()
  127. }
  128. }
  129. Case (6) {
  130. If (CondRefOf(\_SB.PCI0.RP06.PON)) {
  131. \_SB.PCI0.RP06.PON()
  132. }
  133. }
  134. Case (7) {
  135. If (CondRefOf(\_SB.PCI0.RP07.PON)) {
  136. \_SB.PCI0.RP07.PON()
  137. }
  138. }
  139. Case (8) {
  140. If (CondRefOf(\_SB.PCI0.RP08.PON)) {
  141. \_SB.PCI0.RP08.PON()
  142. }
  143. }
  144. Case (9) {
  145. If (CondRefOf(\_SB.PCI0.RP09.PON)) {
  146. \_SB.PCI0.RP09.PON()
  147. }
  148. }
  149. Case (10) {
  150. If (CondRefOf(\_SB.PCI0.RP10.PON)) {
  151. \_SB.PCI0.RP10.PON()
  152. }
  153. }
  154. Case (11) {
  155. If (CondRefOf(\_SB.PCI0.RP11.PON)) {
  156. \_SB.PCI0.RP11.PON()
  157. }
  158. }
  159. Case (12) {
  160. If (CondRefOf(\_SB.PCI0.RP12.PON)) {
  161. \_SB.PCI0.RP12.PON()
  162. }
  163. }
  164. Case (13) {
  165. If (CondRefOf(\_SB.PCI0.RP13.PON)) {
  166. \_SB.PCI0.RP13.PON()
  167. }
  168. }
  169. Case (14) {
  170. If (CondRefOf(\_SB.PCI0.RP14.PON)) {
  171. \_SB.PCI0.RP14.PON()
  172. }
  173. }
  174. Case (15) {
  175. If (CondRefOf(\_SB.PCI0.RP15.PON)) {
  176. \_SB.PCI0.RP15.PON()
  177. }
  178. }
  179. Case (16) {
  180. If (CondRefOf(\_SB.PCI0.RP16.PON)) {
  181. \_SB.PCI0.RP16.PON()
  182. }
  183. }
  184. Case (17) {
  185. If (CondRefOf(\_SB.PCI0.RP17.PON)) {
  186. \_SB.PCI0.RP17.PON()
  187. }
  188. }
  189. Case (18) {
  190. If (CondRefOf(\_SB.PCI0.RP18.PON)) {
  191. \_SB.PCI0.RP18.PON()
  192. }
  193. }
  194. Case (19) {
  195. If (CondRefOf(\_SB.PCI0.RP19.PON)) {
  196. \_SB.PCI0.RP19.PON()
  197. }
  198. }
  199. Case (20) {
  200. If (CondRefOf(\_SB.PCI0.RP20.PON)) {
  201. \_SB.PCI0.RP20.PON()
  202. }
  203. }
  204. Case (21) {
  205. If (CondRefOf(\_SB.PCI0.RP21.PON)) {
  206. \_SB.PCI0.RP21.PON()
  207. }
  208. }
  209. Case (22) {
  210. If (CondRefOf(\_SB.PCI0.RP22.PON)) {
  211. \_SB.PCI0.RP22.PON()
  212. }
  213. }
  214. Case (23) {
  215. If (CondRefOf(\_SB.PCI0.RP23.PON)) {
  216. \_SB.PCI0.RP23.PON()
  217. }
  218. }
  219. Case (24) {
  220. If (CondRefOf(\_SB.PCI0.RP24.PON)) {
  221. \_SB.PCI0.RP24.PON()
  222. }
  223. }
  224. }//Switch(ToInteger(RPS0)) // TBT Selector
  225. Store(0, TRDO)
  226. } // End of TBON
  227. //
  228. // Name: TBTD
  229. // Description: Function to return the TBT RP# device no
  230. // Input: Arg0 -> Tbt Root Port value from Tbt NVS
  231. // Input: Arg1 -> Tbt port type value from Tbt NVS
  232. // Return: TBT RP# device no
  233. //
  234. Method(TBTD,2)
  235. {
  236. ADBG("TBTD")
  237. If (LEqual(Arg1, DTBT_TYPE_PCH)) {
  238. Switch(ToInteger(Arg0))
  239. {
  240. Case (Package () {1, 2, 3, 4, 5, 6, 7, 8})
  241. {
  242. Store(0x1C, Local0) //Device28-Function0...Function7 = 11100.000...111
  243. }
  244. Case (Package () {9, 10, 11, 12, 13, 14, 15, 16})
  245. {
  246. Store(0x1D, Local0) //Device29-Function0...Function7 = 11101.000...111
  247. }
  248. Case (Package () {17, 18, 19, 20, 21, 22, 23, 24})
  249. {
  250. Store(0x1B, Local0) //Device27-Function0...Function3 = 11011.000...011
  251. }
  252. }
  253. } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) {
  254. Switch(ToInteger(Arg0))
  255. {
  256. Case (Package () {1, 2, 3})
  257. {
  258. Store(0x1, Local0) //Device1-Function0...Function2 = 00001.000...010
  259. }
  260. }
  261. } Else {
  262. Store(0xFF, Local0)
  263. }
  264. ADBG("Device no")
  265. ADBG(Local0)
  266. Return(Local0)
  267. } // End of Method(TBTD,1)
  268. //
  269. // Name: TBTF
  270. // Description: Function to return the TBT RP# function no
  271. // Input: Arg0 -> Tbt Root Port value from Tbt NVS
  272. // Input: Arg1 -> Tbt port type value from Tbt NVS
  273. // Return: TBT RP# function no
  274. //
  275. Method(TBTF,2)
  276. {
  277. ADBG("TBTF")
  278. If (LEqual(Arg1, DTBT_TYPE_PCH)) {
  279. Switch(ToInteger(Arg0))
  280. {
  281. Case (1)
  282. {
  283. Store(And(\RPA1,0xF), Local0) //Device28-Function0 = 11100.000
  284. }
  285. Case (2)
  286. {
  287. Store(And(\RPA2,0xF), Local0) //Device28-Function1 = 11100.001
  288. }
  289. Case (3)
  290. {
  291. Store(And(\RPA3,0xF), Local0) //Device28-Function2 = 11100.010
  292. }
  293. Case (4)
  294. {
  295. Store(And(\RPA4,0xF), Local0) //Device28-Function3 = 11100.011
  296. }
  297. Case (5)
  298. {
  299. Store(And(\RPA5,0xF), Local0) //Device28-Function4 = 11100.100
  300. }
  301. Case (6)
  302. {
  303. Store(And(\RPA6,0xF), Local0) //Device28-Function5 = 11100.101
  304. }
  305. Case (7)
  306. {
  307. Store(And(\RPA7,0xF), Local0) //Device28-Function6 = 11100.110
  308. }
  309. Case (8)
  310. {
  311. Store(And(\RPA8,0xF), Local0) //Device28-Function7 = 11100.111
  312. }
  313. Case (9)
  314. {
  315. Store(And(\RPA9,0xF), Local0) //Device29-Function0 = 11101.000
  316. }
  317. Case (10)
  318. {
  319. Store(And(\RPAA,0xF), Local0) //Device29-Function1 = 11101.001
  320. }
  321. Case (11)
  322. {
  323. Store(And(\RPAB,0xF), Local0) //Device29-Function2 = 11101.010
  324. }
  325. Case (12)
  326. {
  327. Store(And(\RPAC,0xF), Local0) //Device29-Function3 = 11101.011
  328. }
  329. Case (13)
  330. {
  331. Store(And(\RPAD,0xF), Local0) //Device29-Function4 = 11101.100
  332. }
  333. Case (14)
  334. {
  335. Store(And(\RPAE,0xF), Local0) //Device29-Function5 = 11101.101
  336. }
  337. Case (15)
  338. {
  339. Store(And(\RPAF,0xF), Local0) //Device29-Function6 = 11101.110
  340. }
  341. Case (16)
  342. {
  343. Store(And(\RPAG,0xF), Local0) //Device29-Function7 = 11101.111
  344. }
  345. Case (17)
  346. {
  347. Store(And(\RPAH,0xF), Local0) //Device27-Function0 = 11011.000
  348. }
  349. Case (18)
  350. {
  351. Store(And(\RPAI,0xF), Local0) //Device27-Function1 = 11011.001
  352. }
  353. Case (19)
  354. {
  355. Store(And(\RPAJ,0xF), Local0) //Device27-Function2 = 11011.010
  356. }
  357. Case (20)
  358. {
  359. Store(And(\RPAK,0xF), Local0) //Device27-Function3 = 11011.011
  360. }
  361. Case (21)
  362. {
  363. Store(And(\RPAL,0xF), Local0) //Device27-Function4 = 11011.100
  364. }
  365. Case (22)
  366. {
  367. Store(And(\RPAM,0xF), Local0) //Device27-Function5 = 11011.101
  368. }
  369. Case (23)
  370. {
  371. Store(And(\RPAN,0xF), Local0) //Device27-Function6 = 11011.110
  372. }
  373. Case (24)
  374. {
  375. Store(And(\RPAO,0xF), Local0) //Device27-Function7 = 11011.111
  376. }
  377. }
  378. } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) {
  379. Switch(ToInteger(Arg0))
  380. {
  381. Case (1)
  382. {
  383. Store(0x0, Local0) //Device1-Function0 = 00001.000
  384. }
  385. Case (2)
  386. {
  387. Store(0x1, Local0) //Device1-Function1 = 00001.001
  388. }
  389. Case (3)
  390. {
  391. Store(0x2, Local0) //Device1-Function2 = 00001.010
  392. }
  393. }
  394. } Else {
  395. Store(0xFF, Local0)
  396. }
  397. ADBG("Function no")
  398. ADBG(Local0)
  399. Return(Local0)
  400. } // End of Method(TBTF,1)
  401. //
  402. // Name: MMRP
  403. // Description: Function to return the Pci base address of TBT rootport
  404. // Input: Arg0 -> Tbt Root Port value from Tbt NVS
  405. // Input: Arg1 -> Tbt port type value from Tbt NVS
  406. //
  407. Method(MMRP, 2, Serialized)
  408. {
  409. Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address
  410. Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no
  411. Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no
  412. Return(Local0)
  413. } // End of Method(MMRP)
  414. //
  415. // Name: MMRP
  416. // Description: Function to return the Pci base address of TBT Up stream port
  417. // Input: Arg0 -> Tbt Root Port value from Tbt NVS
  418. // Input: Arg1 -> Tbt port type value from Tbt NVS
  419. //
  420. Method(MMTB, 2, Serialized)
  421. {
  422. ADBG("MMTB")
  423. Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address
  424. Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no
  425. Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no
  426. OperationRegion (MMMM, SystemMemory, Local0, 0x1A)
  427. Field (MMMM, AnyAcc, NoLock, Preserve)
  428. {
  429. Offset(0x19),
  430. SBUS, 8
  431. }
  432. Store(SBUS, Local2)
  433. Store(\_SB.PCI0.GPCB(), Local0)
  434. Multiply(Local2, 0x100000, Local2)
  435. Add(Local2, Local0, Local0) // TBT HR US port
  436. ADBG("TBT-US-ADR")
  437. ADBG(Local0)
  438. Return(Local0)
  439. } // End of Method(MMTB, 1, Serialized)
  440. //
  441. // Name: FFTB
  442. // Description: Function to Check for FFFF in TBT PCIe
  443. // Input: Arg0 -> Tbt Root Port value from Tbt NVS
  444. // Input: Arg1 -> Tbt port type value from Tbt NVS
  445. // Return: 1 if TBT PCIe space has value FFFF, 0 if not
  446. //
  447. Method(FFTB, 2, Serialized)
  448. {
  449. ADBG("FFTB")
  450. Add(MMTB(Arg0, Arg1), 0x548, Local0)
  451. OperationRegion(PXVD,SystemMemory,Local0,0x08)
  452. Field(PXVD,DWordAcc, NoLock, Preserve)
  453. {
  454. TB2P, 32,
  455. P2TB, 32
  456. }
  457. Store(TB2P, Local1)
  458. If(LEqual(Local1, 0xFFFFFFFF))
  459. {
  460. ADBG("FFTb 1")
  461. Return (1)
  462. }
  463. Else
  464. {
  465. ADBG("FFTb 0")
  466. Return (0)
  467. }
  468. } // End of Method(FFTB)
  469. Name(TDMA, 0x80000000) // Address of Thunderbolt(TM) debug memory buffer, fixed up during POST
  470. Scope(\_GPE)
  471. {
  472. //
  473. //
  474. //OS up Mail Box command execution to host router upstream port each time
  475. //exiting from Sx State .Avoids intermediate
  476. //PCIe Scan by OS during resorce allocation
  477. // Arg0 : PCIe Base address
  478. // Arg1 : Controller Type 0x00 : DTBT
  479. //Developer notes: Called twice
  480. // 1. During OS INIT (booting to OS from S3-S5/Reboot)
  481. // 2. Up on Hot plug
  482. //
  483. Method(OSUP, 2, Serialized)
  484. {
  485. ADBG("OSUP")
  486. Add(Arg0, 0x540, Local0)
  487. OperationRegion(PXVD,SystemMemory,Local0,0x10)
  488. Field(PXVD,DWordAcc, NoLock, Preserve)
  489. {
  490. IT2P, 32,
  491. IP2T, 32,
  492. DT2P, 32,
  493. DP2T, 32
  494. }
  495. Store(100, Local1)
  496. Store(0x0D, DP2T) // Write OS_Up to PCIe2TBT
  497. While(LGreater(Local1, 0))
  498. {
  499. Store(Subtract(Local1, 1), Local1)
  500. Store(DT2P, Local2)
  501. If(LAnd(LEqual(Local2, 0xFFFFFFFF),LEqual(Arg1, DTBT_CONTROLLER)))// Device gone
  502. {
  503. ADBG("Dev gone")
  504. Return(2)
  505. }
  506. If(And(Local2, 1)) // Done
  507. {
  508. ADBG("Cmd acknowledged")
  509. break
  510. }
  511. Sleep(50)
  512. }
  513. If(LEqual(TRWA,1))
  514. {
  515. Store(0xC, DP2T) // Write OSUP to PCIe2TBT
  516. }
  517. Else
  518. {
  519. Store(0x0, DP2T) // Write 0 to PCIe2TBT
  520. }
  521. //Store(0x00, P2TB) // Write 0 to PCIe2TBT
  522. ADBG("End-of-OSUP")
  523. Return(1)
  524. } // End of Method(OSUP, 1, Serialized)
  525. //
  526. // Check for FFFF in TBT
  527. // Input: Arg0 -> Tbt Root Port value from Tbt NVS
  528. // Input: Arg1 -> Tbt port type value from Tbt NVS
  529. //
  530. Method(TBFF, 2, Serialized)
  531. {
  532. ADBG("TBFF")
  533. Store(MMTB(Arg0, Arg1), Local0)
  534. OperationRegion (PXVD, SystemMemory, Local0, 0x8)
  535. Field (PXVD, DWordAcc, NoLock, Preserve) {
  536. VEDI, 32, // Vendor/Device ID
  537. CMDR, 32 // CMD register
  538. }
  539. Store(VEDI, Local1)
  540. If (LEqual(Local1, 0xFFFFFFFF)) {
  541. If (LNotEqual(\TWIN, 0)) { // TBT Enumeration is Native mode?
  542. If (LEqual(CMDR, 0xFFFFFFFF)) { // Device Gone
  543. Return (2)// Notify only
  544. }
  545. Return (1)// Exit w/o notify
  546. } Else {
  547. Return (OSUP(Local0, DTBT_CONTROLLER))
  548. }
  549. } Else
  550. {
  551. ADBG("Dev Present")
  552. Return (0)
  553. }
  554. } // End of Method(TBFF, 1, Serialized)
  555. //
  556. // Secondary bus of TBT RP
  557. // Input: Arg0 -> Tbt Root Port value from Tbt NVS
  558. // Input: Arg1 -> Tbt port type value from Tbt NVS
  559. //
  560. Method(TSUB, 2, Serialized)
  561. {
  562. ADBG("TSUB")
  563. Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address
  564. Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no
  565. Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no
  566. ADBG("ADR")
  567. ADBG(Local0)
  568. OperationRegion (MMMM, SystemMemory, Local0, 0x1A)
  569. Field (MMMM, AnyAcc, NoLock, Preserve)
  570. {
  571. Offset(0x19),
  572. SBUS, 8
  573. }
  574. ADBG("Sec Bus")
  575. ADBG(SBUS)
  576. Return(SBUS)
  577. } // End of Method(TSUB, 0, Serialized)
  578. //
  579. // Pmem of TBT RP
  580. // Input: Arg0 -> Tbt Root Port value from Tbt NVS
  581. // Input: Arg1 -> Tbt port type value from Tbt NVS
  582. //
  583. Method(TSUP, 2, Serialized)
  584. {
  585. ADBG("TSUB")
  586. Store(\_SB.PCI0.GPCB(), Local0) // MMIO Base address
  587. Add(Local0, ShiftLeft(TBTD(Arg0, Arg1), 15), Local0) // Device no
  588. Add(Local0, ShiftLeft(TBTF(Arg0, Arg1), 12), Local0) // Function no
  589. ADBG("ADR:")
  590. ADBG(Local0)
  591. OperationRegion (MMMM, SystemMemory, Local0, 0x30)
  592. Field (MMMM, AnyAcc, NoLock, Preserve)
  593. {
  594. CMDS, 32,
  595. Offset(0x19),
  596. SBUS, 8,
  597. SBU5, 8,
  598. Offset(0x1C),
  599. SEIO, 32,
  600. MMBL, 32,
  601. PMBL, 32,
  602. }
  603. ADBG("Pmem of TBT RP:")
  604. ADBG(PMBL)
  605. Return(PMBL)
  606. } // End of Method(TSUP, 0, Serialized)
  607. //
  608. // Wait for secondary bus in TBT RP
  609. // Input: Arg0 -> Tbt Root Port value from Tbt NVS
  610. // Input: Arg1 -> Tbt port type value from Tbt NVS
  611. //
  612. Method(WSUB, 2, Serialized)
  613. {
  614. ADBG(Concatenate("WSUB=", ToHexString(Arg0)))
  615. ADBG(ToHexString(Timer))
  616. Store(0, Local0)
  617. Store(0, Local1)
  618. While(1)
  619. {
  620. Store(TSUP(Arg0, Arg1), Local1)
  621. If(LGreater(Local1, 0x1FFF1))
  622. {
  623. ADBG("WSUB-Finished")
  624. Break
  625. }
  626. Else
  627. {
  628. Add(Local0, 1, Local0)
  629. If(LGreater(Local0, 1000))
  630. {
  631. Sleep(1000)
  632. ADBG("WSUB-Deadlock")
  633. }
  634. Else
  635. {
  636. Sleep(16)
  637. }
  638. }
  639. }
  640. ADBG(Concatenate("WSUb=", ToHexString(Local1)))
  641. } // End of Method(WSUB)
  642. // Wait for _WAK finished
  643. Method(WWAK)
  644. {
  645. ADBG("WWAK")
  646. Wait(WFEV, 0xFFFF)
  647. Signal(WFEV) // Set it, to enter on next HP
  648. } // End of Method(WWAK)
  649. Method(NTFY, 2, Serialized)
  650. {
  651. ADBG("NTFY")
  652. If(LEqual(NOHP,1))
  653. {
  654. If (LEqual(Arg1, DTBT_TYPE_PCH)) {
  655. Switch(ToInteger(Arg0)) // TBT Selector
  656. {
  657. Case (1)
  658. {
  659. ADBG("Notify RP01")
  660. Notify(\_SB.PCI0.RP01,0)
  661. }
  662. Case (2)
  663. {
  664. ADBG("Notify RP02")
  665. Notify(\_SB.PCI0.RP02,0)
  666. }
  667. Case (3)
  668. {
  669. ADBG("Notify RP03")
  670. Notify(\_SB.PCI0.RP03,0)
  671. }
  672. Case (4)
  673. {
  674. ADBG("Notify RP04")
  675. Notify(\_SB.PCI0.RP04,0)
  676. }
  677. Case (5)
  678. {
  679. ADBG("Notify RP05")
  680. Notify(\_SB.PCI0.RP05,0)
  681. }
  682. Case (6)
  683. {
  684. ADBG("Notify RP06")
  685. Notify(\_SB.PCI0.RP06,0)
  686. }
  687. Case (7)
  688. {
  689. ADBG("Notify RP07")
  690. Notify(\_SB.PCI0.RP07,0)
  691. }
  692. Case (8)
  693. {
  694. ADBG("Notify RP08")
  695. Notify(\_SB.PCI0.RP08,0)
  696. }
  697. Case (9)
  698. {
  699. ADBG("Notify RP09")
  700. Notify(\_SB.PCI0.RP09,0)
  701. }
  702. Case (10)
  703. {
  704. ADBG("Notify RP10")
  705. Notify(\_SB.PCI0.RP10,0)
  706. }
  707. Case (11)
  708. {
  709. ADBG("Notify RP11")
  710. Notify(\_SB.PCI0.RP11,0)
  711. }
  712. Case (12)
  713. {
  714. ADBG("Notify RP12")
  715. Notify(\_SB.PCI0.RP12,0)
  716. }
  717. Case (13)
  718. {
  719. ADBG("Notify RP13")
  720. Notify(\_SB.PCI0.RP13,0)
  721. }
  722. Case (14)
  723. {
  724. ADBG("Notify RP14")
  725. Notify(\_SB.PCI0.RP14,0)
  726. }
  727. Case (15)
  728. {
  729. ADBG("Notify RP15")
  730. Notify(\_SB.PCI0.RP15,0)
  731. }
  732. Case (16)
  733. {
  734. ADBG("Notify RP16")
  735. Notify(\_SB.PCI0.RP16,0)
  736. }
  737. Case (17)
  738. {
  739. ADBG("Notify RP17")
  740. Notify(\_SB.PCI0.RP17,0)
  741. }
  742. Case (18)
  743. {
  744. ADBG("Notify RP18")
  745. Notify(\_SB.PCI0.RP18,0)
  746. }
  747. Case (19)
  748. {
  749. ADBG("Notify RP19")
  750. Notify(\_SB.PCI0.RP19,0)
  751. }
  752. Case (20)
  753. {
  754. ADBG("Notify RP20")
  755. Notify(\_SB.PCI0.RP20,0)
  756. }
  757. Case (21)
  758. {
  759. ADBG("Notify RP21")
  760. Notify(\_SB.PCI0.RP21,0)
  761. }
  762. Case (22)
  763. {
  764. ADBG("Notify RP22")
  765. Notify(\_SB.PCI0.RP22,0)
  766. }
  767. Case (23)
  768. {
  769. ADBG("Notify RP23")
  770. Notify(\_SB.PCI0.RP23,0)
  771. }
  772. Case (24)
  773. {
  774. ADBG("Notify RP24")
  775. Notify(\_SB.PCI0.RP24,0)
  776. }
  777. }//Switch(ToInteger(TBSS)) // TBT Selector
  778. } ElseIf (LEqual(Arg1, DTBT_TYPE_PEG)) {
  779. Switch(ToInteger(Arg0))
  780. {
  781. Case (1)
  782. {
  783. ADBG("Notify PEG0")
  784. Notify(\_SB.PCI0.PEG0,0)
  785. }
  786. Case (2)
  787. {
  788. ADBG("Notify PEG1")
  789. Notify(\_SB.PCI0.PEG1,0)
  790. }
  791. Case (3)
  792. {
  793. ADBG("Notify PEG2")
  794. Notify(\_SB.PCI0.PEG2,0)
  795. }
  796. }
  797. }//Switch(ToInteger(TBSS)) // TBT Selector
  798. }//If(NOHP())
  799. P8XH(0,0xC2)
  800. P8XH(1,0xC2)
  801. }// End of Method(NTFY)
  802. //
  803. // TBT BIOS, GPIO 5 filtering,
  804. // Hot plug of 12V USB devices, into TBT host router, cause electrical noise on PCH GPIOs,
  805. // This noise cause false hot-plug events, and negatively influence BIOS assisted hot-plug.
  806. // WHL-PCH GPIO does not implement Glitch Filter logic (refer to GPIO HAS) on any GPIO pad. Native functions have to implement their own digital glitch-filter logic
  807. // if needed. As HW filter was not implemented on WHL PCH, because of that SW workaround should be implemented in BIOS.
  808. // Register 0x544(Bios mailbox) bit 0 definition:
  809. // if BIOS reads bit as 1, BIOS will clear the bit and continue normal flow, if bit is 0 BIOS will exit from method
  810. //
  811. Method(GNIS,2, Serialized)
  812. {
  813. ADBG("GNIS")
  814. If(LEqual(GP5F, 0))
  815. {
  816. ADBG("GNIS_Dis=0")
  817. Return(0)
  818. }
  819. //
  820. // BIOS mailbox command for GPIO filter
  821. //
  822. Add(MMTB(Arg0, Arg1), 0x544, Local0)
  823. OperationRegion(PXVD,SystemMemory,Local0,0x08)
  824. Field(PXVD,DWordAcc, NoLock, Preserve)
  825. {
  826. HPFI, 1,
  827. Offset(0x4),
  828. TB2P, 32
  829. }
  830. Store(TB2P, Local1)
  831. ADBG(Concatenate("TB2P=", ToHexString(Local1)))
  832. If(LEqual(Local1, 0xFFFFFFFF)) // Disconnect?
  833. {
  834. ADBG("GNIS=0")
  835. Return(0)
  836. }
  837. Store(HPFI, Local2)
  838. ADBG(Concatenate("HPFI=", ToHexString(Local2)))
  839. If(LEqual(Local2, 0x01))
  840. {
  841. Store(0x00, HPFI)
  842. ADBG("GNIS=0")
  843. Return(0)
  844. }
  845. // Any other values treated as a GPIO noise
  846. ADBG("GNIS=1")
  847. Return(1)
  848. }
  849. Method(CHKP,2, Serialized)
  850. {
  851. Add(MMTB(Arg0, Arg1), 0x544, Local0)
  852. OperationRegion(PXVE,SystemMemory,Local0,0x08)
  853. Field(PXVE,DWordAcc, NoLock, Preserve)
  854. {
  855. HPFI, 1,
  856. Offset(0x4),
  857. TB2P, 32
  858. }
  859. Store(TB2P, Local1)
  860. And(Local1,BIT29,Local1)
  861. ADBG(Concatenate("Local1=", ToHexString(Local1)))
  862. //ADBG(Concatenate("BIT29=", ToHexString(LAnd(Local1,BIT29))))
  863. If(LEqual(Local1, BIT29))
  864. {
  865. Return(1)
  866. }
  867. Else
  868. {
  869. Return(0)
  870. }
  871. }
  872. //
  873. // Method to Handle enumerate PCIe structure through
  874. // SMI for Thunderbolt(TM) devices
  875. //
  876. Method(XTBT,2, Serialized)
  877. {
  878. ADBG("XTBT")
  879. ADBG("RP :")
  880. ADBG(Arg0)
  881. Store(Arg0, DTCP) // Root port to enumerate
  882. Store(Arg1, DTPT) // Root port Type
  883. If(LEqual(Arg0, RPS0)) {
  884. Store (1, Local0)
  885. } ElseIf (LEqual(Arg0, RPS1)) {
  886. Store (2, Local0)
  887. } Else {
  888. Store (0, Local0)
  889. Return ()
  890. }
  891. If (TRDO) {
  892. ADBG("Durng TBT_ON")
  893. Return ()
  894. }
  895. If (TRD3) {
  896. ADBG("During TBT_OFF")
  897. Return ()
  898. }
  899. WWAK()
  900. WSUB(Arg0, Arg1)
  901. If(GNIS(Arg0, Arg1))
  902. {
  903. Return()
  904. }
  905. OperationRegion(SPRT,SystemIO, 0xB2,2)
  906. Field (SPRT, ByteAcc, Lock, Preserve)
  907. {
  908. SSMP, 8
  909. }
  910. ADBG("TBT-HP-Handler")
  911. Acquire(OSUM, 0xFFFF)
  912. Store(TBFF(Arg0, Arg1), Local1)
  913. If(LEqual(Local1, 1))// Only HR
  914. {
  915. Sleep(16)
  916. Release(OSUM)
  917. ADBG("OS_Up_Received")
  918. Return ()
  919. }
  920. If(LEqual(Local1, 2)) // Disconnect
  921. {
  922. NTFY(Arg0, Arg1)
  923. Sleep(16)
  924. Release(OSUM)
  925. ADBG("Disconnect")
  926. Return ()
  927. }
  928. // HR and EP
  929. If(LEqual(SOHP, 1))
  930. {
  931. // Trigger SMI to enumerate PCIe Structure
  932. ADBG("TBT SW SMI")
  933. Store(21, TBSF)
  934. Store(0xF7, SSMP)
  935. }
  936. NTFY(Arg0, Arg1)
  937. Sleep(16)
  938. Release(OSUM)
  939. ADBG("End-of-XTBT")
  940. } // End of Method(XTBT)
  941. //
  942. // Calling Method to Handle enumerate PCIe structure through
  943. // SMI for Thunderbolt(TM) devices for Tier 1 GPIOs
  944. // Used in Two ways ,
  945. // If CIO GPIO(1 Tier) is Different for the Controllers, this will be used as 1 Tier GPIO Handler for 1st controller
  946. // If CIO GPIO(1 Tier) is Same for all the controllers, this will be used as 1 Tier GPIO Handler for All the controllers
  947. //
  948. Method(ATBT)
  949. {
  950. ADBG("ATBT")
  951. //
  952. // Calling Method to Handle enumerate PCIe structure through
  953. //
  954. If(LEqual(CGST,0)) { // If GPIO is Different for each controller
  955. If(LEqual(RPN0,1))
  956. {
  957. XTBT(RPS0, RPT0)
  958. }
  959. } Else {
  960. If(LEqual(RPN0,1))
  961. {
  962. XTBT(RPS0, RPT0)
  963. }
  964. ElseIf(LEqual(RPN1,1))
  965. {
  966. XTBT(RPS1, RPT1)
  967. }
  968. }
  969. ADBG("End-of-ATBT")
  970. } // End of Method(ATBT)
  971. Method(BTBT)
  972. {
  973. ADBG("BTBT")
  974. //
  975. // Calling Method to Handle enumerate PCIe structure through
  976. //
  977. If(LEqual(CGST,0)) { // If GPIO is Different for each controller
  978. If(LEqual(RPN1,1))
  979. {
  980. XTBT(RPS1, RPT1)
  981. }
  982. }
  983. ADBG("End-of-BTBT")
  984. } // End of Method(BTBT)
  985. //
  986. // Method to call OSPU Mail box command
  987. // Arg0 : Controller type 0x00 : Discrete 0x80 : Integrated TBT
  988. // Arg1 : TBT RP Selector / DMA
  989. // Arg2 : TBT Type (PCH or PEG)
  990. //
  991. Method(TINI, 3, Serialized)
  992. {
  993. ADBG("TINI")
  994. If(Lequal (Arg0, DTBT_CONTROLLER))
  995. {
  996. //ADBG("DTBT")
  997. Store(MMRP(Arg1, Arg2), Local0)
  998. OperationRegion(RP_X,SystemMemory,Local0,0x20)
  999. Field(RP_X,DWordAcc, NoLock, Preserve)
  1000. {
  1001. REG0, 32,
  1002. REG1, 32,
  1003. REG2, 32,
  1004. REG3, 32,
  1005. REG4, 32,
  1006. REG5, 32,
  1007. REG6, 32,
  1008. REG7, 32
  1009. }
  1010. Store(REG6, Local1)
  1011. Store(0x00F0F000, REG6)
  1012. Store(MMTB(Arg1, Arg2), Local2)
  1013. OSUP(Local2, DTBT_CONTROLLER)
  1014. Store(Local1, REG6)
  1015. }
  1016. ADBG("End-of-TINI")
  1017. }
  1018. } // End of Scope (\_GPE)
  1019. Scope (\_SB)
  1020. {
  1021. //
  1022. // The code needs to be executed for TBT Hotplug Handler event (2-tier GPI GPE event architecture) is presented here
  1023. //
  1024. Method(THDR, 3, Serialized)
  1025. {
  1026. ADBG("THDR")
  1027. \_SB.CAGS(Arg0)
  1028. \_GPE.XTBT(Arg1, Arg2)
  1029. } // End of Method(THDR, 3, Serialized)
  1030. } // End of Scope(\_SB)
  1031. Scope (\_SB)
  1032. {
  1033. //
  1034. // Name: CGWR [Combined GPIO Write]
  1035. // Description: Function to write into GPIO
  1036. // Input: Arg0 -> GpioPad / Expander pin
  1037. // Arg1 -> Value
  1038. // Return: Nothing
  1039. //
  1040. Method(CGWR, 2, Serialized)
  1041. {
  1042. // PCH
  1043. If (CondRefOf(\_SB.SGOV))
  1044. {
  1045. \_SB.SGOV(Arg0, Arg1)
  1046. }
  1047. } // End of Method(CGWR, 4, Serialized)
  1048. //
  1049. // Name: CGRD [Combined GPIO Read]
  1050. // Description: Function to read from GPIO
  1051. // Input: Arg0 -> GpioPad / Expander pin
  1052. // Arg1 -> 0: GPO [GPIO TX State]
  1053. // 1: GPI [GPIO RX State]
  1054. // Return: Value
  1055. //
  1056. Method(CGRD, 2, Serialized)
  1057. {
  1058. Store(1, Local0)
  1059. // PCH
  1060. If (LEqual(Arg1, 0))
  1061. {
  1062. // GPIO TX State
  1063. If (CondRefOf(\_SB.GGOV))
  1064. {
  1065. Store(\_SB.GGOV(Arg0), Local0)
  1066. }
  1067. }
  1068. ElseIf (LEqual(Arg1, 1))
  1069. {
  1070. // GPIO RX State
  1071. If (CondRefOf(\_SB.GGIV))
  1072. {
  1073. Store(\_SB.GGIV(Arg0), Local0)
  1074. }
  1075. }
  1076. Return(Local0)
  1077. } // End of Method(CGRD, 4, Serialized)
  1078. //
  1079. // Name: WRGP [GPIO Write]
  1080. // Description: Function to write into GPIO
  1081. // Input: Arg0 -> COMMON_GPIO_CONFIG GpioInfo
  1082. // Arg1 -> Value
  1083. // Return: Nothing
  1084. //
  1085. Method(WRGP, 2, Serialized)
  1086. {
  1087. Store(Arg0, Local0)
  1088. Store(Arg0, Local1)
  1089. And(Local0, 0xFFFFFFFF, Local0) // Low 32 bits (31:00)
  1090. ShiftRight(Local1, 32, Local1) // High 32 bits (63:32)
  1091. If (LEqual(And(Local0, 0xFF), 1))
  1092. {
  1093. // PCH
  1094. \_SB.CGWR(Local1, Arg1)
  1095. }
  1096. } // End of Method(WRGP, 2, Serialized)
  1097. //
  1098. // Name: RDGP [GPIO Read]
  1099. // Description: Function to write into GPIO
  1100. // Input: Arg0 -> COMMON_GPIO_CONFIG GpioInfo
  1101. // Arg1 -> In case of PCH Gpio Read {GPIO TX(0)/RX(1) State indicator}
  1102. // Return: Value
  1103. //
  1104. Method(RDGP, 2, Serialized)
  1105. {
  1106. Store(1, Local7)
  1107. Store(Arg0, Local0)
  1108. Store(Arg0, Local1)
  1109. And(Local0, 0xFFFFFFFF, Local0) // Low 32 bits (31:00)
  1110. ShiftRight(Local1, 32, Local1) // High 32 bits (63:32)
  1111. If (LEqual(And(Local0, 0xFF), 1))
  1112. {
  1113. // PCH
  1114. Store(\_SB.CGRD(Local1, Arg1), Local7)
  1115. }
  1116. Return(Local7)
  1117. } // End of Method(RDGP, 2, Serialized)
  1118. } // End of Scope(\_SB)
  1119. Scope(\_SB)
  1120. {
  1121. // Asserts/De-asserts TBT force power
  1122. Method(TBFP, 2)
  1123. {
  1124. If(Arg0)
  1125. {
  1126. // Implementation dependent way to assert TBT force power
  1127. If(LEqual(Arg1, 1)) {
  1128. CGWR(FPG0, FP0L)
  1129. }
  1130. Else {
  1131. CGWR(FPG1, FP1L)
  1132. }
  1133. }
  1134. Else
  1135. {
  1136. // Implementation dependent way to de-assert TBT force power
  1137. If(LEqual(Arg1, 1)) {
  1138. CGWR(FPG0, LNot(FP0L))
  1139. }
  1140. Else {
  1141. CGWR(FPG1, LNot(FP1L))
  1142. }
  1143. }
  1144. }
  1145. // WMI ACPI device to control TBT force power
  1146. Device(WMTF)
  1147. {
  1148. // pnp0c14 is pnp id assigned to WMI mapper
  1149. Name(_HID, "PNP0C14")
  1150. Name(_UID, "TBFP")
  1151. Name(_WDG, Buffer() {
  1152. // {86CCFD48-205E-4A77-9C48-2021CBEDE341}
  1153. 0x48, 0xFD, 0xCC, 0x86,
  1154. 0x5E, 0x20,
  1155. 0x77, 0x4A,
  1156. 0x9C, 0x48,
  1157. 0x20, 0x21, 0xCB, 0xED, 0xE3, 0x41,
  1158. 84, 70, // Object Id (TF)
  1159. 1, // Instance Count
  1160. 0x02 // Flags (WMIACPI_REGFLAG_METHOD)
  1161. })
  1162. // Set TBT force power
  1163. // Arg2 is force power value
  1164. Method(WMTF, 3)
  1165. {
  1166. CreateByteField(Arg2,0,FP)
  1167. If(FP)
  1168. {
  1169. TBFP(1, 1)
  1170. }
  1171. Else
  1172. {
  1173. TBFP(0, 1)
  1174. }
  1175. }
  1176. }
  1177. } // End of Scope(\_SB)
  1178. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 1),LEqual(RPS1, 1))))
  1179. {
  1180. Scope(\_SB.PCI0.RP01)
  1181. {
  1182. Device(HRUS)// Host router Upstream port
  1183. {
  1184. Name(_ADR, 0x00000000)
  1185. Method(_RMV)
  1186. {
  1187. Return(TARS)
  1188. } // end _RMV
  1189. }
  1190. }//End of Scope(\_SB.PCI0.RP01)
  1191. }
  1192. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 2),LEqual(RPS1, 2))))
  1193. {
  1194. Scope(\_SB.PCI0.RP02)
  1195. {
  1196. Device(HRUS)// Host router Upstream port
  1197. {
  1198. Name(_ADR, 0x00000000)
  1199. Method(_RMV)
  1200. {
  1201. Return(TARS)
  1202. } // end _RMV
  1203. }
  1204. }//End of Scope(\_SB.PCI0.RP02)
  1205. }
  1206. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 3),LEqual(RPS1, 3))))
  1207. {
  1208. Scope(\_SB.PCI0.RP03)
  1209. {
  1210. Device(HRUS)// Host router Upstream port
  1211. {
  1212. Name(_ADR, 0x00000000)
  1213. Method(_RMV)
  1214. {
  1215. Return(TARS)
  1216. } // end _RMV
  1217. }
  1218. }//End of Scope(\_SB.PCI0.RP03)
  1219. }
  1220. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 4),LEqual(RPS1, 4))))
  1221. {
  1222. Scope(\_SB.PCI0.RP04)
  1223. {
  1224. Device(HRUS)// Host router Upstream port
  1225. {
  1226. Name(_ADR, 0x00000000)
  1227. Method(_RMV)
  1228. {
  1229. Return(TARS)
  1230. } // end _RMV
  1231. }
  1232. }//End of Scope(\_SB.PCI0.RP04)
  1233. }
  1234. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 5),LEqual(RPS1, 5))))
  1235. {
  1236. Scope(\_SB.PCI0.RP05)
  1237. {
  1238. Device(HRUS)// Host router Upstream port
  1239. {
  1240. Name(_ADR, 0x00000000)
  1241. Method(_RMV)
  1242. {
  1243. Return(TARS)
  1244. } // end _RMV
  1245. }
  1246. }//End of Scope(\_SB.PCI0.RP05)
  1247. }
  1248. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 6),LEqual(RPS1, 6))))
  1249. {
  1250. Scope(\_SB.PCI0.RP06)
  1251. {
  1252. Device(HRUS)// Host router Upstream port
  1253. {
  1254. Name(_ADR, 0x00000000)
  1255. Method(_RMV)
  1256. {
  1257. Return(TARS)
  1258. } // end _RMV
  1259. }
  1260. }//End of Scope(\_SB.PCI0.RP06)
  1261. }
  1262. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 7),LEqual(RPS1, 7))))
  1263. {
  1264. Scope(\_SB.PCI0.RP07)
  1265. {
  1266. Device(HRUS)// Host router Upstream port
  1267. {
  1268. Name(_ADR, 0x00000000)
  1269. Method(_RMV)
  1270. {
  1271. Return(TARS)
  1272. } // end _RMV
  1273. }
  1274. }//End of Scope(\_SB.PCI0.RP07)
  1275. }
  1276. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 8),LEqual(RPS1, 8))))
  1277. {
  1278. Scope(\_SB.PCI0.RP08)
  1279. {
  1280. Device(HRUS)// Host router Upstream port
  1281. {
  1282. Name(_ADR, 0x00000000)
  1283. Method(_RMV)
  1284. {
  1285. Return(TARS)
  1286. } // end _RMV
  1287. }
  1288. }//End of Scope(\_SB.PCI0.RP08)
  1289. }
  1290. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 9),LEqual(RPS1, 9))))
  1291. {
  1292. Scope(\_SB.PCI0.RP09)
  1293. {
  1294. Device(HRUS)// Host router Upstream port
  1295. {
  1296. Name(_ADR, 0x00000000)
  1297. Method(_RMV)
  1298. {
  1299. Return(TARS)
  1300. } // end _RMV
  1301. }
  1302. }//End of Scope(\_SB.PCI0.RP09)
  1303. }
  1304. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 10),LEqual(RPS1, 10))))
  1305. {
  1306. Scope(\_SB.PCI0.RP10)
  1307. {
  1308. Device(HRUS)// Host router Upstream port
  1309. {
  1310. Name(_ADR, 0x00000000)
  1311. Method(_RMV)
  1312. {
  1313. Return(TARS)
  1314. } // end _RMV
  1315. }
  1316. }//End of Scope(\_SB.PCI0.RP10)
  1317. }
  1318. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 11),LEqual(RPS1, 11))))
  1319. {
  1320. Scope(\_SB.PCI0.RP11)
  1321. {
  1322. Device(HRUS)// Host router Upstream port
  1323. {
  1324. Name(_ADR, 0x00000000)
  1325. Method(_RMV)
  1326. {
  1327. Return(TARS)
  1328. } // end _RMV
  1329. }
  1330. }//End of Scope(\_SB.PCI0.RP11)
  1331. }
  1332. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 12),LEqual(RPS1, 12))))
  1333. {
  1334. Scope(\_SB.PCI0.RP12)
  1335. {
  1336. Device(HRUS)// Host router Upstream port
  1337. {
  1338. Name(_ADR, 0x00000000)
  1339. Method(_RMV)
  1340. {
  1341. Return(TARS)
  1342. } // end _RMV
  1343. }
  1344. }//End of Scope(\_SB.PCI0.RP12)
  1345. }
  1346. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 13),LEqual(RPS1, 13))))
  1347. {
  1348. Scope(\_SB.PCI0.RP13)
  1349. {
  1350. Device(HRUS)// Host router Upstream port
  1351. {
  1352. Name(_ADR, 0x00000000)
  1353. Method(_RMV)
  1354. {
  1355. Return(TARS)
  1356. } // end _RMV
  1357. }
  1358. }//End of Scope(\_SB.PCI0.RP13)
  1359. }
  1360. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 14),LEqual(RPS1, 14))))
  1361. {
  1362. Scope(\_SB.PCI0.RP14)
  1363. {
  1364. Device(HRUS)// Host router Upstream port
  1365. {
  1366. Name(_ADR, 0x00000000)
  1367. Method(_RMV)
  1368. {
  1369. Return(TARS)
  1370. } // end _RMV
  1371. }
  1372. }//End of Scope(\_SB.PCI0.RP14)
  1373. }
  1374. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 15),LEqual(RPS1, 15))))
  1375. {
  1376. Scope(\_SB.PCI0.RP15)
  1377. {
  1378. Device(HRUS)// Host router Upstream port
  1379. {
  1380. Name(_ADR, 0x00000000)
  1381. Method(_RMV)
  1382. {
  1383. Return(TARS)
  1384. } // end _RMV
  1385. }
  1386. }//End of Scope(\_SB.PCI0.RP15)
  1387. }
  1388. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 16),LEqual(RPS1, 16))))
  1389. {
  1390. Scope(\_SB.PCI0.RP16)
  1391. {
  1392. Device(HRUS)// Host router Upstream port
  1393. {
  1394. Name(_ADR, 0x00000000)
  1395. Method(_RMV)
  1396. {
  1397. Return(TARS)
  1398. } // end _RMV
  1399. }
  1400. }//End of Scope(\_SB.PCI0.RP16)
  1401. }
  1402. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 17),LEqual(RPS1, 17))))
  1403. {
  1404. Scope(\_SB.PCI0.RP17)
  1405. {
  1406. Device(HRUS)// Host router Upstream port
  1407. {
  1408. Name(_ADR, 0x00000000)
  1409. Method(_RMV)
  1410. {
  1411. Return(TARS)
  1412. } // end _RMV
  1413. }
  1414. }//End of Scope(\_SB.PCI0.RP17)
  1415. }
  1416. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 18),LEqual(RPS1, 18))))
  1417. {
  1418. Scope(\_SB.PCI0.RP18)
  1419. {
  1420. Device(HRUS)// Host router Upstream port
  1421. {
  1422. Name(_ADR, 0x00000000)
  1423. Method(_RMV)
  1424. {
  1425. Return(TARS)
  1426. } // end _RMV
  1427. }
  1428. }//End of Scope(\_SB.PCI0.RP18)
  1429. }
  1430. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 19),LEqual(RPS1, 19))))
  1431. {
  1432. Scope(\_SB.PCI0.RP19)
  1433. {
  1434. Device(HRUS)// Host router Upstream port
  1435. {
  1436. Name(_ADR, 0x00000000)
  1437. Method(_RMV)
  1438. {
  1439. Return(TARS)
  1440. } // end _RMV
  1441. }
  1442. }//End of Scope(\_SB.PCI0.RP19)
  1443. }
  1444. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 20),LEqual(RPS1, 20))))
  1445. {
  1446. Scope(\_SB.PCI0.RP20)
  1447. {
  1448. Device(HRUS)// Host router Upstream port
  1449. {
  1450. Name(_ADR, 0x00000000)
  1451. Method(_RMV)
  1452. {
  1453. Return(TARS)
  1454. } // end _RMV
  1455. }
  1456. }//End of Scope(\_SB.PCI0.RP20)
  1457. }
  1458. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 21),LEqual(RPS1, 21))))
  1459. {
  1460. Scope(\_SB.PCI0.PEG0)
  1461. {
  1462. Device(HRUS)// Host router Upstream port
  1463. {
  1464. Name(_ADR, 0x00000000)
  1465. Method(_RMV)
  1466. {
  1467. Return(TARS)
  1468. } // end _RMV
  1469. }
  1470. }//End of Scope(\_SB.PCI0.PEG0)
  1471. }
  1472. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 22),LEqual(RPS1, 22))))
  1473. {
  1474. Scope(\_SB.PCI0.PEG1)
  1475. {
  1476. Device(HRUS)// Host router Upstream port
  1477. {
  1478. Name(_ADR, 0x00000000)
  1479. Method(_RMV)
  1480. {
  1481. Return(TARS)
  1482. } // end _RMV
  1483. }
  1484. }//End of Scope(\_SB.PCI0.PEG1)
  1485. }
  1486. If(LAnd(LEqual(TBTS, 1),LOr(LEqual(RPS0, 23),LEqual(RPS1, 23))))
  1487. {
  1488. Scope(\_SB.PCI0.PEG2)
  1489. {
  1490. Device(HRUS)// Host router Upstream port
  1491. {
  1492. Name(_ADR, 0x00000000)
  1493. Method(_RMV)
  1494. {
  1495. Return(TARS)
  1496. } // end _RMV
  1497. }
  1498. }//End of Scope(\_SB.PCI0.PEG2)
  1499. }
  1500. Scope(\_SB)
  1501. {
  1502. //
  1503. // Name: PERB
  1504. // Description: Function to read a Byte from PCIE-MMIO
  1505. // Input: Arg0 -> PCIE base address
  1506. // Arg1 -> Bus
  1507. // Arg2 -> Device
  1508. // Arg3 -> Function
  1509. // Arg4 -> Register offset
  1510. // Return: Byte data read from PCIE-MMIO
  1511. //
  1512. Method(PERB,5,Serialized)
  1513. {
  1514. ADBG("PERB")
  1515. Store(Arg0, Local7)
  1516. Or(Local7, ShiftLeft(Arg1, 20), Local7)
  1517. Or(Local7, ShiftLeft(Arg2, 15), Local7)
  1518. Or(Local7, ShiftLeft(Arg3, 12), Local7)
  1519. Or(Local7, Arg4, Local7)
  1520. OperationRegion(PCI0, SystemMemory, Local7, 1)
  1521. Field(PCI0, ByteAcc,NoLock,Preserve)
  1522. {
  1523. TEMP, 8
  1524. }
  1525. Return(TEMP)
  1526. } // End of Method(PERB,5,Serialized)
  1527. //
  1528. // Name: PEWB
  1529. // Description: Function to write a Byte into PCIE-MMIO
  1530. // Input: Arg0 -> PCIE base address
  1531. // Arg1 -> Bus
  1532. // Arg2 -> Device
  1533. // Arg3 -> Function
  1534. // Arg4 -> Register offset
  1535. // Arg5 -> Data
  1536. // Return: Nothing
  1537. //
  1538. Method(PEWB,6,Serialized)
  1539. {
  1540. ADBG("PEWB")
  1541. Store(Arg0, Local7)
  1542. Or(Local7, ShiftLeft(Arg1, 20), Local7)
  1543. Or(Local7, ShiftLeft(Arg2, 15), Local7)
  1544. Or(Local7, ShiftLeft(Arg3, 12), Local7)
  1545. Or(Local7, Arg4, Local7)
  1546. OperationRegion(PCI0, SystemMemory, Local7, 1)
  1547. Field(PCI0, ByteAcc,NoLock,Preserve)
  1548. {
  1549. TEMP, 8
  1550. }
  1551. Store(Arg5,TEMP)
  1552. } // End of Method(PEWB,6,Serialized)
  1553. //
  1554. // Name: PERW
  1555. // Description: Function to read a Word from PCIE-MMIO
  1556. // Input: Arg0 -> PCIE base address
  1557. // Arg1 -> Bus
  1558. // Arg2 -> Device
  1559. // Arg3 -> Function
  1560. // Arg4 -> Register offset
  1561. // Return: Word data read from PCIE-MMIO
  1562. //
  1563. Method(PERW,5,Serialized)
  1564. {
  1565. ADBG("PERW")
  1566. Store(Arg0, Local7)
  1567. Or(Local7, ShiftLeft(Arg1, 20), Local7)
  1568. Or(Local7, ShiftLeft(Arg2, 15), Local7)
  1569. Or(Local7, ShiftLeft(Arg3, 12), Local7)
  1570. Or(Local7, Arg4, Local7)
  1571. OperationRegion(PCI0, SystemMemory, Local7, 2)
  1572. Field(PCI0, ByteAcc,NoLock,Preserve)
  1573. {
  1574. TEMP, 16
  1575. }
  1576. Return(TEMP)
  1577. } // End of Method(PERW,5,Serialized)
  1578. //
  1579. // Name: PEWW
  1580. // Description: Function to write a Word into PCIE-MMIO
  1581. // Input: Arg0 -> PCIE base address
  1582. // Arg1 -> Bus
  1583. // Arg2 -> Device
  1584. // Arg3 -> Function
  1585. // Arg4 -> Register offset
  1586. // Arg5 -> Data
  1587. // Return: Nothing
  1588. //
  1589. Method(PEWW,6,Serialized)
  1590. {
  1591. ADBG("PEWW")
  1592. Store(Arg0, Local7)
  1593. Or(Local7, ShiftLeft(Arg1, 20), Local7)
  1594. Or(Local7, ShiftLeft(Arg2, 15), Local7)
  1595. Or(Local7, ShiftLeft(Arg3, 12), Local7)
  1596. Or(Local7, Arg4, Local7)
  1597. OperationRegion(PCI0, SystemMemory, Local7, 2)
  1598. Field(PCI0, ByteAcc,NoLock,Preserve)
  1599. {
  1600. TEMP, 16
  1601. }
  1602. Store(Arg5,TEMP)
  1603. } // End of Method(PEWW,6,Serialized)
  1604. //
  1605. // Name: PERD
  1606. // Description: Function to read a Dword from PCIE-MMIO
  1607. // Input: Arg0 -> PCIE base address
  1608. // Arg1 -> Bus
  1609. // Arg2 -> Device
  1610. // Arg3 -> Function
  1611. // Arg4 -> Register offset
  1612. // Return: Dword data read from PCIE-MMIO
  1613. //
  1614. Method(PERD,5,Serialized)
  1615. {
  1616. ADBG("PERD")
  1617. Store(Arg0, Local7)
  1618. Or(Local7, ShiftLeft(Arg1, 20), Local7)
  1619. Or(Local7, ShiftLeft(Arg2, 15), Local7)
  1620. Or(Local7, ShiftLeft(Arg3, 12), Local7)
  1621. Or(Local7, Arg4, Local7)
  1622. OperationRegion(PCI0, SystemMemory, Local7, 4)
  1623. Field(PCI0, ByteAcc,NoLock,Preserve)
  1624. {
  1625. TEMP, 32
  1626. }
  1627. Return(TEMP)
  1628. } // End of Method(PERD,5,Serialized)
  1629. //
  1630. // Name: PEWD
  1631. // Description: Function to write a Dword into PCIE-MMIO
  1632. // Input: Arg0 -> PCIE base address
  1633. // Arg1 -> Bus
  1634. // Arg2 -> Device
  1635. // Arg3 -> Function
  1636. // Arg4 -> Register offset
  1637. // Arg5 -> Data
  1638. // Return: Nothing
  1639. //
  1640. Method(PEWD,6,Serialized)
  1641. {
  1642. ADBG("PEWD")
  1643. Store(Arg0, Local7)
  1644. Or(Local7, ShiftLeft(Arg1, 20), Local7)
  1645. Or(Local7, ShiftLeft(Arg2, 15), Local7)
  1646. Or(Local7, ShiftLeft(Arg3, 12), Local7)
  1647. Or(Local7, Arg4, Local7)
  1648. OperationRegion(PCI0, SystemMemory, Local7, 4)
  1649. Field(PCI0, ByteAcc,NoLock,Preserve)
  1650. {
  1651. TEMP, 32
  1652. }
  1653. Store(Arg5,TEMP)
  1654. } // End of Method(PEWD,6,Serialized)
  1655. //
  1656. // Name: STDC
  1657. // Description: Function to get Standard Capability Register Offset
  1658. // Input: Arg0 -> PCIE base address
  1659. // Arg1 -> Bus
  1660. // Arg2 -> Device
  1661. // Arg3 -> Function
  1662. // Arg4 -> Capability ID
  1663. // Return: Capability Register Offset data
  1664. //
  1665. Method(STDC,5,Serialized)
  1666. {
  1667. ADBG("STDC")
  1668. //Check for Referenced device is present or not
  1669. Store(PERW(Arg0, Arg1, Arg2, Arg3, 0x00), Local7) //Vendor ID register
  1670. If(LEqual(Local7, 0xFFFF))
  1671. {
  1672. ADBG("Referenced device is not present")
  1673. Return(0)
  1674. }
  1675. Store(PERW(Arg0, Arg1, Arg2, Arg3, 0x06), Local0) //Device Status register
  1676. If (LEqual(And(Local0, 16), 0)) //Bit4 - Capabilities List
  1677. {
  1678. //No Capabilities linked list is available
  1679. ADBG("No Capabilities linked list is available")
  1680. Return(0)
  1681. }
  1682. //Local1 is for storing CapabilityID
  1683. //Local2 is for storing CapabilityPtr
  1684. Store(PERB(Arg0, Arg1, Arg2, Arg3, 0x34), Local2) //CapabilityPtr
  1685. While(1)
  1686. {
  1687. And(Local2, 0xFC, Local2) //Each capability must be DWORD aligned
  1688. If(LEqual(Local2, 0)) //A pointer value of 00h is used to indicate the last capability in the list
  1689. {
  1690. ADBG("Capability ID is not found")
  1691. Return(0)
  1692. }
  1693. Store(PERB(Arg0, Arg1, Arg2, Arg3, Local2), Local1) //CapabilityID
  1694. If(LEqual(Arg4, Local1)) //CapabilityID match
  1695. {
  1696. ADBG("Capability ID is found")
  1697. ADBG("Capability Offset : ")
  1698. ADBG(Local2)
  1699. Return(Local2)
  1700. }
  1701. Store(PERB(Arg0, Arg1, Arg2, Arg3, Add(Local2, 1)), Local2) //CapabilityPtr
  1702. Return(0)
  1703. }
  1704. } // End of Method(STDC,5,Serialized)
  1705. } // End Scope(\_SB)