PciHotPlug.c 13 KB

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  1. /** @file
  2. Pci Hotplug Driver : This file will perform specific PCI-EXPRESS
  3. Devics resource configuration.
  4. Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
  5. SPDX-License-Identifier: BSD-2-Clause-Patent
  6. **/
  7. //
  8. // Statements that include other files
  9. //
  10. #include "PciHotPlug.h"
  11. #include <Ppi/SiPolicy.h>
  12. #include <TbtBoardInfo.h>
  13. #include <Library/PchPcieRpLib.h>
  14. #include <Library/TbtCommonLib.h>
  15. #define PCIE_NUM (20)
  16. #define PEG_NUM (3)
  17. #define PADDING_BUS (1)
  18. #define PADDING_NONPREFETCH_MEM (1)
  19. #define PADDING_PREFETCH_MEM (1)
  20. #define PADDING_IO (1)
  21. #define PADDING_NUM (PADDING_BUS + PADDING_NONPREFETCH_MEM + PADDING_PREFETCH_MEM + PADDING_IO)
  22. GLOBAL_REMOVE_IF_UNREFERENCED EFI_HPC_LOCATION mPcieLocation[PCIE_NUM + PEG_NUM];
  23. GLOBAL_REMOVE_IF_UNREFERENCED UINTN mHpcCount = 0;
  24. GLOBAL_REMOVE_IF_UNREFERENCED PCIE_HOT_PLUG_DEVICE_PATH mHotplugPcieDevicePathTemplate = {
  25. ACPI,
  26. PCI(0xFF, 0xFF), // Dummy Device no & Function no
  27. END
  28. };
  29. /**
  30. Entry point for the driver.
  31. This routine reads the PlatformType GPI on FWH and produces a protocol
  32. to be consumed by the chipset driver to effect those settings.
  33. @param[in] ImageHandle An image handle.
  34. @param[in] SystemTable A pointer to the system table.
  35. @retval EFI_SUCCESS.
  36. **/
  37. EFI_STATUS
  38. EFIAPI
  39. PciHotPlug (
  40. IN EFI_HANDLE ImageHandle,
  41. IN EFI_SYSTEM_TABLE *SystemTable
  42. )
  43. {
  44. EFI_STATUS Status;
  45. PCI_HOT_PLUG_INSTANCE *PciHotPlug;
  46. UINTN Index;
  47. UINTN RpDev;
  48. UINTN RpFunc;
  49. PCIE_HOT_PLUG_DEVICE_PATH *HotplugPcieDevicePath;
  50. UINT32 PcieRootPortHpeData = 0;
  51. DEBUG ((DEBUG_INFO, "PciHotPlug Entry\n"));
  52. PcieRootPortHpeData = PcdGet32 (PcdPchPcieRootPortHpe);
  53. //
  54. // PCH Rootports Hotplug device path creation
  55. //
  56. for (Index = 0; Index < PCIE_NUM; Index++) {
  57. if (((PcieRootPortHpeData >> Index) & BIT0) == BIT0) { // Check the Rootport no's hotplug is set
  58. Status = GetPchPcieRpDevFun (Index, &RpDev, &RpFunc); // Get the actual device/function no corresponding to the Rootport no provided
  59. ASSERT_EFI_ERROR (Status);
  60. HotplugPcieDevicePath = NULL;
  61. HotplugPcieDevicePath = AllocatePool (sizeof (PCIE_HOT_PLUG_DEVICE_PATH));
  62. ASSERT (HotplugPcieDevicePath != NULL);
  63. if (HotplugPcieDevicePath == NULL) {
  64. return EFI_OUT_OF_RESOURCES;
  65. }
  66. CopyMem (HotplugPcieDevicePath, &mHotplugPcieDevicePathTemplate, sizeof (PCIE_HOT_PLUG_DEVICE_PATH));
  67. HotplugPcieDevicePath->PciRootPortNode.Device = (UINT8) RpDev; // Update real Device no
  68. HotplugPcieDevicePath->PciRootPortNode.Function = (UINT8) RpFunc; // Update real Function no
  69. mPcieLocation[mHpcCount].HpcDevicePath = (EFI_DEVICE_PATH_PROTOCOL *)HotplugPcieDevicePath;
  70. mPcieLocation[mHpcCount].HpbDevicePath = (EFI_DEVICE_PATH_PROTOCOL *)HotplugPcieDevicePath;
  71. mHpcCount++;
  72. DEBUG ((DEBUG_INFO, "(%02d) PciHotPlug (PCH RP#) : Bus 0x00, Device 0x%x, Function 0x%x is added to the Hotplug Device Path list \n", mHpcCount, RpDev, RpFunc));
  73. }
  74. }
  75. PciHotPlug = AllocatePool (sizeof (PCI_HOT_PLUG_INSTANCE));
  76. ASSERT (PciHotPlug != NULL);
  77. if (PciHotPlug == NULL) {
  78. return EFI_OUT_OF_RESOURCES;
  79. }
  80. //
  81. // Initialize driver private data.
  82. //
  83. ZeroMem (PciHotPlug, sizeof (PCI_HOT_PLUG_INSTANCE));
  84. PciHotPlug->Signature = PCI_HOT_PLUG_DRIVER_PRIVATE_SIGNATURE;
  85. PciHotPlug->HotPlugInitProtocol.GetRootHpcList = GetRootHpcList;
  86. PciHotPlug->HotPlugInitProtocol.InitializeRootHpc = InitializeRootHpc;
  87. PciHotPlug->HotPlugInitProtocol.GetResourcePadding = GetResourcePadding;
  88. Status = gBS->InstallProtocolInterface (
  89. &PciHotPlug->Handle,
  90. &gEfiPciHotPlugInitProtocolGuid,
  91. EFI_NATIVE_INTERFACE,
  92. &PciHotPlug->HotPlugInitProtocol
  93. );
  94. ASSERT_EFI_ERROR (Status);
  95. return EFI_SUCCESS;
  96. }
  97. /**
  98. This procedure returns a list of Root Hot Plug controllers that require
  99. initialization during boot process
  100. @param[in] This The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol.
  101. @param[out] HpcCount The number of Root HPCs returned.
  102. @param[out] HpcList The list of Root HPCs. HpcCount defines the number of elements in this list.
  103. @retval EFI_SUCCESS.
  104. **/
  105. EFI_STATUS
  106. EFIAPI
  107. GetRootHpcList (
  108. IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
  109. OUT UINTN *HpcCount,
  110. OUT EFI_HPC_LOCATION **HpcList
  111. )
  112. {
  113. *HpcCount = mHpcCount;
  114. *HpcList = mPcieLocation;
  115. return EFI_SUCCESS;
  116. }
  117. /**
  118. This procedure Initializes one Root Hot Plug Controller
  119. This process may casue initialization of its subordinate buses
  120. @param[in] This The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol.
  121. @param[in] HpcDevicePath The Device Path to the HPC that is being initialized.
  122. @param[in] HpcPciAddress The address of the Hot Plug Controller function on the PCI bus.
  123. @param[in] Event The event that should be signaled when the Hot Plug Controller initialization is complete. Set to NULL if the caller wants to wait until the entire initialization process is complete. The event must be of the type EFI_EVT_SIGNAL.
  124. @param[out] HpcState The state of the Hot Plug Controller hardware. The type EFI_Hpc_STATE is defined in section 3.1.
  125. @retval EFI_SUCCESS.
  126. **/
  127. EFI_STATUS
  128. EFIAPI
  129. InitializeRootHpc (
  130. IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
  131. IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
  132. IN UINT64 HpcPciAddress,
  133. IN EFI_EVENT Event, OPTIONAL
  134. OUT EFI_HPC_STATE *HpcState
  135. )
  136. {
  137. if (Event) {
  138. gBS->SignalEvent (Event);
  139. }
  140. *HpcState = EFI_HPC_STATE_INITIALIZED;
  141. return EFI_SUCCESS;
  142. }
  143. /**
  144. Returns the resource padding required by the PCI bus that is controlled by the specified Hot Plug Controller.
  145. @param[in] This The pointer to the instance of the EFI_PCI_HOT_PLUG_INIT protocol. initialized.
  146. @param[in] HpcDevicePath The Device Path to the Hot Plug Controller.
  147. @param[in] HpcPciAddress The address of the Hot Plug Controller function on the PCI bus.
  148. @param[out] HpcState The state of the Hot Plug Controller hardware. The type EFI_HPC_STATE is defined in section 3.1.
  149. @param[out] Padding This is the amount of resource padding required by the PCI bus under the control of the specified Hpc. Since the caller does not know the size of this buffer, this buffer is allocated by the callee and freed by the caller.
  150. @param[out] Attribute Describes how padding is accounted for.
  151. @retval EFI_SUCCESS.
  152. **/
  153. EFI_STATUS
  154. EFIAPI
  155. GetResourcePadding (
  156. IN EFI_PCI_HOT_PLUG_INIT_PROTOCOL *This,
  157. IN EFI_DEVICE_PATH_PROTOCOL *HpcDevicePath,
  158. IN UINT64 HpcPciAddress,
  159. OUT EFI_HPC_STATE *HpcState,
  160. OUT VOID **Padding,
  161. OUT EFI_HPC_PADDING_ATTRIBUTES *Attributes
  162. )
  163. {
  164. EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *PaddingResource;
  165. EFI_STATUS Status;
  166. UINT8 RsvdExtraBusNum = 0;
  167. UINT16 RsvdPcieMegaMem = 10;
  168. UINT8 PcieMemAddrRngMax = 0;
  169. UINT16 RsvdPciePMegaMem = 10;
  170. UINT8 PciePMemAddrRngMax = 0;
  171. UINT8 RsvdTbtExtraBusNum = 0;
  172. UINT16 RsvdTbtPcieMegaMem = 10;
  173. UINT8 TbtPcieMemAddrRngMax = 0;
  174. UINT16 RsvdTbtPciePMegaMem = 10;
  175. UINT8 TbtPciePMemAddrRngMax = 0;
  176. UINT8 RsvdPcieKiloIo = 4;
  177. BOOLEAN SetResourceforTbt = FALSE;
  178. UINTN RpIndex;
  179. UINTN RpDev;
  180. UINTN RpFunc;
  181. DEBUG ((DEBUG_INFO, "GetResourcePadding : Start \n"));
  182. PaddingResource = AllocatePool (PADDING_NUM * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
  183. ASSERT (PaddingResource != NULL);
  184. if (PaddingResource == NULL) {
  185. return EFI_OUT_OF_RESOURCES;
  186. }
  187. *Padding = (VOID *) PaddingResource;
  188. RpDev = (UINTN) ((HpcPciAddress >> 16) & 0xFF);
  189. RpFunc = (UINTN) ((HpcPciAddress >> 8) & 0xFF);
  190. // Get the actual Rootport no corresponding to the device/function no provided
  191. if (RpDev == SA_PEG_DEV_NUM) {
  192. // PEG
  193. RpIndex = PCIE_NUM + RpFunc;
  194. DEBUG ((DEBUG_INFO, "GetResourcePadding : PEG Rootport no %02d Bus 0x00, Device 0x%x, Function 0x%x \n", (RpIndex-PCIE_NUM), RpDev, RpFunc));
  195. } else {
  196. // PCH
  197. Status = GetPchPcieRpNumber (RpDev, RpFunc, &RpIndex);
  198. DEBUG ((DEBUG_INFO, "GetResourcePadding : PCH Rootport no %02d Bus 0x00, Device 0x%x, Function 0x%x \n", RpIndex, RpDev, RpFunc));
  199. }
  200. GetRootporttoSetResourcesforTbt(RpIndex, &RsvdTbtExtraBusNum, &RsvdTbtPcieMegaMem ,&TbtPcieMemAddrRngMax ,&RsvdTbtPciePMegaMem ,&TbtPciePMemAddrRngMax, &SetResourceforTbt);
  201. if (SetResourceforTbt) {
  202. RsvdExtraBusNum = RsvdTbtExtraBusNum;
  203. RsvdPcieMegaMem = RsvdTbtPcieMegaMem;
  204. PcieMemAddrRngMax = TbtPcieMemAddrRngMax;
  205. RsvdPciePMegaMem = RsvdTbtPciePMegaMem;
  206. PciePMemAddrRngMax = TbtPciePMemAddrRngMax;
  207. }
  208. //
  209. // Padding for bus
  210. //
  211. ZeroMem (PaddingResource, PADDING_NUM * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR));
  212. *Attributes = EfiPaddingPciBus;
  213. PaddingResource->Desc = 0x8A;
  214. PaddingResource->Len = 0x2B;
  215. PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_BUS;
  216. PaddingResource->GenFlag = 0x0;
  217. PaddingResource->SpecificFlag = 0;
  218. PaddingResource->AddrRangeMin = 0;
  219. PaddingResource->AddrRangeMax = 0;
  220. PaddingResource->AddrLen = RsvdExtraBusNum;
  221. //
  222. // Padding for non-prefetchable memory
  223. //
  224. PaddingResource++;
  225. PaddingResource->Desc = 0x8A;
  226. PaddingResource->Len = 0x2B;
  227. PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
  228. PaddingResource->GenFlag = 0x0;
  229. if (SetResourceforTbt) {
  230. PaddingResource->AddrSpaceGranularity = 32;
  231. } else {
  232. PaddingResource->AddrSpaceGranularity = 32;
  233. }
  234. PaddingResource->SpecificFlag = 0;
  235. //
  236. // Pad non-prefetchable
  237. //
  238. PaddingResource->AddrRangeMin = 0;
  239. PaddingResource->AddrLen = RsvdPcieMegaMem * 0x100000;
  240. if (SetResourceforTbt) {
  241. PaddingResource->AddrRangeMax = (1 << PcieMemAddrRngMax) - 1;
  242. } else {
  243. PaddingResource->AddrRangeMax = 1;
  244. }
  245. //
  246. // Padding for prefetchable memory
  247. //
  248. PaddingResource++;
  249. PaddingResource->Desc = 0x8A;
  250. PaddingResource->Len = 0x2B;
  251. PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_MEM;
  252. PaddingResource->GenFlag = 0x0;
  253. if (SetResourceforTbt) {
  254. PaddingResource->AddrSpaceGranularity = 32;
  255. } else {
  256. PaddingResource->AddrSpaceGranularity = 32;
  257. }
  258. PaddingResource->SpecificFlag = 06;
  259. //
  260. // Padding for prefetchable memory
  261. //
  262. PaddingResource->AddrRangeMin = 0;
  263. if (SetResourceforTbt) {
  264. PaddingResource->AddrLen = RsvdPciePMegaMem * 0x100000;
  265. } else {
  266. PaddingResource->AddrLen = RsvdPcieMegaMem * 0x100000;
  267. }
  268. //
  269. // Pad 16 MB of MEM
  270. //
  271. if (SetResourceforTbt) {
  272. PaddingResource->AddrRangeMax = (1 << PciePMemAddrRngMax) - 1;
  273. } else {
  274. PaddingResource->AddrRangeMax = 1;
  275. }
  276. //
  277. // Alignment
  278. //
  279. // Padding for I/O
  280. //
  281. PaddingResource++;
  282. PaddingResource->Desc = 0x8A;
  283. PaddingResource->Len = 0x2B;
  284. PaddingResource->ResType = ACPI_ADDRESS_SPACE_TYPE_IO;
  285. PaddingResource->GenFlag = 0x0;
  286. PaddingResource->SpecificFlag = 0;
  287. PaddingResource->AddrRangeMin = 0;
  288. PaddingResource->AddrLen = RsvdPcieKiloIo * 0x400;
  289. //
  290. // Pad 4K of IO
  291. //
  292. PaddingResource->AddrRangeMax = 1;
  293. //
  294. // Alignment
  295. //
  296. // Terminate the entries.
  297. //
  298. PaddingResource++;
  299. ((EFI_ACPI_END_TAG_DESCRIPTOR *) PaddingResource)->Desc = ACPI_END_TAG_DESCRIPTOR;
  300. ((EFI_ACPI_END_TAG_DESCRIPTOR *) PaddingResource)->Checksum = 0x0;
  301. *HpcState = EFI_HPC_STATE_INITIALIZED | EFI_HPC_STATE_ENABLED;
  302. return EFI_SUCCESS;
  303. }