PciTree.asl 10 KB

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  1. /** @file
  2. ACPI DSDT table
  3. Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. Scope(\_SB) {
  7. Name(PD00, Package(){
  8. // If the setting changed in PCH PxRcConfig policy, platform should also update static assignment here.
  9. // PCI Bridge
  10. // D31: cAVS, SMBus, GbE, Nothpeak
  11. Package(){0x001FFFFF, 0, 0, 11 },
  12. Package(){0x001FFFFF, 1, 0, 10 },
  13. Package(){0x001FFFFF, 2, 0, 11 },
  14. Package(){0x001FFFFF, 3, 0, 11 },
  15. // D30: SerialIo and SCS - can't use PIC
  16. // D29: PCI Express Port 9-16
  17. Package(){0x001DFFFF, 0, 0, 11 },
  18. Package(){0x001DFFFF, 1, 0, 10 },
  19. Package(){0x001DFFFF, 2, 0, 11 },
  20. Package(){0x001DFFFF, 3, 0, 11 },
  21. // D28: PCI Express Port 1-8
  22. Package(){0x001CFFFF, 0, 0, 11 },
  23. Package(){0x001CFFFF, 1, 0, 10 },
  24. Package(){0x001CFFFF, 2, 0, 11 },
  25. Package(){0x001CFFFF, 3, 0, 11 },
  26. // D27: PCI Express Port 17-20
  27. Package(){0x001BFFFF, 0, 0, 11 },
  28. Package(){0x001BFFFF, 1, 0, 10 },
  29. Package(){0x001BFFFF, 2, 0, 11 },
  30. Package(){0x001BFFFF, 3, 0, 11 },
  31. // D25: SerialIo - can't use PIC
  32. // D23: SATA controller
  33. Package(){0x0017FFFF, 0, 0, 11 },
  34. // D22: CSME (HECI, IDE-R, Keyboard and Text redirection
  35. Package(){0x0016FFFF, 0, 0, 11 },
  36. Package(){0x0016FFFF, 1, 0, 10 },
  37. Package(){0x0016FFFF, 2, 0, 11 },
  38. Package(){0x0016FFFF, 3, 0, 11 },
  39. // D21: SerialIo - can't use PIC
  40. // D20: xHCI, OTG, Thermal Subsystem, Camera IO Host Controller
  41. // D20: xHCI, OTG, CNVi WiFi, SDcard
  42. Package(){0x0014FFFF, 0, 0, 11 },
  43. Package(){0x0014FFFF, 1, 0, 10 },
  44. Package(){0x0014FFFF, 2, 0, 11 },
  45. Package(){0x0014FFFF, 3, 0, 11 },
  46. // D19: Integrated Sensor Hub - can't use PIC
  47. // D18: Thermal, UFS, SerialIo SPI2 - can't use PIC
  48. Package(){0x0012FFFF, 0, 0, 11 },
  49. Package(){0x0012FFFF, 1, 0, 10 },
  50. Package(){0x0012FFFF, 2, 0, 11 },
  51. Package(){0x0012FFFF, 3, 0, 11 },
  52. // Host Bridge
  53. // P.E.G. Root Port D1F0
  54. Package(){0x0001FFFF, 0, 0, 11 },
  55. Package(){0x0001FFFF, 1, 0, 10 },
  56. Package(){0x0001FFFF, 2, 0, 11 },
  57. Package(){0x0001FFFF, 3, 0, 11 },
  58. // P.E.G. Root Port D1F1
  59. // P.E.G. Root Port D1F2
  60. // SA IGFX Device
  61. Package(){0x0002FFFF, 0, 0, 11 },
  62. // SA Thermal Device
  63. Package(){0x0004FFFF, 0, 0, 11 },
  64. // SA IPU Device
  65. Package(){0x0005FFFF, 0, 0, 11 },
  66. // SA GNA Device
  67. Package(){0x0008FFFF, 0, 0, 11 },
  68. })
  69. Name(AR00, Package(){
  70. // PCI Bridge
  71. // D31: cAVS, SMBus, GbE, Nothpeak
  72. Package(){0x001FFFFF, 0, 0, 16 },
  73. Package(){0x001FFFFF, 1, 0, 17 },
  74. Package(){0x001FFFFF, 2, 0, 18 },
  75. Package(){0x001FFFFF, 3, 0, 19 },
  76. // D30: SerialIo and SCS
  77. Package(){0x001EFFFF, 0, 0, 20 },
  78. Package(){0x001EFFFF, 1, 0, 21 },
  79. Package(){0x001EFFFF, 2, 0, 22 },
  80. Package(){0x001EFFFF, 3, 0, 23 },
  81. // D29: PCI Express Port 9-16
  82. Package(){0x001DFFFF, 0, 0, 16 },
  83. Package(){0x001DFFFF, 1, 0, 17 },
  84. Package(){0x001DFFFF, 2, 0, 18 },
  85. Package(){0x001DFFFF, 3, 0, 19 },
  86. // D28: PCI Express Port 1-8
  87. Package(){0x001CFFFF, 0, 0, 16 },
  88. Package(){0x001CFFFF, 1, 0, 17 },
  89. Package(){0x001CFFFF, 2, 0, 18 },
  90. Package(){0x001CFFFF, 3, 0, 19 },
  91. // D27: PCI Express Port 17-20
  92. Package(){0x001BFFFF, 0, 0, 16 },
  93. Package(){0x001BFFFF, 1, 0, 17 },
  94. Package(){0x001BFFFF, 2, 0, 18 },
  95. Package(){0x001BFFFF, 3, 0, 19 },
  96. // D26: eMMC
  97. Package(){0x001AFFFF, 0, 0, 16 },
  98. Package(){0x001AFFFF, 1, 0, 17 },
  99. Package(){0x001AFFFF, 2, 0, 18 },
  100. Package(){0x001AFFFF, 3, 0, 19 },
  101. // D25: SerialIo
  102. Package(){0x0019FFFF, 0, 0, 32 },
  103. Package(){0x0019FFFF, 1, 0, 33 },
  104. Package(){0x0019FFFF, 2, 0, 34 },
  105. // D23: SATA controller
  106. Package(){0x0017FFFF, 0, 0, 16 },
  107. // D22: CSME (HECI, IDE-R, Keyboard and Text redirection
  108. Package(){0x0016FFFF, 0, 0, 16 },
  109. Package(){0x0016FFFF, 1, 0, 17 },
  110. Package(){0x0016FFFF, 2, 0, 18 },
  111. Package(){0x0016FFFF, 3, 0, 19 },
  112. // D21: SerialIo
  113. Package(){0x0015FFFF, 0, 0, 16 },
  114. Package(){0x0015FFFF, 1, 0, 17 },
  115. Package(){0x0015FFFF, 2, 0, 18 },
  116. Package(){0x0015FFFF, 3, 0, 19 },
  117. // D20: xHCI, OTG, Thermal Subsystem, Camera IO Host Controller
  118. // D20: xHCI, OTG, CNVi WiFi, SDcard
  119. Package(){0x0014FFFF, 0, 0, 16 },
  120. Package(){0x0014FFFF, 1, 0, 17 },
  121. Package(){0x0014FFFF, 2, 0, 18 },
  122. Package(){0x0014FFFF, 3, 0, 19 },
  123. // D19: Integrated Sensor Hub
  124. Package(){0x0013FFFF, 0, 0, 20 },
  125. // D18: Thermal, UFS, SerialIo SPI 2
  126. Package(){0x0012FFFF, 0, 0, 16 },
  127. Package(){0x0012FFFF, 1, 0, 24 },
  128. Package(){0x0012FFFF, 2, 0, 18 },
  129. Package(){0x0012FFFF, 3, 0, 19 },
  130. // Host Bridge
  131. // P.E.G. Root Port D1F0
  132. Package(){0x0001FFFF, 0, 0, 16 },
  133. Package(){0x0001FFFF, 1, 0, 17 },
  134. Package(){0x0001FFFF, 2, 0, 18 },
  135. Package(){0x0001FFFF, 3, 0, 19 },
  136. // P.E.G. Root Port D1F1
  137. // P.E.G. Root Port D1F2
  138. // SA IGFX Device
  139. Package(){0x0002FFFF, 0, 0, 16 },
  140. // SA Thermal Device
  141. Package(){0x0004FFFF, 0, 0, 16 },
  142. // SA IPU Device
  143. Package(){0x0005FFFF, 0, 0, 16 },
  144. // SA GNA Device
  145. Package(){0x0008FFFF, 0, 0, 16 },
  146. })
  147. Name(PD04, Package(){
  148. Package(){0x0000FFFF, 0, 0, 11 },
  149. Package(){0x0000FFFF, 1, 0, 10 },
  150. Package(){0x0000FFFF, 2, 0, 11 },
  151. Package(){0x0000FFFF, 3, 0, 11 },
  152. })
  153. Name(AR04, Package(){
  154. Package(){0x0000FFFF, 0, 0, 16 },
  155. Package(){0x0000FFFF, 1, 0, 17 },
  156. Package(){0x0000FFFF, 2, 0, 18 },
  157. Package(){0x0000FFFF, 3, 0, 19 },
  158. })
  159. Name(PD05, Package(){
  160. Package(){0x0000FFFF, 0, 0, 10 },
  161. Package(){0x0000FFFF, 1, 0, 11 },
  162. Package(){0x0000FFFF, 2, 0, 11 },
  163. Package(){0x0000FFFF, 3, 0, 11 },
  164. })
  165. Name(AR05, Package(){
  166. Package(){0x0000FFFF, 0, 0, 17 },
  167. Package(){0x0000FFFF, 1, 0, 18 },
  168. Package(){0x0000FFFF, 2, 0, 19 },
  169. Package(){0x0000FFFF, 3, 0, 16 },
  170. })
  171. Name(PD06, Package(){
  172. Package(){0x0000FFFF, 0, 0, 11 },
  173. Package(){0x0000FFFF, 1, 0, 11 },
  174. Package(){0x0000FFFF, 2, 0, 11 },
  175. Package(){0x0000FFFF, 3, 0, 10 },
  176. })
  177. Name(AR06, Package(){
  178. Package(){0x0000FFFF, 0, 0, 18 },
  179. Package(){0x0000FFFF, 1, 0, 19 },
  180. Package(){0x0000FFFF, 2, 0, 16 },
  181. Package(){0x0000FFFF, 3, 0, 17 },
  182. })
  183. Name(PD07, Package(){
  184. Package(){0x0000FFFF, 0, 0, 11 },
  185. Package(){0x0000FFFF, 1, 0, 11 },
  186. Package(){0x0000FFFF, 2, 0, 10 },
  187. Package(){0x0000FFFF, 3, 0, 11 },
  188. })
  189. Name(AR07, Package(){
  190. Package(){0x0000FFFF, 0, 0, 19 },
  191. Package(){0x0000FFFF, 1, 0, 16 },
  192. Package(){0x0000FFFF, 2, 0, 17 },
  193. Package(){0x0000FFFF, 3, 0, 18 },
  194. })
  195. Name(PD08, Package(){
  196. Package(){0x0000FFFF, 0, 0, 11 },
  197. Package(){0x0000FFFF, 1, 0, 10 },
  198. Package(){0x0000FFFF, 2, 0, 11 },
  199. Package(){0x0000FFFF, 3, 0, 11 },
  200. })
  201. Name(AR08, Package(){
  202. Package(){0x0000FFFF, 0, 0, 16 },
  203. Package(){0x0000FFFF, 1, 0, 17 },
  204. Package(){0x0000FFFF, 2, 0, 18 },
  205. Package(){0x0000FFFF, 3, 0, 19 },
  206. })
  207. Name(PD09, Package(){
  208. Package(){0x0000FFFF, 0, 0, 10 },
  209. Package(){0x0000FFFF, 1, 0, 11 },
  210. Package(){0x0000FFFF, 2, 0, 11 },
  211. Package(){0x0000FFFF, 3, 0, 11 },
  212. })
  213. Name(AR09, Package(){
  214. Package(){0x0000FFFF, 0, 0, 17 },
  215. Package(){0x0000FFFF, 1, 0, 18 },
  216. Package(){0x0000FFFF, 2, 0, 19 },
  217. Package(){0x0000FFFF, 3, 0, 16 },
  218. })
  219. Name(PD0E, Package(){
  220. Package(){0x0000FFFF, 0, 0, 11 },
  221. Package(){0x0000FFFF, 1, 0, 11 },
  222. Package(){0x0000FFFF, 2, 0, 11 },
  223. Package(){0x0000FFFF, 3, 0, 10 },
  224. })
  225. Name(AR0E, Package(){
  226. Package(){0x0000FFFF, 0, 0, 18 },
  227. Package(){0x0000FFFF, 1, 0, 19 },
  228. Package(){0x0000FFFF, 2, 0, 16 },
  229. Package(){0x0000FFFF, 3, 0, 17 },
  230. })
  231. Name(PD0F, Package(){
  232. Package(){0x0000FFFF, 0, 0, 11 },
  233. Package(){0x0000FFFF, 1, 0, 11 },
  234. Package(){0x0000FFFF, 2, 0, 10 },
  235. Package(){0x0000FFFF, 3, 0, 11 },
  236. })
  237. Name(AR0F, Package(){
  238. Package(){0x0000FFFF, 0, 0, 19 },
  239. Package(){0x0000FFFF, 1, 0, 16 },
  240. Package(){0x0000FFFF, 2, 0, 17 },
  241. Package(){0x0000FFFF, 3, 0, 18 },
  242. })
  243. Name(PD02, Package(){
  244. Package(){0x0000FFFF, 0, 0, 11 },
  245. Package(){0x0000FFFF, 1, 0, 10 },
  246. Package(){0x0000FFFF, 2, 0, 11 },
  247. Package(){0x0000FFFF, 3, 0, 11 },
  248. })
  249. Name(AR02, Package(){
  250. // P.E.G. Port Slot x16
  251. Package(){0x0000FFFF, 0, 0, 16 },
  252. Package(){0x0000FFFF, 1, 0, 17 },
  253. Package(){0x0000FFFF, 2, 0, 18 },
  254. Package(){0x0000FFFF, 3, 0, 19 },
  255. })
  256. Name(PD0A, Package(){
  257. // P.E.G. Port Slot x8
  258. Package(){0x0000FFFF, 0, 0, 10 },
  259. Package(){0x0000FFFF, 1, 0, 11 },
  260. Package(){0x0000FFFF, 2, 0, 11 },
  261. Package(){0x0000FFFF, 3, 0, 11 },
  262. })
  263. Name(AR0A, Package(){
  264. // P.E.G. Port Slot x8
  265. Package(){0x0000FFFF, 0, 0, 17 },
  266. Package(){0x0000FFFF, 1, 0, 18 },
  267. Package(){0x0000FFFF, 2, 0, 19 },
  268. Package(){0x0000FFFF, 3, 0, 16 },
  269. })
  270. Name(PD0B, Package(){
  271. // P.E.G. Port Slot x4
  272. Package(){0x0000FFFF, 0, 0, 11 },
  273. Package(){0x0000FFFF, 1, 0, 11 },
  274. Package(){0x0000FFFF, 2, 0, 11 },
  275. Package(){0x0000FFFF, 3, 0, 10 },
  276. })
  277. Name(AR0B, Package(){
  278. // P.E.G. Port Slot x4
  279. Package(){0x0000FFFF, 0, 0, 18 },
  280. Package(){0x0000FFFF, 1, 0, 19 },
  281. Package(){0x0000FFFF, 2, 0, 16 },
  282. Package(){0x0000FFFF, 3, 0, 17 },
  283. })
  284. //---------------------------------------------------------------------------
  285. // Begin PCI tree object scope
  286. //---------------------------------------------------------------------------
  287. Device(PCI0) { // PCI Bridge "Host Bridge"
  288. Name(_HID, EISAID("PNP0A08")) // Indicates PCI Express/PCI-X Mode2 host hierarchy
  289. Name(_CID, EISAID("PNP0A03")) // To support legacy OS that doesn't understand the new HID
  290. Name(_SEG, 0)
  291. Name(_ADR, 0x00000000)
  292. Method(^BN00, 0){ return(0x0000) } // Returns default Bus number for Peer PCI busses. Name can be overriden with control method placed directly under Device scope
  293. Method(_BBN, 0){ return(BN00()) } // Bus number, optional for the Root PCI Bus
  294. Name(_UID, 0x0000) // Unique Bus ID, optional
  295. Method(_PRT,0) {
  296. If(PICM) {Return(AR00)} // APIC mode
  297. Return (PD00) // PIC Mode
  298. } // end _PRT
  299. Include("HostBus.asl")
  300. } // end PCI0 Bridge "Host Bridge"
  301. } // end _SB scope