HostBus.asl 12 KB

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  1. /** @file
  2. This file contains the SystemAgent PCI Configuration space
  3. definition.
  4. It defines various System Agent PCI Configuration Space registers
  5. which will be used to dynamically produce all resources in the Host Bus.
  6. Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
  7. SPDX-License-Identifier: BSD-2-Clause-Patent
  8. **/
  9. //
  10. // Define various System Agent (SA) PCI Configuration Space
  11. // registers which will be used to dynamically produce all
  12. // resources in the Host Bus _CRS.
  13. //
  14. OperationRegion (HBUS, PCI_Config, 0x00, 0x100)
  15. Field (HBUS, DWordAcc, NoLock, Preserve)
  16. {
  17. Offset(0x40), // EPBAR (0:0:0:40)
  18. EPEN, 1, // Enable
  19. , 11,
  20. EPBR, 20, // EPBAR [31:12]
  21. Offset(0x48), // MCHBAR (0:0:0:48)
  22. MHEN, 1, // Enable
  23. , 14,
  24. MHBR, 17, // MCHBAR [31:15]
  25. Offset(0x50), // GGC (0:0:0:50)
  26. GCLK, 1, // GGCLCK
  27. Offset(0x54), // DEVEN (0:0:0:54)
  28. D0EN, 1, // DEV0 Enable
  29. D1F2, 1, // DEV1 FUN2 Enable
  30. D1F1, 1, // DEV1 FUN1 Enable
  31. D1F0, 1, // DEV1 FUN0 Enable
  32. Offset(0x60), // PCIEXBAR (0:0:0:60)
  33. PXEN, 1, // Enable
  34. PXSZ, 2, // PCI Express Size
  35. , 23,
  36. PXBR, 6, // PCI Express BAR [31:26]
  37. Offset(0x68), // DMIBAR (0:0:0:68)
  38. DIEN, 1, // Enable
  39. , 11,
  40. DIBR, 20, // DMIBAR [31:12]
  41. Offset(0x70), // MESEG_BASE (0:0:0:70)
  42. , 20,
  43. MEBR, 12, // MESEG_BASE [31:20]
  44. Offset(0x80), // PAM0 Register (0:0:0:80)
  45. PMLK, 1, // PAM Lock bit.
  46. , 3,
  47. PM0H, 2, // PAM 0, High Nibble
  48. , 2,
  49. Offset(0x81), // PAM1 Register (0:0:0:81)
  50. PM1L, 2, // PAM1, Low Nibble
  51. , 2,
  52. PM1H, 2, // PAM1, High Nibble
  53. , 2,
  54. Offset(0x82), // PAM2 Register (0:0:0:82)
  55. PM2L, 2, // PAM2, Low Nibble
  56. , 2,
  57. PM2H, 2, // PAM2, High Nibble
  58. , 2,
  59. Offset(0x83), // PAM3 Register (0:0:0:83)
  60. PM3L, 2, // PAM3, Low Nibble
  61. , 2,
  62. PM3H, 2, // PAM3, High Nibble
  63. , 2,
  64. Offset(0x84), // PAM4 Register (0:0:0:84)
  65. PM4L, 2, // PAM4, Low Nibble
  66. , 2,
  67. PM4H, 2, // PAM4, High Nibble
  68. , 2,
  69. Offset(0x85), // PAM5 Register (0:0:0:85)
  70. PM5L, 2, // PAM5, Low Nibble
  71. , 2,
  72. PM5H, 2, // PAM5, High Nibble
  73. , 2,
  74. Offset(0x86), // PAM6 Register (0:0:0:86)
  75. PM6L, 2, // PAM6, Low Nibble
  76. , 2,
  77. PM6H, 2, // PAM6, High Nibble
  78. , 2,
  79. Offset(0xA8), // Top of Upper Usable DRAM Register (0:0:0:A8)
  80. , 20,
  81. TUUD, 19, // TOUUD [38:20]
  82. Offset(0xBC), // Top of Lower Usable DRAM Register (0:0:0:BC)
  83. , 20,
  84. TLUD, 12, // TOLUD [31:20]
  85. Offset(0xC8), // ERRSTS register (0:0:0:C8)
  86. , 7,
  87. HTSE, 1 // Host Thermal Sensor Event for SMI/SCI/SERR
  88. }
  89. //
  90. // Define a buffer that will store all the bus, memory, and IO information
  91. // relating to the Host Bus. This buffer will be dynamically altered in
  92. // the _CRS and passed back to the OS.
  93. //
  94. Name(BUF0,ResourceTemplate()
  95. {
  96. //
  97. // Bus Number Allocation: Bus 0 to 0xFF
  98. //
  99. WORDBusNumber(ResourceProducer,MinFixed,MaxFixed,PosDecode,0x00,
  100. 0x0000,0x00FF,0x00,0x0100,,,PB00)
  101. //
  102. // I/O Region Allocation 0 ( 0x0000 - 0x0CF7 )
  103. //
  104. DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,
  105. 0x00,0x0000,0x0CF7,0x00,0x0CF8,,,PI00)
  106. //
  107. // PCI Configuration Registers ( 0x0CF8 - 0x0CFF )
  108. //
  109. Io(Decode16,0x0CF8,0x0CF8,1,0x08)
  110. //
  111. // I/O Region Allocation 1 ( 0x0D00 - 0xFFFF )
  112. //
  113. DWordIo(ResourceProducer,MinFixed,MaxFixed,PosDecode,EntireRange,
  114. 0x00,0x0D00,0xFFFF,0x00,0xF300,,,PI01)
  115. //
  116. // Video Buffer Area ( 0xA0000 - 0xBFFFF )
  117. //
  118. DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
  119. ReadWrite,0x00,0xA0000,0xBFFFF,0x00,0x20000,,,A000)
  120. //
  121. // ISA Add-on BIOS Area ( 0xC0000 - 0xC3FFF )
  122. //
  123. DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
  124. ReadWrite,0x00,0xC0000,0xC3FFF,0x00,0x4000,,,C000)
  125. //
  126. // ISA Add-on BIOS Area ( 0xC4000 - 0xC7FFF )
  127. //
  128. DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
  129. ReadWrite,0x00,0xC4000,0xC7FFF,0x00,0x4000,,,C400)
  130. //
  131. // ISA Add-on BIOS Area ( 0xC8000 - 0xCBFFF )
  132. //
  133. DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
  134. ReadWrite,0x00,0xC8000,0xCBFFF,0x00,0x4000,,,C800)
  135. //
  136. // ISA Add-on BIOS Area ( 0xCC000 - 0xCFFFF )
  137. //
  138. DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
  139. ReadWrite,0x00,0xCC000,0xCFFFF,0x00,0x4000,,,CC00)
  140. //
  141. // ISA Add-on BIOS Area ( 0xD0000 - 0xD3FFF )
  142. //
  143. DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
  144. ReadWrite,0x00,0xD0000,0xD3FFF,0x00,0x4000,,,D000)
  145. //
  146. // ISA Add-on BIOS Area ( 0xD4000 - 0xD7FFF )
  147. //
  148. DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
  149. ReadWrite,0x00,0xD4000,0xD7FFF,0x00,0x4000,,,D400)
  150. //
  151. // ISA Add-on BIOS Area ( 0xD8000 - 0xDBFFF )
  152. //
  153. DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
  154. ReadWrite,0x00,0xD8000,0xDBFFF,0x00,0x4000,,,D800)
  155. //
  156. // ISA Add-on BIOS Area ( 0xDC000 - 0xDFFFF )
  157. //
  158. DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
  159. ReadWrite,0x00,0xDC000,0xDFFFF,0x00,0x4000,,,DC00)
  160. //
  161. // BIOS Extension Area ( 0xE0000 - 0xE3FFF )
  162. //
  163. DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
  164. ReadWrite,0x00,0xE0000,0xE3FFF,0x00,0x4000,,,E000)
  165. //
  166. // BIOS Extension Area ( 0xE4000 - 0xE7FFF )
  167. //
  168. DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
  169. ReadWrite,0x00,0xE4000,0xE7FFF,0x00,0x4000,,,E400)
  170. //
  171. // BIOS Extension Area ( 0xE8000 - 0xEBFFF )
  172. //
  173. DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
  174. ReadWrite,0x00,0xE8000,0xEBFFF,0x00,0x4000,,,E800)
  175. //
  176. // BIOS Extension Area ( 0xEC000 - 0xEFFFF )
  177. //
  178. DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
  179. ReadWrite,0x00,0xEC000,0xEFFFF,0x00,0x4000,,,EC00)
  180. //
  181. // BIOS Area ( 0xF0000 - 0xFFFFF )
  182. //
  183. DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
  184. ReadWrite,0x00,0xF0000,0xFFFFF,0x00,0x10000,,,F000)
  185. // //
  186. // // Memory Hole Region ( 0xF00000 - 0xFFFFFF )
  187. // //
  188. // DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,Cacheable,
  189. // ReadWrite,0x00,0xF00000,0xFFFFFF,0x00,0x100000,,,HOLE)
  190. //
  191. // PCI Memory Region ( TOLUD - 0xDFFFFFFF )
  192. //
  193. DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable,
  194. ReadWrite,0x00,0x00000000,0xDFFFFFFF,0x00,0xE0000000,,,PM01)
  195. //
  196. // PCI Memory Region ( TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE) )
  197. // (This is dummy range for OS compatibility, will patch it in _CRS)
  198. //
  199. QWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable,
  200. ReadWrite,0x00,0x10000,0x1FFFF,0x00,0x10000,,,PM02)
  201. //
  202. // PCH reserved resources ( 0xFC800000 - 0xFE7FFFFF )
  203. //
  204. DWordMemory(ResourceProducer,PosDecode,MinFixed,MaxFixed,NonCacheable,
  205. ReadWrite,0x00,0xFC800000,0xFE7FFFFF,0x00,0x2000000,,,PM03)
  206. })
  207. Name(EP_B, 0) // to store EP BAR
  208. Name(MH_B, 0) // to store MCH BAR
  209. Name(PC_B, 0) // to store PCIe BAR
  210. Name(PC_L, 0) // to store PCIe BAR Length
  211. Name(DM_B, 0) // to store DMI BAR
  212. //
  213. // Get EP BAR
  214. //
  215. Method(GEPB,0,Serialized)
  216. {
  217. if(LEqual(EP_B,0))
  218. {
  219. ShiftLeft(\_SB.PCI0.EPBR,12,EP_B)
  220. }
  221. Return(EP_B)
  222. }
  223. //
  224. // Get MCH BAR
  225. //
  226. Method(GMHB,0,Serialized)
  227. {
  228. if(LEqual(MH_B,0))
  229. {
  230. ShiftLeft(\_SB.PCI0.MHBR,15,MH_B)
  231. }
  232. Return(MH_B)
  233. }
  234. //
  235. // Get PCIe BAR
  236. //
  237. Method(GPCB,0,Serialized)
  238. {
  239. if(LEqual(PC_B,0))
  240. {
  241. ShiftLeft(\_SB.PCI0.PXBR,26,PC_B)
  242. }
  243. Return(PC_B)
  244. }
  245. //
  246. // Get PCIe Length
  247. //
  248. Method(GPCL,0,Serialized)
  249. {
  250. if(LEqual(PC_L,0)) {
  251. ShiftRight(0x10000000, \_SB.PCI0.PXSZ,PC_L)
  252. }
  253. Return(PC_L)
  254. }
  255. //
  256. // Get DMI BAR
  257. //
  258. Method(GDMB,0,Serialized)
  259. {
  260. if(LEqual(DM_B,0))
  261. {
  262. ShiftLeft(\_SB.PCI0.DIBR,12,DM_B)
  263. }
  264. Return(DM_B)
  265. }
  266. Method(_CRS,0,Serialized)
  267. {
  268. //
  269. // Fix up Max Bus Number and Length
  270. //
  271. Store(\_SB.PCI0.GPCL(),Local0)
  272. CreateWordField(BUF0, ^PB00._MAX, PBMX)
  273. Store(Subtract(ShiftRight(Local0,20),2), PBMX)
  274. CreateWordField(BUF0, ^PB00._LEN, PBLN)
  275. Store(Subtract(ShiftRight(Local0,20),1), PBLN)
  276. //
  277. // Fix up all of the Option ROM areas from 0xC0000-0xFFFFF.
  278. //
  279. If(PM1L) // \_SB.PCI0
  280. {
  281. // PAMx != 0. Set length = 0.
  282. CreateDwordField(BUF0, ^C000._LEN,C0LN)
  283. Store(Zero,C0LN)
  284. }
  285. If(LEqual(PM1L,1))
  286. {
  287. CreateBitField(BUF0, ^C000._RW,C0RW)
  288. Store(Zero,C0RW)
  289. }
  290. If(PM1H)
  291. {
  292. CreateDwordField(BUF0, ^C400._LEN,C4LN)
  293. Store(Zero,C4LN)
  294. }
  295. If(LEqual(PM1H,1))
  296. {
  297. CreateBitField(BUF0, ^C400._RW,C4RW)
  298. Store(Zero,C4RW)
  299. }
  300. If(PM2L)
  301. {
  302. CreateDwordField(BUF0, ^C800._LEN,C8LN)
  303. Store(Zero,C8LN)
  304. }
  305. If(LEqual(PM2L,1))
  306. {
  307. CreateBitField(BUF0, ^C800._RW,C8RW)
  308. Store(Zero,C8RW)
  309. }
  310. If(PM2H)
  311. {
  312. CreateDwordField(BUF0, ^CC00._LEN,CCLN)
  313. Store(Zero,CCLN)
  314. }
  315. If(LEqual(PM2H,1))
  316. {
  317. CreateBitField(BUF0, ^CC00._RW,CCRW)
  318. Store(Zero,CCRW)
  319. }
  320. If(PM3L)
  321. {
  322. CreateDwordField(BUF0, ^D000._LEN,D0LN)
  323. Store(Zero,D0LN)
  324. }
  325. If(LEqual(PM3L,1))
  326. {
  327. CreateBitField(BUF0, ^D000._RW,D0RW)
  328. Store(Zero,D0RW)
  329. }
  330. If(PM3H)
  331. {
  332. CreateDwordField(BUF0, ^D400._LEN,D4LN)
  333. Store(Zero,D4LN)
  334. }
  335. If(LEqual(PM3H,1))
  336. {
  337. CreateBitField(BUF0, ^D400._RW,D4RW)
  338. Store(Zero,D4RW)
  339. }
  340. If(PM4L)
  341. {
  342. CreateDwordField(BUF0, ^D800._LEN,D8LN)
  343. Store(Zero,D8LN)
  344. }
  345. If(LEqual(PM4L,1))
  346. {
  347. CreateBitField(BUF0, ^D800._RW,D8RW)
  348. Store(Zero,D8RW)
  349. }
  350. If(PM4H)
  351. {
  352. CreateDwordField(BUF0, ^DC00._LEN,DCLN)
  353. Store(Zero,DCLN)
  354. }
  355. If(LEqual(PM4H,1))
  356. {
  357. CreateBitField(BUF0, ^DC00._RW,DCRW)
  358. Store(Zero,DCRW)
  359. }
  360. If(PM5L)
  361. {
  362. CreateDwordField(BUF0, ^E000._LEN,E0LN)
  363. Store(Zero,E0LN)
  364. }
  365. If(LEqual(PM5L,1))
  366. {
  367. CreateBitField(BUF0, ^E000._RW,E0RW)
  368. Store(Zero,E0RW)
  369. }
  370. If(PM5H)
  371. {
  372. CreateDwordField(BUF0, ^E400._LEN,E4LN)
  373. Store(Zero,E4LN)
  374. }
  375. If(LEqual(PM5H,1))
  376. {
  377. CreateBitField(BUF0, ^E400._RW,E4RW)
  378. Store(Zero,E4RW)
  379. }
  380. If(PM6L)
  381. {
  382. CreateDwordField(BUF0, ^E800._LEN,E8LN)
  383. Store(Zero,E8LN)
  384. }
  385. If(LEqual(PM6L,1))
  386. {
  387. CreateBitField(BUF0, ^E800._RW,E8RW)
  388. Store(Zero,E8RW)
  389. }
  390. If(PM6H)
  391. {
  392. CreateDwordField(BUF0, ^EC00._LEN,ECLN)
  393. Store(Zero,ECLN)
  394. }
  395. If(LEqual(PM6H,1))
  396. {
  397. CreateBitField(BUF0, ^EC00._RW,ECRW)
  398. Store(Zero,ECRW)
  399. }
  400. If(PM0H)
  401. {
  402. CreateDwordField(BUF0, ^F000._LEN,F0LN)
  403. Store(Zero,F0LN)
  404. }
  405. If(LEqual(PM0H,1))
  406. {
  407. CreateBitField(BUF0, ^F000._RW,F0RW)
  408. Store(Zero,F0RW)
  409. }
  410. //
  411. // Create pointers to Memory Sizing values.
  412. //
  413. CreateDwordField(BUF0, ^PM01._MIN,M1MN)
  414. CreateDwordField(BUF0, ^PM01._MAX,M1MX)
  415. CreateDwordField(BUF0, ^PM01._LEN,M1LN)
  416. //
  417. // Set Memory Size Values. TLUD represents bits 31:20 of phyical
  418. // TOM, so shift these bits into the correct position and fix up
  419. // the Memory Region available to PCI.
  420. //
  421. Add (Subtract (FixedPcdGet32(PcdPciReservedMemLimit),FixedPcdGet32(PcdPciReservedMemBase)), 1, M1LN)
  422. Store (FixedPcdGet32(PcdPciReservedMemBase), M1MN)
  423. Store (FixedPcdGet32(PcdPciReservedMemLimit), M1MX)
  424. //
  425. // Create pointers to Memory Sizing values.
  426. // Patch PM02 range basing on memory size and OS type
  427. //
  428. CreateQwordField(BUF0, ^PM02._LEN,MSLN)
  429. //
  430. // Set resource length to 0
  431. //
  432. Store (0, MSLN)
  433. D8XH (0, 0xC5)
  434. D8XH (1, 0xAA)
  435. Return(BUF0)
  436. }