PciRootBridgeIo.c 96 KB

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  1. /**
  2. * Copyright (c) 2014, AppliedMicro Corp. All rights reserved.
  3. * Copyright (c) 2016, Hisilicon Limited. All rights reserved.
  4. * Copyright (c) 2016, Linaro Limited. All rights reserved.
  5. *
  6. * This program and the accompanying materials
  7. * are licensed and made available under the terms and conditions of the BSD License
  8. * which accompanies this distribution. The full text of the license may be found at
  9. * http://opensource.org/licenses/bsd-license.php
  10. *
  11. * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12. * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13. *
  14. **/
  15. #include "PciHostBridge.h"
  16. #include <Library/DevicePathLib.h>
  17. #include <Library/DmaLib.h>
  18. #include <Library/PciExpressLib.h>
  19. #include <Regs/HisiPcieV1RegOffset.h>
  20. typedef struct {
  21. EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR SpaceDesp[TypeMax];
  22. EFI_ACPI_END_TAG_DESCRIPTOR EndDesp;
  23. } RESOURCE_CONFIGURATION;
  24. RESOURCE_CONFIGURATION Configuration = {
  25. {{0x8A, 0x2B, 1, 0, 0, 0, 0, 0, 0, 0},
  26. {0x8A, 0x2B, 0, 0, 0, 32, 0, 0, 0, 0},
  27. {0x8A, 0x2B, 0, 0, 6, 32, 0, 0, 0, 0},
  28. {0x8A, 0x2B, 0, 0, 0, 64, 0, 0, 0, 0},
  29. {0x8A, 0x2B, 0, 0, 6, 64, 0, 0, 0, 0},
  30. {0x8A, 0x2B, 2, 0, 0, 0, 0, 0, 0, 0}},
  31. {0x79, 0}
  32. };
  33. //
  34. // Protocol Member Function Prototypes
  35. //
  36. /**
  37. Polls an address in memory mapped I/O space until an exit condition is met, or
  38. a timeout occurs.
  39. This function provides a standard way to poll a PCI memory location. A PCI memory read
  40. operation is performed at the PCI memory address specified by Address for the width specified
  41. by Width. The result of this PCI memory read operation is stored in Result. This PCI memory
  42. read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result &
  43. Mask) is equal to Value.
  44. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  45. @param[in] Width Signifies the width of the memory operations.
  46. @param[in] Address The base address of the memory operations. The caller is
  47. responsible for aligning Address if required.
  48. @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
  49. are ignored. The bits in the bytes below Width which are zero in
  50. Mask are ignored when polling the memory address.
  51. @param[in] Value The comparison value used for the polling exit criteria.
  52. @param[in] Delay The number of 100 ns units to poll. Note that timer available may
  53. be of poorer granularity.
  54. @param[out] Result Pointer to the last value read from the memory location.
  55. @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
  56. @retval EFI_INVALID_PARAMETER Width is invalid.
  57. @retval EFI_INVALID_PARAMETER Result is NULL.
  58. @retval EFI_TIMEOUT Delay expired before a match occurred.
  59. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  60. **/
  61. EFI_STATUS
  62. EFIAPI
  63. RootBridgeIoPollMem (
  64. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  65. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
  66. IN UINT64 Address,
  67. IN UINT64 Mask,
  68. IN UINT64 Value,
  69. IN UINT64 Delay,
  70. OUT UINT64 *Result
  71. );
  72. /**
  73. Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
  74. satisfied or after a defined duration.
  75. This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is
  76. performed at the PCI I/O address specified by Address for the width specified by Width.
  77. The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is
  78. repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal
  79. to Value.
  80. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  81. @param[in] Width Signifies the width of the I/O operations.
  82. @param[in] Address The base address of the I/O operations. The caller is responsible
  83. for aligning Address if required.
  84. @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
  85. are ignored. The bits in the bytes below Width which are zero in
  86. Mask are ignored when polling the I/O address.
  87. @param[in] Value The comparison value used for the polling exit criteria.
  88. @param[in] Delay The number of 100 ns units to poll. Note that timer available may
  89. be of poorer granularity.
  90. @param[out] Result Pointer to the last value read from the memory location.
  91. @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
  92. @retval EFI_INVALID_PARAMETER Width is invalid.
  93. @retval EFI_INVALID_PARAMETER Result is NULL.
  94. @retval EFI_TIMEOUT Delay expired before a match occurred.
  95. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  96. **/
  97. EFI_STATUS
  98. EFIAPI
  99. RootBridgeIoPollIo (
  100. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  101. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
  102. IN UINT64 Address,
  103. IN UINT64 Mask,
  104. IN UINT64 Value,
  105. IN UINT64 Delay,
  106. OUT UINT64 *Result
  107. );
  108. /**
  109. Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
  110. The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
  111. registers in the PCI root bridge memory space.
  112. The memory operations are carried out exactly as requested. The caller is responsible for satisfying
  113. any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
  114. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  115. @param[in] Width Signifies the width of the memory operation.
  116. @param[in] Address The base address of the memory operation. The caller is
  117. responsible for aligning the Address if required.
  118. @param[in] Count The number of memory operations to perform. Bytes moved is
  119. Width size * Count, starting at Address.
  120. @param[out] Buffer For read operations, the destination buffer to store the results. For
  121. write operations, the source buffer to write data from.
  122. @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
  123. @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
  124. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  125. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  126. **/
  127. EFI_STATUS
  128. EFIAPI
  129. RootBridgeIoMemRead (
  130. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  131. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
  132. IN UINT64 Address,
  133. IN UINTN Count,
  134. OUT VOID *Buffer
  135. );
  136. /**
  137. Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
  138. The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
  139. registers in the PCI root bridge memory space.
  140. The memory operations are carried out exactly as requested. The caller is responsible for satisfying
  141. any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
  142. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  143. @param[in] Width Signifies the width of the memory operation.
  144. @param[in] Address The base address of the memory operation. The caller is
  145. responsible for aligning the Address if required.
  146. @param[in] Count The number of memory operations to perform. Bytes moved is
  147. Width size * Count, starting at Address.
  148. @param[in] Buffer For read operations, the destination buffer to store the results. For
  149. write operations, the source buffer to write data from.
  150. @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
  151. @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
  152. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  153. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  154. **/
  155. EFI_STATUS
  156. EFIAPI
  157. RootBridgeIoMemWrite (
  158. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  159. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
  160. IN UINT64 Address,
  161. IN UINTN Count,
  162. IN VOID *Buffer
  163. );
  164. /**
  165. Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
  166. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  167. @param[in] Width Signifies the width of the memory operations.
  168. @param[in] UserAddress The base address of the I/O operation. The caller is responsible for
  169. aligning the Address if required.
  170. @param[in] Count The number of I/O operations to perform. Bytes moved is Width
  171. size * Count, starting at Address.
  172. @param[out] UserBuffer For read operations, the destination buffer to store the results. For
  173. write operations, the source buffer to write data from.
  174. @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
  175. @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
  176. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  177. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  178. **/
  179. EFI_STATUS
  180. EFIAPI
  181. RootBridgeIoIoRead (
  182. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  183. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
  184. IN UINT64 UserAddress,
  185. IN UINTN Count,
  186. OUT VOID *UserBuffer
  187. );
  188. /**
  189. Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
  190. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  191. @param[in] Width Signifies the width of the memory operations.
  192. @param[in] UserAddress The base address of the I/O operation. The caller is responsible for
  193. aligning the Address if required.
  194. @param[in] Count The number of I/O operations to perform. Bytes moved is Width
  195. size * Count, starting at Address.
  196. @param[in] UserBuffer For read operations, the destination buffer to store the results. For
  197. write operations, the source buffer to write data from.
  198. @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
  199. @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
  200. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  201. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  202. **/
  203. EFI_STATUS
  204. EFIAPI
  205. RootBridgeIoIoWrite (
  206. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  207. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
  208. IN UINT64 UserAddress,
  209. IN UINTN Count,
  210. IN VOID *UserBuffer
  211. );
  212. /**
  213. Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI
  214. root bridge memory space.
  215. The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory
  216. space to another region of PCI root bridge memory space. This is especially useful for video scroll
  217. operation on a memory mapped video buffer.
  218. The memory operations are carried out exactly as requested. The caller is responsible for satisfying
  219. any alignment and memory width restrictions that a PCI root bridge on a platform might require.
  220. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.
  221. @param[in] Width Signifies the width of the memory operations.
  222. @param[in] DestAddress The destination address of the memory operation. The caller is
  223. responsible for aligning the DestAddress if required.
  224. @param[in] SrcAddress The source address of the memory operation. The caller is
  225. responsible for aligning the SrcAddress if required.
  226. @param[in] Count The number of memory operations to perform. Bytes moved is
  227. Width size * Count, starting at DestAddress and SrcAddress.
  228. @retval EFI_SUCCESS The data was copied from one memory region to another memory region.
  229. @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
  230. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  231. **/
  232. EFI_STATUS
  233. EFIAPI
  234. RootBridgeIoCopyMem (
  235. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  236. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
  237. IN UINT64 DestAddress,
  238. IN UINT64 SrcAddress,
  239. IN UINTN Count
  240. );
  241. /**
  242. Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
  243. The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
  244. registers for a PCI controller.
  245. The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
  246. any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
  247. require.
  248. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  249. @param[in] Width Signifies the width of the memory operations.
  250. @param[in] Address The address within the PCI configuration space for the PCI controller.
  251. @param[in] Count The number of PCI configuration operations to perform. Bytes
  252. moved is Width size * Count, starting at Address.
  253. @param[out] Buffer For read operations, the destination buffer to store the results. For
  254. write operations, the source buffer to write data from.
  255. @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
  256. @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
  257. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  258. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  259. **/
  260. EFI_STATUS
  261. EFIAPI
  262. RootBridgeIoPciRead (
  263. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  264. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
  265. IN UINT64 Address,
  266. IN UINTN Count,
  267. OUT VOID *Buffer
  268. );
  269. /**
  270. Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
  271. The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
  272. registers for a PCI controller.
  273. The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
  274. any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
  275. require.
  276. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  277. @param[in] Width Signifies the width of the memory operations.
  278. @param[in] Address The address within the PCI configuration space for the PCI controller.
  279. @param[in] Count The number of PCI configuration operations to perform. Bytes
  280. moved is Width size * Count, starting at Address.
  281. @param[in] Buffer For read operations, the destination buffer to store the results. For
  282. write operations, the source buffer to write data from.
  283. @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
  284. @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
  285. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  286. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  287. **/
  288. EFI_STATUS
  289. EFIAPI
  290. RootBridgeIoPciWrite (
  291. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  292. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
  293. IN UINT64 Address,
  294. IN UINTN Count,
  295. IN VOID *Buffer
  296. );
  297. /**
  298. Provides the PCI controller-specific addresses required to access system memory from a
  299. DMA bus master.
  300. The Map() function provides the PCI controller specific addresses needed to access system
  301. memory. This function is used to map system memory for PCI bus master DMA accesses.
  302. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  303. @param[in] Operation Indicates if the bus master is going to read or write to system memory.
  304. @param[in] HostAddress The system memory address to map to the PCI controller.
  305. @param[in, out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.
  306. @param[out] DeviceAddress The resulting map address for the bus master PCI controller to use
  307. to access the system memory's HostAddress.
  308. @param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete.
  309. @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
  310. @retval EFI_INVALID_PARAMETER Operation is invalid.
  311. @retval EFI_INVALID_PARAMETER HostAddress is NULL.
  312. @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL.
  313. @retval EFI_INVALID_PARAMETER DeviceAddress is NULL.
  314. @retval EFI_INVALID_PARAMETER Mapping is NULL.
  315. @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
  316. @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
  317. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  318. **/
  319. EFI_STATUS
  320. EFIAPI
  321. RootBridgeIoMap (
  322. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  323. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,
  324. IN VOID *HostAddress,
  325. IN OUT UINTN *NumberOfBytes,
  326. OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
  327. OUT VOID **Mapping
  328. );
  329. /**
  330. Completes the Map() operation and releases any corresponding resources.
  331. The Unmap() function completes the Map() operation and releases any corresponding resources.
  332. If the operation was an EfiPciOperationBusMasterWrite or
  333. EfiPciOperationBusMasterWrite64, the data is committed to the target system memory.
  334. Any resources used for the mapping are freed.
  335. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  336. @param[in] Mapping The mapping value returned from Map().
  337. @retval EFI_SUCCESS The range was unmapped.
  338. @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
  339. @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
  340. **/
  341. EFI_STATUS
  342. EFIAPI
  343. RootBridgeIoUnmap (
  344. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  345. IN VOID *Mapping
  346. );
  347. /**
  348. Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or
  349. EfiPciOperationBusMasterCommonBuffer64 mapping.
  350. @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  351. @param Type This parameter is not used and must be ignored.
  352. @param MemoryType The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.
  353. @param Pages The number of pages to allocate.
  354. @param HostAddress A pointer to store the base system memory address of the allocated range.
  355. @param Attributes The requested bit mask of attributes for the allocated range. Only
  356. the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED,
  357. and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.
  358. @retval EFI_SUCCESS The requested memory pages were allocated.
  359. @retval EFI_INVALID_PARAMETER MemoryType is invalid.
  360. @retval EFI_INVALID_PARAMETER HostAddress is NULL.
  361. @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
  362. MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
  363. @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
  364. **/
  365. EFI_STATUS
  366. EFIAPI
  367. RootBridgeIoAllocateBuffer (
  368. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  369. IN EFI_ALLOCATE_TYPE Type,
  370. IN EFI_MEMORY_TYPE MemoryType,
  371. IN UINTN Pages,
  372. OUT VOID **HostAddress,
  373. IN UINT64 Attributes
  374. );
  375. /**
  376. Frees memory that was allocated with AllocateBuffer().
  377. The FreeBuffer() function frees memory that was allocated with AllocateBuffer().
  378. @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  379. @param Pages The number of pages to free.
  380. @param HostAddress The base system memory address of the allocated range.
  381. @retval EFI_SUCCESS The requested memory pages were freed.
  382. @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
  383. was not allocated with AllocateBuffer().
  384. **/
  385. EFI_STATUS
  386. EFIAPI
  387. RootBridgeIoFreeBuffer (
  388. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  389. IN UINTN Pages,
  390. OUT VOID *HostAddress
  391. );
  392. /**
  393. Flushes all PCI posted write transactions from a PCI host bridge to system memory.
  394. The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system
  395. memory. Posted write transactions are generated by PCI bus masters when they perform write
  396. transactions to target addresses in system memory.
  397. This function does not flush posted write transactions from any PCI bridges. A PCI controller
  398. specific action must be taken to guarantee that the posted write transactions have been flushed from
  399. the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with
  400. a PCI read transaction from the PCI controller prior to calling Flush().
  401. @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  402. @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host
  403. bridge to system memory.
  404. @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI
  405. host bridge due to a hardware error.
  406. **/
  407. EFI_STATUS
  408. EFIAPI
  409. RootBridgeIoFlush (
  410. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This
  411. );
  412. /**
  413. Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the
  414. attributes that a PCI root bridge is currently using.
  415. The GetAttributes() function returns the mask of attributes that this PCI root bridge supports
  416. and the mask of attributes that the PCI root bridge is currently using.
  417. @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  418. @param Supported A pointer to the mask of attributes that this PCI root bridge
  419. supports setting with SetAttributes().
  420. @param Attributes A pointer to the mask of attributes that this PCI root bridge is
  421. currently using.
  422. @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root
  423. bridge supports is returned in Supports. If Attributes is
  424. not NULL, then the attributes that the PCI root bridge is currently
  425. using is returned in Attributes.
  426. @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
  427. **/
  428. EFI_STATUS
  429. EFIAPI
  430. RootBridgeIoGetAttributes (
  431. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  432. OUT UINT64 *Supported,
  433. OUT UINT64 *Attributes
  434. );
  435. /**
  436. Sets attributes for a resource range on a PCI root bridge.
  437. The SetAttributes() function sets the attributes specified in Attributes for the PCI root
  438. bridge on the resource range specified by ResourceBase and ResourceLength. Since the
  439. granularity of setting these attributes may vary from resource type to resource type, and from
  440. platform to platform, the actual resource range and the one passed in by the caller may differ. As a
  441. result, this function may set the attributes specified by Attributes on a larger resource range
  442. than the caller requested. The actual range is returned in ResourceBase and
  443. ResourceLength. The caller is responsible for verifying that the actual range for which the
  444. attributes were set is acceptable.
  445. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  446. @param[in] Attributes The mask of attributes to set. If the attribute bit
  447. MEMORY_WRITE_COMBINE, MEMORY_CACHED, or
  448. MEMORY_DISABLE is set, then the resource range is specified by
  449. ResourceBase and ResourceLength. If
  450. MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
  451. MEMORY_DISABLE are not set, then ResourceBase and
  452. ResourceLength are ignored, and may be NULL.
  453. @param[in, out] ResourceBase A pointer to the base address of the resource range to be modified
  454. by the attributes specified by Attributes.
  455. @param[in, out] ResourceLength A pointer to the length of the resource range to be modified by the
  456. attributes specified by Attributes.
  457. @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
  458. @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
  459. @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
  460. **/
  461. EFI_STATUS
  462. EFIAPI
  463. RootBridgeIoSetAttributes (
  464. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  465. IN UINT64 Attributes,
  466. IN OUT UINT64 *ResourceBase,
  467. IN OUT UINT64 *ResourceLength
  468. );
  469. /**
  470. Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0
  471. resource descriptors.
  472. There are only two resource descriptor types from the ACPI Specification that may be used to
  473. describe the current resources allocated to a PCI root bridge. These are the QWORD Address
  474. Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The
  475. QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic
  476. or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD
  477. Address Space Descriptors followed by an End Tag.
  478. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  479. @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that describe the
  480. current configuration of this PCI root bridge. The storage for the
  481. ACPI 2.0 resource descriptors is allocated by this function. The
  482. caller must treat the return buffer as read-only data, and the buffer
  483. must not be freed by the caller.
  484. @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
  485. @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
  486. @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
  487. **/
  488. EFI_STATUS
  489. EFIAPI
  490. RootBridgeIoConfiguration (
  491. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  492. OUT VOID **Resources
  493. );
  494. //
  495. // Memory Controller Pci Root Bridge Io Module Variables
  496. //
  497. EFI_METRONOME_ARCH_PROTOCOL *mMetronome;
  498. //
  499. // Lookup table for increment values based on transfer widths
  500. //
  501. UINT8 mInStride[] = {
  502. 1, // EfiPciWidthUint8
  503. 2, // EfiPciWidthUint16
  504. 4, // EfiPciWidthUint32
  505. 8, // EfiPciWidthUint64
  506. 0, // EfiPciWidthFifoUint8
  507. 0, // EfiPciWidthFifoUint16
  508. 0, // EfiPciWidthFifoUint32
  509. 0, // EfiPciWidthFifoUint64
  510. 1, // EfiPciWidthFillUint8
  511. 2, // EfiPciWidthFillUint16
  512. 4, // EfiPciWidthFillUint32
  513. 8 // EfiPciWidthFillUint64
  514. };
  515. //
  516. // Lookup table for increment values based on transfer widths
  517. //
  518. UINT8 mOutStride[] = {
  519. 1, // EfiPciWidthUint8
  520. 2, // EfiPciWidthUint16
  521. 4, // EfiPciWidthUint32
  522. 8, // EfiPciWidthUint64
  523. 1, // EfiPciWidthFifoUint8
  524. 2, // EfiPciWidthFifoUint16
  525. 4, // EfiPciWidthFifoUint32
  526. 8, // EfiPciWidthFifoUint64
  527. 0, // EfiPciWidthFillUint8
  528. 0, // EfiPciWidthFillUint16
  529. 0, // EfiPciWidthFillUint32
  530. 0 // EfiPciWidthFillUint64
  531. };
  532. UINT64 GetPcieCfgAddress (
  533. UINT64 Ecam,
  534. UINTN Bus,
  535. UINTN Device,
  536. UINTN Function,
  537. UINTN Reg
  538. )
  539. {
  540. return Ecam + PCI_EXPRESS_LIB_ADDRESS (Bus, Device, Function, Reg);
  541. }
  542. void SetAtuConfig0RW (
  543. PCI_ROOT_BRIDGE_INSTANCE *Private,
  544. UINT32 Index
  545. )
  546. {
  547. UINTN RbPciBase = Private->RbPciBar;
  548. UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 1, 1, 0, 0) - 1;
  549. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
  550. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam));
  551. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32));
  552. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
  553. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
  554. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
  555. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG0);
  556. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE);
  557. {
  558. UINTN i;
  559. for (i=0; i<0x20; i+=4) {
  560. DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
  561. }
  562. }
  563. }
  564. void SetAtuConfig1RW (
  565. PCI_ROOT_BRIDGE_INSTANCE *Private,
  566. UINT32 Index
  567. )
  568. {
  569. UINTN RbPciBase = Private->RbPciBar;
  570. UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1;
  571. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
  572. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1);
  573. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam));
  574. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32));
  575. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
  576. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
  577. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
  578. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE);
  579. {
  580. UINTN i;
  581. for (i=0; i<0x20; i+=4) {
  582. DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
  583. }
  584. }
  585. }
  586. void SetAtuIoRW(UINT64 RbPciBase,UINT64 IoBase,UINT64 CpuIoRegionLimit, UINT64 CpuIoRegionBase, UINT32 Index)
  587. {
  588. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
  589. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_IO);
  590. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(CpuIoRegionBase));
  591. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)CpuIoRegionBase >> 32));
  592. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)(CpuIoRegionLimit));
  593. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(IoBase));
  594. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(IoBase) >> 32));
  595. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_MODE);
  596. {
  597. UINTN i;
  598. for (i=0; i<0x20; i+=4) {
  599. DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
  600. }
  601. }
  602. }
  603. void SetAtuMemRW(UINT64 RbPciBase,UINT64 MemBase,UINT64 CpuMemRegionLimit, UINT64 CpuMemRegionBase, UINT32 Index)
  604. {
  605. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
  606. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_MEM);
  607. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(CpuMemRegionBase));
  608. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(CpuMemRegionBase) >> 32));
  609. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)(CpuMemRegionLimit));
  610. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(MemBase));
  611. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(MemBase) >> 32));
  612. MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_MODE);
  613. {
  614. UINTN i;
  615. for (i=0; i<0x20; i+=4) {
  616. DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
  617. }
  618. }
  619. }
  620. VOID InitAtu (PCI_ROOT_BRIDGE_INSTANCE *Private)
  621. {
  622. SetAtuMemRW (Private->RbPciBar, Private->PciRegionBase, Private->PciRegionLimit, Private->CpuMemRegionBase, 0);
  623. SetAtuConfig0RW (Private, 1);
  624. SetAtuConfig1RW (Private, 2);
  625. SetAtuIoRW (Private->RbPciBar, Private->IoBase, Private->IoLimit, Private->CpuIoRegionBase, 3);
  626. }
  627. BOOLEAN PcieIsLinkUp (UINT32 SocType, UINTN RbPciBar, UINTN Port)
  628. {
  629. UINT32 Value = 0;
  630. if (0x1610 == SocType)
  631. {
  632. Value = MmioRead32(RbPciBar + 0x131C);
  633. if ((Value & 0x3F) == 0x11)
  634. {
  635. return TRUE;
  636. }
  637. return FALSE;
  638. }
  639. else
  640. {
  641. Value = MmioRead32 (0xb0000000 + 0x6818 + 0x100 * Port);
  642. if ((Value & 0x3F) == 0x11)
  643. {
  644. return TRUE;
  645. }
  646. return FALSE;
  647. }
  648. }
  649. /**
  650. Construct the Pci Root Bridge Io protocol
  651. @param Protocol Point to protocol instance
  652. @param HostBridgeHandle Handle of host bridge
  653. @param Attri Attribute of host bridge
  654. @param ResAppeture ResourceAppeture for host bridge
  655. @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.
  656. **/
  657. EFI_STATUS
  658. RootBridgeConstructor (
  659. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,
  660. IN EFI_HANDLE HostBridgeHandle,
  661. IN UINT64 Attri,
  662. IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE *ResAppeture,
  663. IN UINT32 Seg
  664. )
  665. {
  666. EFI_STATUS Status;
  667. PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
  668. PCI_RESOURCE_TYPE Index;
  669. PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (Protocol);
  670. //
  671. // The host to pci bridge, the host memory and io addresses are
  672. // direct mapped to pci addresses, so no need translate, set bases to 0.
  673. //
  674. PrivateData->MemBase = ResAppeture->MemBase;
  675. PrivateData->IoBase = ResAppeture->IoBase;
  676. PrivateData->RbPciBar = ResAppeture->RbPciBar;
  677. PrivateData->MemLimit = ResAppeture->MemLimit;
  678. PrivateData->IoLimit = ResAppeture->IoLimit;
  679. PrivateData->Ecam = ResAppeture->Ecam;
  680. PrivateData->CpuMemRegionBase = ResAppeture->CpuMemRegionBase;
  681. PrivateData->CpuIoRegionBase = ResAppeture->CpuIoRegionBase;
  682. PrivateData->PciRegionBase = ResAppeture->PciRegionBase;
  683. PrivateData->PciRegionLimit = ResAppeture->PciRegionLimit;
  684. //
  685. // Bus Appeture for this Root Bridge (Possible Range)
  686. //
  687. PrivateData->BusBase = ResAppeture->BusBase;
  688. PrivateData->BusLimit = ResAppeture->BusLimit;
  689. //
  690. // Specific for this chipset
  691. //
  692. for (Index = TypeIo; Index < TypeMax; Index++) {
  693. PrivateData->ResAllocNode[Index].Type = Index;
  694. PrivateData->ResAllocNode[Index].Base = 0;
  695. PrivateData->ResAllocNode[Index].Length = 0;
  696. PrivateData->ResAllocNode[Index].Status = ResNone;
  697. }
  698. PrivateData->RootBridgeAttrib = Attri;
  699. PrivateData->Supports = EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | \
  700. EFI_PCI_ATTRIBUTE_ISA_IO_16 | EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \
  701. EFI_PCI_ATTRIBUTE_VGA_MEMORY | \
  702. EFI_PCI_ATTRIBUTE_VGA_IO_16 | EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16 | \
  703. EFI_PCI_ATTRIBUTE_VALID_FOR_ALLOCATE_BUFFER;
  704. PrivateData->Attributes = PrivateData->Supports;
  705. Protocol->ParentHandle = HostBridgeHandle;
  706. Protocol->PollMem = RootBridgeIoPollMem;
  707. Protocol->PollIo = RootBridgeIoPollIo;
  708. Protocol->Mem.Read = RootBridgeIoMemRead;
  709. Protocol->Mem.Write = RootBridgeIoMemWrite;
  710. Protocol->Io.Read = RootBridgeIoIoRead;
  711. Protocol->Io.Write = RootBridgeIoIoWrite;
  712. Protocol->CopyMem = RootBridgeIoCopyMem;
  713. Protocol->Pci.Read = RootBridgeIoPciRead;
  714. Protocol->Pci.Write = RootBridgeIoPciWrite;
  715. Protocol->Map = RootBridgeIoMap;
  716. Protocol->Unmap = RootBridgeIoUnmap;
  717. Protocol->AllocateBuffer = RootBridgeIoAllocateBuffer;
  718. Protocol->FreeBuffer = RootBridgeIoFreeBuffer;
  719. Protocol->Flush = RootBridgeIoFlush;
  720. Protocol->GetAttributes = RootBridgeIoGetAttributes;
  721. Protocol->SetAttributes = RootBridgeIoSetAttributes;
  722. Protocol->Configuration = RootBridgeIoConfiguration;
  723. Protocol->SegmentNumber = Seg;
  724. InitAtu (PrivateData);
  725. Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **)&mMetronome);
  726. if (EFI_ERROR(Status))
  727. {
  728. DEBUG((EFI_D_ERROR,"LocateProtocol MetronomeArchProtocol Error\n"));
  729. }
  730. return EFI_SUCCESS;
  731. }
  732. /**
  733. Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge IO.
  734. The I/O operations are carried out exactly as requested. The caller is responsible
  735. for satisfying any alignment and I/O width restrictions that a PI System on a
  736. platform might require. For example on some platforms, width requests of
  737. EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the other hand, will
  738. be handled by the driver.
  739. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  740. @param[in] OperationType I/O operation type: IO/MMIO/PCI.
  741. @param[in] Width Signifies the width of the I/O or Memory operation.
  742. @param[in] Address The base address of the I/O operation.
  743. @param[in] Count The number of I/O operations to perform. The number of
  744. bytes moved is Width size * Count, starting at Address.
  745. @param[in] Buffer For read operations, the destination buffer to store the results.
  746. For write operations, the source buffer from which to write data.
  747. @retval EFI_SUCCESS The parameters for this request pass the checks.
  748. @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
  749. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  750. @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
  751. @retval EFI_UNSUPPORTED The address range specified by Address, Width,
  752. and Count is not valid for this PI system.
  753. **/
  754. EFI_STATUS
  755. RootBridgeIoCheckParameter (
  756. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  757. IN OPERATION_TYPE OperationType,
  758. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
  759. IN UINT64 Address,
  760. IN UINTN Count,
  761. IN VOID *Buffer
  762. )
  763. {
  764. PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
  765. EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr;
  766. UINT64 MaxCount;
  767. UINT64 Base;
  768. UINT64 Limit;
  769. //
  770. // Check to see if Buffer is NULL
  771. //
  772. if (Buffer == NULL) {
  773. return EFI_INVALID_PARAMETER;
  774. }
  775. //
  776. // Check to see if Width is in the valid range
  777. //
  778. if ((UINT32)Width >= EfiPciWidthMaximum) {
  779. return EFI_INVALID_PARAMETER;
  780. }
  781. //
  782. // For FIFO type, the target address won't increase during the access,
  783. // so treat Count as 1
  784. //
  785. if (Width >= EfiPciWidthFifoUint8 && Width <= EfiPciWidthFifoUint64) {
  786. Count = 1;
  787. }
  788. //
  789. // Check to see if Width is in the valid range for I/O Port operations
  790. //
  791. Width = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
  792. if ((OperationType != MemOperation) && (Width == EfiPciWidthUint64)) {
  793. ASSERT (FALSE);
  794. return EFI_INVALID_PARAMETER;
  795. }
  796. //
  797. // Check to see if Address is aligned
  798. //
  799. if ((Address & (UINT64)(mInStride[Width] - 1)) != 0) {
  800. return EFI_UNSUPPORTED;
  801. }
  802. PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
  803. //
  804. // Check to see if any address associated with this transfer exceeds the maximum
  805. // allowed address. The maximum address implied by the parameters passed in is
  806. // Address + Size * Count. If the following condition is met, then the transfer
  807. // is not supported.
  808. //
  809. // Address + Size * Count > Limit + 1
  810. //
  811. // Since Limit can be the maximum integer value supported by the CPU and Count
  812. // can also be the maximum integer value supported by the CPU, this range
  813. // check must be adjusted to avoid all oveflow conditions.
  814. //
  815. // The following form of the range check is equivalent but assumes that
  816. // Limit is of the form (2^n - 1).
  817. //
  818. if (OperationType == IoOperation) {
  819. Base = PrivateData->IoBase;
  820. Limit = PrivateData->IoLimit;
  821. } else if (OperationType == MemOperation) {
  822. Base = PrivateData->MemBase;
  823. Limit = PrivateData->MemLimit;
  824. } else {
  825. PciRbAddr = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS*) &Address;
  826. if (PciRbAddr->Bus < PrivateData->BusBase || PciRbAddr->Bus > PrivateData->BusLimit) {
  827. return EFI_INVALID_PARAMETER;
  828. }
  829. /* The root complex has only one device / function */
  830. if (PciRbAddr->Bus == PrivateData->BusBase && PciRbAddr->Device != 0) {
  831. return EFI_INVALID_PARAMETER;
  832. }
  833. /* The other side of the RC has only one device as well */
  834. if (PciRbAddr->Bus == (PrivateData->BusBase + 1 ) && PciRbAddr->Device != 0) {
  835. return EFI_INVALID_PARAMETER;
  836. }
  837. if (PciRbAddr->Device > MAX_PCI_DEVICE_NUMBER || PciRbAddr->Function > MAX_PCI_FUNCTION_NUMBER) {
  838. return EFI_INVALID_PARAMETER;
  839. }
  840. if (PciRbAddr->ExtendedRegister != 0) {
  841. Address = PciRbAddr->ExtendedRegister;
  842. } else {
  843. Address = PciRbAddr->Register;
  844. }
  845. Base = 0;
  846. Limit = MAX_PCI_REG_ADDRESS;
  847. }
  848. if (Address < Base) {
  849. return EFI_INVALID_PARAMETER;
  850. }
  851. if (Count == 0) {
  852. if (Address > Limit) {
  853. return EFI_UNSUPPORTED;
  854. }
  855. } else {
  856. MaxCount = RShiftU64 (Limit, Width);
  857. if (MaxCount < (Count - 1)) {
  858. return EFI_UNSUPPORTED;
  859. }
  860. if (Address > LShiftU64 (MaxCount - Count + 1, Width)) {
  861. return EFI_UNSUPPORTED;
  862. }
  863. }
  864. return EFI_SUCCESS;
  865. }
  866. /**
  867. Internal help function for read and write memory space.
  868. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  869. @param[in] Write Switch value for Read or Write.
  870. @param[in] Width Signifies the width of the memory operations.
  871. @param[in] UserAddress The address within the PCI configuration space for the PCI controller.
  872. @param[in] Count The number of PCI configuration operations to perform. Bytes
  873. moved is Width size * Count, starting at Address.
  874. @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For
  875. write operations, the source buffer to write data from.
  876. @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
  877. @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
  878. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  879. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  880. **/
  881. EFI_STATUS
  882. RootBridgeIoMemRW (
  883. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  884. IN BOOLEAN Write,
  885. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
  886. IN UINT64 Address,
  887. IN UINTN Count,
  888. IN OUT VOID *Buffer
  889. )
  890. {
  891. EFI_STATUS Status;
  892. UINT8 InStride;
  893. UINT8 OutStride;
  894. EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;
  895. UINT8 *Uint8Buffer;
  896. PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
  897. PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
  898. /* Address is bus resource */
  899. Address -= PrivateData->PciRegionBase;
  900. Address += PrivateData->CpuMemRegionBase;
  901. PCIE_DEBUG("RootBridgeIoMemRW Address:0x%llx\n", Address);
  902. PCIE_DEBUG("RootBridgeIoMemRW Count:0x%llx\n", Count);
  903. PCIE_DEBUG("RootBridgeIoMemRW Write:0x%llx\n", Write);
  904. PCIE_DEBUG("RootBridgeIoMemRW Width:0x%llx\n", Width);
  905. Status = RootBridgeIoCheckParameter (This, MemOperation, Width, Address, Count, Buffer);
  906. if (EFI_ERROR (Status)) {
  907. return Status;
  908. }
  909. InStride = mInStride[Width];
  910. OutStride = mOutStride[Width];
  911. OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
  912. for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
  913. if (Write) {
  914. switch (OperationWidth) {
  915. case EfiPciWidthUint8:
  916. MmioWrite8 ((UINTN)Address, *Uint8Buffer);
  917. break;
  918. case EfiPciWidthUint16:
  919. MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
  920. break;
  921. case EfiPciWidthUint32:
  922. MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
  923. break;
  924. case EfiPciWidthUint64:
  925. MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
  926. break;
  927. default:
  928. //
  929. // The RootBridgeIoCheckParameter call above will ensure that this
  930. // path is not taken.
  931. //
  932. ASSERT (FALSE);
  933. break;
  934. }
  935. } else {
  936. switch (OperationWidth) {
  937. case EfiPciWidthUint8:
  938. *Uint8Buffer = MmioRead8 ((UINTN)Address);
  939. break;
  940. case EfiPciWidthUint16:
  941. *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
  942. break;
  943. case EfiPciWidthUint32:
  944. *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
  945. break;
  946. case EfiPciWidthUint64:
  947. *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
  948. break;
  949. default:
  950. //
  951. // The RootBridgeIoCheckParameter call above will ensure that this
  952. // path is not taken.
  953. //
  954. ASSERT (FALSE);
  955. break;
  956. }
  957. }
  958. }
  959. return EFI_SUCCESS;
  960. }
  961. /**
  962. Internal help function for read and write IO space.
  963. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  964. @param[in] Write Switch value for Read or Write.
  965. @param[in] Width Signifies the width of the memory operations.
  966. @param[in] UserAddress The address within the PCI configuration space for the PCI controller.
  967. @param[in] Count The number of PCI configuration operations to perform. Bytes
  968. moved is Width size * Count, starting at Address.
  969. @param[in, out] UserBuffer For read operations, the destination buffer to store the results. For
  970. write operations, the source buffer to write data from.
  971. @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
  972. @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
  973. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  974. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  975. **/
  976. EFI_STATUS
  977. RootBridgeIoIoRW (
  978. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  979. IN BOOLEAN Write,
  980. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
  981. IN UINT64 Address,
  982. IN UINTN Count,
  983. IN OUT VOID *Buffer
  984. )
  985. {
  986. EFI_STATUS Status;
  987. UINT8 InStride;
  988. UINT8 OutStride;
  989. EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth;
  990. UINT8 *Uint8Buffer;
  991. PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
  992. PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
  993. /* Address is bus resource */
  994. Address -= PrivateData->IoBase;
  995. Address += PrivateData->CpuIoRegionBase;
  996. Status = RootBridgeIoCheckParameter (This, IoOperation, Width, Address, Count, Buffer);
  997. if (EFI_ERROR (Status)) {
  998. return Status;
  999. }
  1000. InStride = mInStride[Width];
  1001. OutStride = mOutStride[Width];
  1002. OperationWidth = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) (Width & 0x03);
  1003. for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
  1004. if (Write) {
  1005. switch (OperationWidth) {
  1006. case EfiPciWidthUint8:
  1007. MmioWrite8 ((UINTN)Address, *Uint8Buffer);
  1008. break;
  1009. case EfiPciWidthUint16:
  1010. MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer));
  1011. break;
  1012. case EfiPciWidthUint32:
  1013. MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
  1014. break;
  1015. case EfiPciWidthUint64:
  1016. MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
  1017. break;
  1018. default:
  1019. //
  1020. // The RootBridgeIoCheckParameter call above will ensure that this
  1021. // path is not taken.
  1022. //
  1023. ASSERT (FALSE);
  1024. break;
  1025. }
  1026. } else {
  1027. switch (OperationWidth) {
  1028. case EfiPciWidthUint8:
  1029. *Uint8Buffer = MmioRead8 ((UINTN)Address);
  1030. break;
  1031. case EfiPciWidthUint16:
  1032. *((UINT16 *)Uint8Buffer) = MmioRead16 ((UINTN)Address);
  1033. break;
  1034. case EfiPciWidthUint32:
  1035. *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
  1036. break;
  1037. case EfiPciWidthUint64:
  1038. *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
  1039. break;
  1040. default:
  1041. //
  1042. // The RootBridgeIoCheckParameter call above will ensure that this
  1043. // path is not taken.
  1044. //
  1045. ASSERT (FALSE);
  1046. break;
  1047. }
  1048. }
  1049. }
  1050. return EFI_SUCCESS;
  1051. }
  1052. /**
  1053. Polls an address in memory mapped I/O space until an exit condition is met, or
  1054. a timeout occurs.
  1055. This function provides a standard way to poll a PCI memory location. A PCI memory read
  1056. operation is performed at the PCI memory address specified by Address for the width specified
  1057. by Width. The result of this PCI memory read operation is stored in Result. This PCI memory
  1058. read operation is repeated until either a timeout of Delay 100 ns units has expired, or (Result &
  1059. Mask) is equal to Value.
  1060. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  1061. @param[in] Width Signifies the width of the memory operations.
  1062. @param[in] Address The base address of the memory operations. The caller is
  1063. responsible for aligning Address if required.
  1064. @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
  1065. are ignored. The bits in the bytes below Width which are zero in
  1066. Mask are ignored when polling the memory address.
  1067. @param[in] Value The comparison value used for the polling exit criteria.
  1068. @param[in] Delay The number of 100 ns units to poll. Note that timer available may
  1069. be of poorer granularity.
  1070. @param[out] Result Pointer to the last value read from the memory location.
  1071. @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
  1072. @retval EFI_INVALID_PARAMETER Width is invalid.
  1073. @retval EFI_INVALID_PARAMETER Result is NULL.
  1074. @retval EFI_TIMEOUT Delay expired before a match occurred.
  1075. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  1076. **/
  1077. EFI_STATUS
  1078. EFIAPI
  1079. RootBridgeIoPollMem (
  1080. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  1081. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
  1082. IN UINT64 Address,
  1083. IN UINT64 Mask,
  1084. IN UINT64 Value,
  1085. IN UINT64 Delay,
  1086. OUT UINT64 *Result
  1087. )
  1088. {
  1089. EFI_STATUS Status;
  1090. UINT64 NumberOfTicks;
  1091. UINT32 Remainder;
  1092. if (Result == NULL) {
  1093. return EFI_INVALID_PARAMETER;
  1094. }
  1095. //
  1096. // No matter what, always do a single poll.
  1097. //
  1098. Status = This->Mem.Read (This, Width, Address, 1, Result);
  1099. if (EFI_ERROR (Status)) {
  1100. return Status;
  1101. }
  1102. if ((*Result & Mask) == Value) {
  1103. return EFI_SUCCESS;
  1104. }
  1105. if (Delay == 0) {
  1106. return EFI_TIMEOUT;
  1107. } else {
  1108. //
  1109. // Determine the proper # of metronome ticks to wait for polling the
  1110. // location. The nuber of ticks is Roundup (Delay / mMetronome->TickPeriod)+1
  1111. // The "+1" to account for the possibility of the first tick being short
  1112. // because we started in the middle of a tick.
  1113. //
  1114. // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metronome
  1115. // protocol definition is updated.
  1116. //
  1117. NumberOfTicks = DivU64x32Remainder (Delay, (UINT32) mMetronome->TickPeriod, &Remainder);
  1118. if (Remainder != 0) {
  1119. NumberOfTicks += 1;
  1120. }
  1121. NumberOfTicks += 1;
  1122. while (NumberOfTicks != 0) {
  1123. mMetronome->WaitForTick (mMetronome, 1);
  1124. Status = This->Mem.Read (This, Width, Address, 1, Result);
  1125. if (EFI_ERROR (Status)) {
  1126. return Status;
  1127. }
  1128. if ((*Result & Mask) == Value) {
  1129. return EFI_SUCCESS;
  1130. }
  1131. NumberOfTicks -= 1;
  1132. }
  1133. }
  1134. return EFI_TIMEOUT;
  1135. }
  1136. /**
  1137. Reads from the I/O space of a PCI Root Bridge. Returns when either the polling exit criteria is
  1138. satisfied or after a defined duration.
  1139. This function provides a standard way to poll a PCI I/O location. A PCI I/O read operation is
  1140. performed at the PCI I/O address specified by Address for the width specified by Width.
  1141. The result of this PCI I/O read operation is stored in Result. This PCI I/O read operation is
  1142. repeated until either a timeout of Delay 100 ns units has expired, or (Result & Mask) is equal
  1143. to Value.
  1144. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  1145. @param[in] Width Signifies the width of the I/O operations.
  1146. @param[in] Address The base address of the I/O operations. The caller is responsible
  1147. for aligning Address if required.
  1148. @param[in] Mask Mask used for the polling criteria. Bytes above Width in Mask
  1149. are ignored. The bits in the bytes below Width which are zero in
  1150. Mask are ignored when polling the I/O address.
  1151. @param[in] Value The comparison value used for the polling exit criteria.
  1152. @param[in] Delay The number of 100 ns units to poll. Note that timer available may
  1153. be of poorer granularity.
  1154. @param[out] Result Pointer to the last value read from the memory location.
  1155. @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.
  1156. @retval EFI_INVALID_PARAMETER Width is invalid.
  1157. @retval EFI_INVALID_PARAMETER Result is NULL.
  1158. @retval EFI_TIMEOUT Delay expired before a match occurred.
  1159. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  1160. **/
  1161. EFI_STATUS
  1162. EFIAPI
  1163. RootBridgeIoPollIo (
  1164. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  1165. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
  1166. IN UINT64 Address,
  1167. IN UINT64 Mask,
  1168. IN UINT64 Value,
  1169. IN UINT64 Delay,
  1170. OUT UINT64 *Result
  1171. )
  1172. {
  1173. EFI_STATUS Status;
  1174. UINT64 NumberOfTicks;
  1175. UINT32 Remainder;
  1176. //
  1177. // No matter what, always do a single poll.
  1178. //
  1179. if (Result == NULL) {
  1180. return EFI_INVALID_PARAMETER;
  1181. }
  1182. Status = This->Io.Read (This, Width, Address, 1, Result);
  1183. if (EFI_ERROR (Status)) {
  1184. return Status;
  1185. }
  1186. if ((*Result & Mask) == Value) {
  1187. return EFI_SUCCESS;
  1188. }
  1189. if (Delay == 0) {
  1190. return EFI_SUCCESS;
  1191. } else {
  1192. //
  1193. // Determine the proper # of metronome ticks to wait for polling the
  1194. // location. The number of ticks is Roundup (Delay / mMetronome->TickPeriod)+1
  1195. // The "+1" to account for the possibility of the first tick being short
  1196. // because we started in the middle of a tick.
  1197. //
  1198. NumberOfTicks = DivU64x32Remainder (Delay, (UINT32)mMetronome->TickPeriod, &Remainder);
  1199. if (Remainder != 0) {
  1200. NumberOfTicks += 1;
  1201. }
  1202. NumberOfTicks += 1;
  1203. while (NumberOfTicks != 0) {
  1204. mMetronome->WaitForTick (mMetronome, 1);
  1205. Status = This->Io.Read (This, Width, Address, 1, Result);
  1206. if (EFI_ERROR (Status)) {
  1207. return Status;
  1208. }
  1209. if ((*Result & Mask) == Value) {
  1210. return EFI_SUCCESS;
  1211. }
  1212. NumberOfTicks -= 1;
  1213. }
  1214. }
  1215. return EFI_TIMEOUT;
  1216. }
  1217. /**
  1218. Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
  1219. The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
  1220. registers in the PCI root bridge memory space.
  1221. The memory operations are carried out exactly as requested. The caller is responsible for satisfying
  1222. any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
  1223. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  1224. @param[in] Width Signifies the width of the memory operation.
  1225. @param[in] Address The base address of the memory operation. The caller is
  1226. responsible for aligning the Address if required.
  1227. @param[in] Count The number of memory operations to perform. Bytes moved is
  1228. Width size * Count, starting at Address.
  1229. @param[out] Buffer For read operations, the destination buffer to store the results. For
  1230. write operations, the source buffer to write data from.
  1231. @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
  1232. @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
  1233. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  1234. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  1235. **/
  1236. EFI_STATUS
  1237. EFIAPI
  1238. RootBridgeIoMemRead (
  1239. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  1240. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
  1241. IN UINT64 Address,
  1242. IN UINTN Count,
  1243. OUT VOID *Buffer
  1244. )
  1245. {
  1246. return RootBridgeIoMemRW (This, FALSE, Width, Address, Count, Buffer);
  1247. }
  1248. /**
  1249. Enables a PCI driver to access PCI controller registers in the PCI root bridge memory space.
  1250. The Mem.Read(), and Mem.Write() functions enable a driver to access PCI controller
  1251. registers in the PCI root bridge memory space.
  1252. The memory operations are carried out exactly as requested. The caller is responsible for satisfying
  1253. any alignment and memory width restrictions that a PCI Root Bridge on a platform might require.
  1254. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  1255. @param[in] Width Signifies the width of the memory operation.
  1256. @param[in] Address The base address of the memory operation. The caller is
  1257. responsible for aligning the Address if required.
  1258. @param[in] Count The number of memory operations to perform. Bytes moved is
  1259. Width size * Count, starting at Address.
  1260. @param[in] Buffer For read operations, the destination buffer to store the results. For
  1261. write operations, the source buffer to write data from.
  1262. @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
  1263. @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
  1264. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  1265. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  1266. **/
  1267. EFI_STATUS
  1268. EFIAPI
  1269. RootBridgeIoMemWrite (
  1270. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  1271. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
  1272. IN UINT64 Address,
  1273. IN UINTN Count,
  1274. IN VOID *Buffer
  1275. )
  1276. {
  1277. return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer);
  1278. }
  1279. /**
  1280. Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
  1281. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  1282. @param[in] Width Signifies the width of the memory operations.
  1283. @param[in] Address The base address of the I/O operation. The caller is responsible for
  1284. aligning the Address if required.
  1285. @param[in] Count The number of I/O operations to perform. Bytes moved is Width
  1286. size * Count, starting at Address.
  1287. @param[out] Buffer For read operations, the destination buffer to store the results. For
  1288. write operations, the source buffer to write data from.
  1289. @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
  1290. @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
  1291. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  1292. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  1293. **/
  1294. EFI_STATUS
  1295. EFIAPI
  1296. RootBridgeIoIoRead (
  1297. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  1298. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
  1299. IN UINT64 Address,
  1300. IN UINTN Count,
  1301. OUT VOID *Buffer
  1302. )
  1303. {
  1304. return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer);
  1305. }
  1306. /**
  1307. Enables a PCI driver to access PCI controller registers in the PCI root bridge I/O space.
  1308. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  1309. @param[in] Width Signifies the width of the memory operations.
  1310. @param[in] Address The base address of the I/O operation. The caller is responsible for
  1311. aligning the Address if required.
  1312. @param[in] Count The number of I/O operations to perform. Bytes moved is Width
  1313. size * Count, starting at Address.
  1314. @param[in] Buffer For read operations, the destination buffer to store the results. For
  1315. write operations, the source buffer to write data from.
  1316. @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
  1317. @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
  1318. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  1319. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  1320. **/
  1321. EFI_STATUS
  1322. EFIAPI
  1323. RootBridgeIoIoWrite (
  1324. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  1325. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
  1326. IN UINT64 Address,
  1327. IN UINTN Count,
  1328. IN VOID *Buffer
  1329. )
  1330. {
  1331. return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer);
  1332. }
  1333. /**
  1334. Enables a PCI driver to copy one region of PCI root bridge memory space to another region of PCI
  1335. root bridge memory space.
  1336. The CopyMem() function enables a PCI driver to copy one region of PCI root bridge memory
  1337. space to another region of PCI root bridge memory space. This is especially useful for video scroll
  1338. operation on a memory mapped video buffer.
  1339. The memory operations are carried out exactly as requested. The caller is responsible for satisfying
  1340. any alignment and memory width restrictions that a PCI root bridge on a platform might require.
  1341. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL instance.
  1342. @param[in] Width Signifies the width of the memory operations.
  1343. @param[in] DestAddress The destination address of the memory operation. The caller is
  1344. responsible for aligning the DestAddress if required.
  1345. @param[in] SrcAddress The source address of the memory operation. The caller is
  1346. responsible for aligning the SrcAddress if required.
  1347. @param[in] Count The number of memory operations to perform. Bytes moved is
  1348. Width size * Count, starting at DestAddress and SrcAddress.
  1349. @retval EFI_SUCCESS The data was copied from one memory region to another memory region.
  1350. @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
  1351. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  1352. **/
  1353. EFI_STATUS
  1354. EFIAPI
  1355. RootBridgeIoCopyMem (
  1356. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  1357. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
  1358. IN UINT64 DestAddress,
  1359. IN UINT64 SrcAddress,
  1360. IN UINTN Count
  1361. )
  1362. {
  1363. EFI_STATUS Status;
  1364. BOOLEAN Direction;
  1365. UINTN Stride;
  1366. UINTN Index;
  1367. UINT64 Result;
  1368. if ((UINT32)Width > EfiPciWidthUint64) {
  1369. return EFI_INVALID_PARAMETER;
  1370. }
  1371. if (DestAddress == SrcAddress) {
  1372. return EFI_SUCCESS;
  1373. }
  1374. Stride = (UINTN)((UINTN)1 << Width);
  1375. Direction = TRUE;
  1376. if ((DestAddress > SrcAddress) && (DestAddress < (SrcAddress + Count * Stride))) {
  1377. Direction = FALSE;
  1378. SrcAddress = SrcAddress + (Count-1) * Stride;
  1379. DestAddress = DestAddress + (Count-1) * Stride;
  1380. }
  1381. for (Index = 0;Index < Count;Index++) {
  1382. Status = RootBridgeIoMemRead (
  1383. This,
  1384. Width,
  1385. SrcAddress,
  1386. 1,
  1387. &Result
  1388. );
  1389. if (EFI_ERROR (Status)) {
  1390. return Status;
  1391. }
  1392. Status = RootBridgeIoMemWrite (
  1393. This,
  1394. Width,
  1395. DestAddress,
  1396. 1,
  1397. &Result
  1398. );
  1399. if (EFI_ERROR (Status)) {
  1400. return Status;
  1401. }
  1402. if (Direction) {
  1403. SrcAddress += Stride;
  1404. DestAddress += Stride;
  1405. } else {
  1406. SrcAddress -= Stride;
  1407. DestAddress -= Stride;
  1408. }
  1409. }
  1410. return EFI_SUCCESS;
  1411. }
  1412. /**
  1413. Reads memory-mapped registers.
  1414. @param[in] Width Signifies the width of the I/O or Memory operation.
  1415. @param[in] Address The base address of the I/O operation.
  1416. @param[in] Count The number of I/O operations to perform. The number of
  1417. bytes moved is Width size * Count, starting at Address.
  1418. @param[out] Buffer For read operations, the destination buffer to store the results.
  1419. For write operations, the source buffer from which to write data.
  1420. @retval EFI_SUCCESS The data was read from or written to the PI system.
  1421. @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
  1422. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  1423. @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
  1424. @retval EFI_UNSUPPORTED The address range specified by Address, Width,
  1425. and Count is not valid for this PI system.
  1426. **/
  1427. EFI_STATUS
  1428. CpuMemoryServiceRead (
  1429. IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
  1430. IN UINT64 Address,
  1431. IN UINTN Count,
  1432. OUT VOID *Buffer
  1433. )
  1434. {
  1435. UINT8 InStride;
  1436. UINT8 OutStride;
  1437. EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
  1438. UINT8 *Uint8Buffer;
  1439. UINT32 Uint32Buffer = 0;
  1440. //
  1441. // Select loop based on the width of the transfer
  1442. //
  1443. InStride = mInStride[Width];
  1444. OutStride = mOutStride[Width];
  1445. OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
  1446. for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
  1447. if (OperationWidth == EfiCpuIoWidthUint8) {
  1448. Uint32Buffer = MmioRead32((UINTN)(Address & (~0x3)));
  1449. Uint32Buffer &= (0xFF << ((Address & 0x3) * 8));
  1450. *((UINT8*)Uint8Buffer) = (UINT8)(Uint32Buffer >> (((Address & 0x3) * 8)));
  1451. } else if (OperationWidth == EfiCpuIoWidthUint16) {
  1452. if (((Address & 0x3) == 1) || ((Address & 0x3) == 3)) {
  1453. return EFI_INVALID_PARAMETER;
  1454. }
  1455. Uint32Buffer = MmioRead32((UINTN)(Address & (~0x3)));
  1456. Uint32Buffer &= (0xFFFF << ((Address & 0x3) * 8));
  1457. *(UINT16 *)Uint8Buffer = (UINT16)(Uint32Buffer >> (((Address & 0x3) * 8)));
  1458. } else if (OperationWidth == EfiCpuIoWidthUint32) {
  1459. *((UINT32 *)Uint8Buffer) = MmioRead32 ((UINTN)Address);
  1460. } else if (OperationWidth == EfiCpuIoWidthUint64) {
  1461. *((UINT64 *)Uint8Buffer) = MmioRead64 ((UINTN)Address);
  1462. }
  1463. }
  1464. return EFI_SUCCESS;
  1465. }
  1466. /**
  1467. Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
  1468. The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
  1469. registers for a PCI controller.
  1470. The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
  1471. any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
  1472. require.
  1473. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  1474. @param[in] Width Signifies the width of the memory operations.
  1475. @param[in] Address The address within the PCI configuration space for the PCI controller.
  1476. @param[in] Count The number of PCI configuration operations to perform. Bytes
  1477. moved is Width size * Count, starting at Address.
  1478. @param[out] Buffer For read operations, the destination buffer to store the results. For
  1479. write operations, the source buffer to write data from.
  1480. @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
  1481. @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
  1482. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  1483. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  1484. **/
  1485. EFI_STATUS
  1486. EFIAPI
  1487. RootBridgeIoPciRead (
  1488. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  1489. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
  1490. IN UINT64 EfiAddress,
  1491. IN UINTN Count,
  1492. OUT VOID *Buffer
  1493. )
  1494. {
  1495. UINT32 Offset;
  1496. EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *EfiPciAddress;
  1497. UINT64 Address;
  1498. PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
  1499. EfiPciAddress = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *)&EfiAddress;
  1500. PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
  1501. if (Buffer == NULL) {
  1502. return EFI_INVALID_PARAMETER;
  1503. }
  1504. if (Width >= EfiPciWidthMaximum) {
  1505. return EFI_INVALID_PARAMETER;
  1506. }
  1507. if (EfiPciAddress->ExtendedRegister) {
  1508. Offset = EfiPciAddress->ExtendedRegister;
  1509. } else {
  1510. Offset = EfiPciAddress->Register;
  1511. }
  1512. PCIE_DEBUG ("[%a:%d] - bus %x dev %x func %x Off %x\n", __FUNCTION__, __LINE__,
  1513. EfiPciAddress->Bus,
  1514. EfiPciAddress->Device,
  1515. EfiPciAddress->Function,
  1516. Offset
  1517. );
  1518. if (EfiPciAddress->Bus < PrivateData->BusBase || EfiPciAddress->Bus > PrivateData->BusLimit) {
  1519. PCIE_DEBUG ("[%a:%d] - Bus number out of range %d\n", __FUNCTION__, __LINE__, EfiPciAddress->Bus);
  1520. SetMem (Buffer, mOutStride[Width] * Count, 0xFF);
  1521. return EFI_INVALID_PARAMETER;
  1522. }
  1523. // The UEFI PCI enumerator scans for devices at all possible addresses,
  1524. // and ignores some PCI rules - this results in some hardware being
  1525. // detected multiple times. We work around this by faking absent
  1526. // devices
  1527. if(EfiPciAddress->Bus == PrivateData->BusBase)
  1528. {
  1529. if((EfiPciAddress->Device != 0x0) || (EfiPciAddress->Function != 0)) {
  1530. SetMem (Buffer, mOutStride[Width] * Count, 0xFF);
  1531. return EFI_UNSUPPORTED;
  1532. }
  1533. }
  1534. if (EfiPciAddress->Bus == PrivateData->BusBase){
  1535. Address = PrivateData->RbPciBar + Offset;
  1536. }
  1537. else if(EfiPciAddress->Bus == PrivateData->BusBase + 1)
  1538. {
  1539. if (!PcieIsLinkUp(PrivateData->SocType,PrivateData->RbPciBar, PrivateData->Port))
  1540. {
  1541. SetMem (Buffer, mOutStride[Width] * Count, 0xFF);
  1542. return EFI_NOT_READY;
  1543. }
  1544. Address = GetPcieCfgAddress (
  1545. PrivateData->Ecam,
  1546. EfiPciAddress->Bus,
  1547. EfiPciAddress->Device,
  1548. EfiPciAddress->Function,
  1549. Offset
  1550. );
  1551. }
  1552. else
  1553. {
  1554. Address = GetPcieCfgAddress (
  1555. PrivateData->Ecam,
  1556. EfiPciAddress->Bus,
  1557. EfiPciAddress->Device,
  1558. EfiPciAddress->Function,
  1559. Offset
  1560. );
  1561. }
  1562. (VOID)CpuMemoryServiceRead((EFI_CPU_IO_PROTOCOL_WIDTH)Width, Address, Count, Buffer);
  1563. PCIE_DEBUG ("[%a:%d] - %x\n", __FUNCTION__, __LINE__, *(UINT32 *)Buffer);
  1564. return EFI_SUCCESS;
  1565. }
  1566. /**
  1567. Writes memory-mapped registers.
  1568. @param[in] Width Signifies the width of the I/O or Memory operation.
  1569. @param[in] Address The base address of the I/O operation.
  1570. @param[in] Count The number of I/O operations to perform. The number of
  1571. bytes moved is Width size * Count, starting at Address.
  1572. @param[in] Buffer For read operations, the destination buffer to store the results.
  1573. For write operations, the source buffer from which to write data.
  1574. @retval EFI_SUCCESS The data was read from or written to the PI system.
  1575. @retval EFI_INVALID_PARAMETER Width is invalid for this PI system.
  1576. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  1577. @retval EFI_UNSUPPORTED The Buffer is not aligned for the given Width.
  1578. @retval EFI_UNSUPPORTED The address range specified by Address, Width,
  1579. and Count is not valid for this PI system.
  1580. **/
  1581. EFI_STATUS
  1582. CpuMemoryServiceWrite (
  1583. IN EFI_CPU_IO_PROTOCOL_WIDTH Width,
  1584. IN UINT64 Address,
  1585. IN UINTN Count,
  1586. IN VOID *Buffer
  1587. )
  1588. {
  1589. UINT8 InStride;
  1590. UINT8 OutStride;
  1591. EFI_CPU_IO_PROTOCOL_WIDTH OperationWidth;
  1592. UINT8 *Uint8Buffer;
  1593. UINT32 Uint32Buffer;
  1594. //
  1595. // Select loop based on the width of the transfer
  1596. //
  1597. InStride = mInStride[Width];
  1598. OutStride = mOutStride[Width];
  1599. OperationWidth = (EFI_CPU_IO_PROTOCOL_WIDTH) (Width & 0x03);
  1600. for (Uint8Buffer = Buffer; Count > 0; Address += InStride, Uint8Buffer += OutStride, Count--) {
  1601. if (OperationWidth == EfiCpuIoWidthUint8) {
  1602. Uint32Buffer = MmioRead32 ((UINTN)(Address & (~0x03)));
  1603. Uint32Buffer &= ~(UINT32)(0xFF << ((Address & 0x3) * 8));
  1604. Uint32Buffer |= (UINT32)(*(UINT8 *)Uint8Buffer) << ((Address & 0x3) * 8);
  1605. MmioWrite32 ((UINTN)(Address & (~0x03)), Uint32Buffer);
  1606. } else if (OperationWidth == EfiCpuIoWidthUint16) {
  1607. if (((Address & 0x3) == 1) || ((Address & 0x3) == 3)) {
  1608. return EFI_INVALID_PARAMETER;
  1609. }
  1610. Uint32Buffer = MmioRead32 ((UINTN)(Address & (~0x03)));
  1611. Uint32Buffer &= ~(UINT32)(0xFFFF << ((Address & 0x3) * 8));
  1612. Uint32Buffer |= (UINT32)(*(UINT16 *)Uint8Buffer) << ((Address & 0x3) * 8);
  1613. MmioWrite32 ((UINTN)(Address & (~0x03)), Uint32Buffer);
  1614. } else if (OperationWidth == EfiCpuIoWidthUint32) {
  1615. MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer));
  1616. } else if (OperationWidth == EfiCpuIoWidthUint64) {
  1617. MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer));
  1618. }
  1619. }
  1620. return EFI_SUCCESS;
  1621. }
  1622. /**
  1623. Enables a PCI driver to access PCI controller registers in a PCI root bridge's configuration space.
  1624. The Pci.Read() and Pci.Write() functions enable a driver to access PCI configuration
  1625. registers for a PCI controller.
  1626. The PCI Configuration operations are carried out exactly as requested. The caller is responsible for
  1627. any alignment and PCI configuration width issues that a PCI Root Bridge on a platform might
  1628. require.
  1629. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  1630. @param[in] Width Signifies the width of the memory operations.
  1631. @param[in] Address The address within the PCI configuration space for the PCI controller.
  1632. @param[in] Count The number of PCI configuration operations to perform. Bytes
  1633. moved is Width size * Count, starting at Address.
  1634. @param[in] Buffer For read operations, the destination buffer to store the results. For
  1635. write operations, the source buffer to write data from.
  1636. @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.
  1637. @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge.
  1638. @retval EFI_INVALID_PARAMETER Buffer is NULL.
  1639. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  1640. **/
  1641. EFI_STATUS
  1642. EFIAPI
  1643. RootBridgeIoPciWrite (
  1644. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  1645. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,
  1646. IN UINT64 EfiAddress,
  1647. IN UINTN Count,
  1648. IN VOID *Buffer
  1649. )
  1650. {
  1651. UINT32 Offset;
  1652. EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *EfiPciAddress;
  1653. UINT64 Address;
  1654. PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
  1655. EfiPciAddress = (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *)&EfiAddress;
  1656. PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
  1657. if (Buffer == NULL) {
  1658. return EFI_INVALID_PARAMETER;
  1659. }
  1660. if (Width >= EfiPciWidthMaximum) {
  1661. return EFI_INVALID_PARAMETER;
  1662. }
  1663. if (EfiPciAddress->ExtendedRegister)
  1664. Offset = EfiPciAddress->ExtendedRegister;
  1665. else
  1666. Offset = EfiPciAddress->Register;
  1667. PCIE_DEBUG ("[%a:%d] - bus %x dev %x func %x Off %x\n", __FUNCTION__, __LINE__,
  1668. EfiPciAddress->Bus,
  1669. EfiPciAddress->Device,
  1670. EfiPciAddress->Function,
  1671. Offset
  1672. );
  1673. if (((EfiPciAddress->Bus == PrivateData->BusBase) && (EfiPciAddress->Device == 0x00) && (EfiPciAddress->Function == 0))){
  1674. Address = PrivateData->RbPciBar + Offset;
  1675. if ((Offset == 0x14) || (Offset == 0x10)) {
  1676. return EFI_SUCCESS;
  1677. }
  1678. }
  1679. else if (EfiPciAddress->Bus == PrivateData->BusBase + 1)
  1680. {
  1681. if (!PcieIsLinkUp(PrivateData->SocType,PrivateData->RbPciBar, PrivateData->Port)) {
  1682. return EFI_NOT_READY;
  1683. }
  1684. Address = GetPcieCfgAddress (
  1685. PrivateData->Ecam,
  1686. EfiPciAddress->Bus,
  1687. EfiPciAddress->Device,
  1688. EfiPciAddress->Function,
  1689. Offset
  1690. );
  1691. }
  1692. else
  1693. {
  1694. Address = GetPcieCfgAddress (
  1695. PrivateData->Ecam,
  1696. EfiPciAddress->Bus,
  1697. EfiPciAddress->Device,
  1698. EfiPciAddress->Function,
  1699. Offset
  1700. );
  1701. }
  1702. (VOID)CpuMemoryServiceWrite ((EFI_CPU_IO_PROTOCOL_WIDTH)Width, Address, Count, Buffer);
  1703. PCIE_DEBUG ("[%a:%d] - 0x%08x\n", __FUNCTION__, __LINE__, *(UINT32 *)Buffer);
  1704. return EFI_SUCCESS;
  1705. }
  1706. /**
  1707. Provides the PCI controller-specific addresses required to access system memory from a
  1708. DMA bus master.
  1709. The Map() function provides the PCI controller specific addresses needed to access system
  1710. memory. This function is used to map system memory for PCI bus master DMA accesses.
  1711. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  1712. @param[in] Operation Indicates if the bus master is going to read or write to system memory.
  1713. @param[in] HostAddress The system memory address to map to the PCI controller.
  1714. @param[in, out] NumberOfBytes On input the number of bytes to map. On output the number of bytes that were mapped.
  1715. @param[out] DeviceAddress The resulting map address for the bus master PCI controller to use
  1716. to access the system memory's HostAddress.
  1717. @param[out] Mapping The value to pass to Unmap() when the bus master DMA operation is complete.
  1718. @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
  1719. @retval EFI_INVALID_PARAMETER Operation is invalid.
  1720. @retval EFI_INVALID_PARAMETER HostAddress is NULL.
  1721. @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL.
  1722. @retval EFI_INVALID_PARAMETER DeviceAddress is NULL.
  1723. @retval EFI_INVALID_PARAMETER Mapping is NULL.
  1724. @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
  1725. @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
  1726. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  1727. **/
  1728. EFI_STATUS
  1729. EFIAPI
  1730. RootBridgeIoMap (
  1731. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  1732. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation,
  1733. IN VOID *HostAddress,
  1734. IN OUT UINTN *NumberOfBytes,
  1735. OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,
  1736. OUT VOID **Mapping
  1737. )
  1738. {
  1739. DMA_MAP_OPERATION DmaOperation;
  1740. if (Operation == EfiPciOperationBusMasterRead) {
  1741. DmaOperation = MapOperationBusMasterRead;
  1742. } else if (Operation == EfiPciOperationBusMasterWrite) {
  1743. DmaOperation = MapOperationBusMasterWrite;
  1744. } else if (Operation == EfiPciOperationBusMasterCommonBuffer) {
  1745. DmaOperation = MapOperationBusMasterCommonBuffer;
  1746. } else if (Operation == EfiPciOperationBusMasterRead64) {
  1747. DmaOperation = MapOperationBusMasterRead;
  1748. } else if (Operation == EfiPciOperationBusMasterWrite64) {
  1749. DmaOperation = MapOperationBusMasterWrite;
  1750. } else if (Operation == EfiPciOperationBusMasterCommonBuffer64) {
  1751. DmaOperation = MapOperationBusMasterCommonBuffer;
  1752. } else {
  1753. return EFI_INVALID_PARAMETER;
  1754. }
  1755. (VOID)DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, Mapping);
  1756. return EFI_SUCCESS;
  1757. }
  1758. /**
  1759. Completes the Map() operation and releases any corresponding resources.
  1760. The Unmap() function completes the Map() operation and releases any corresponding resources.
  1761. If the operation was an EfiPciOperationBusMasterWrite or
  1762. EfiPciOperationBusMasterWrite64, the data is committed to the target system memory.
  1763. Any resources used for the mapping are freed.
  1764. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  1765. @param[in] Mapping The mapping value returned from Map().
  1766. @retval EFI_SUCCESS The range was unmapped.
  1767. @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().
  1768. @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
  1769. **/
  1770. EFI_STATUS
  1771. EFIAPI
  1772. RootBridgeIoUnmap (
  1773. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  1774. IN VOID *Mapping
  1775. )
  1776. {
  1777. return DmaUnmap (Mapping);
  1778. }
  1779. /**
  1780. Allocates pages that are suitable for an EfiPciOperationBusMasterCommonBuffer or
  1781. EfiPciOperationBusMasterCommonBuffer64 mapping.
  1782. @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  1783. @param Type This parameter is not used and must be ignored.
  1784. @param MemoryType The type of memory to allocate, EfiBootServicesData or EfiRuntimeServicesData.
  1785. @param Pages The number of pages to allocate.
  1786. @param HostAddress A pointer to store the base system memory address of the allocated range.
  1787. @param Attributes The requested bit mask of attributes for the allocated range. Only
  1788. the attributes EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, EFI_PCI_ATTRIBUTE_MEMORY_CACHED,
  1789. and EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with this function.
  1790. @retval EFI_SUCCESS The requested memory pages were allocated.
  1791. @retval EFI_INVALID_PARAMETER MemoryType is invalid.
  1792. @retval EFI_INVALID_PARAMETER HostAddress is NULL.
  1793. @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
  1794. MEMORY_WRITE_COMBINE, MEMORY_CACHED, and DUAL_ADDRESS_CYCLE.
  1795. @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
  1796. **/
  1797. EFI_STATUS
  1798. EFIAPI
  1799. RootBridgeIoAllocateBuffer (
  1800. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  1801. IN EFI_ALLOCATE_TYPE Type,
  1802. IN EFI_MEMORY_TYPE MemoryType,
  1803. IN UINTN Pages,
  1804. OUT VOID **HostAddress,
  1805. IN UINT64 Attributes
  1806. )
  1807. {
  1808. if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) {
  1809. return EFI_UNSUPPORTED;
  1810. }
  1811. return DmaAllocateBuffer (MemoryType, Pages, HostAddress);
  1812. }
  1813. /**
  1814. Frees memory that was allocated with AllocateBuffer().
  1815. The FreeBuffer() function frees memory that was allocated with AllocateBuffer().
  1816. @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  1817. @param Pages The number of pages to free.
  1818. @param HostAddress The base system memory address of the allocated range.
  1819. @retval EFI_SUCCESS The requested memory pages were freed.
  1820. @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
  1821. was not allocated with AllocateBuffer().
  1822. **/
  1823. EFI_STATUS
  1824. EFIAPI
  1825. RootBridgeIoFreeBuffer (
  1826. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  1827. IN UINTN Pages,
  1828. OUT VOID *HostAddress
  1829. )
  1830. {
  1831. return DmaFreeBuffer (Pages, HostAddress);
  1832. }
  1833. /**
  1834. Flushes all PCI posted write transactions from a PCI host bridge to system memory.
  1835. The Flush() function flushes any PCI posted write transactions from a PCI host bridge to system
  1836. memory. Posted write transactions are generated by PCI bus masters when they perform write
  1837. transactions to target addresses in system memory.
  1838. This function does not flush posted write transactions from any PCI bridges. A PCI controller
  1839. specific action must be taken to guarantee that the posted write transactions have been flushed from
  1840. the PCI controller and from all the PCI bridges into the PCI host bridge. This is typically done with
  1841. a PCI read transaction from the PCI controller prior to calling Flush().
  1842. @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  1843. @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host
  1844. bridge to system memory.
  1845. @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI
  1846. host bridge due to a hardware error.
  1847. **/
  1848. EFI_STATUS
  1849. EFIAPI
  1850. RootBridgeIoFlush (
  1851. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This
  1852. )
  1853. {
  1854. //
  1855. // not supported yet
  1856. //
  1857. return EFI_SUCCESS;
  1858. }
  1859. /**
  1860. Gets the attributes that a PCI root bridge supports setting with SetAttributes(), and the
  1861. attributes that a PCI root bridge is currently using.
  1862. The GetAttributes() function returns the mask of attributes that this PCI root bridge supports
  1863. and the mask of attributes that the PCI root bridge is currently using.
  1864. @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  1865. @param Supported A pointer to the mask of attributes that this PCI root bridge
  1866. supports setting with SetAttributes().
  1867. @param Attributes A pointer to the mask of attributes that this PCI root bridge is
  1868. currently using.
  1869. @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI root
  1870. bridge supports is returned in Supports. If Attributes is
  1871. not NULL, then the attributes that the PCI root bridge is currently
  1872. using is returned in Attributes.
  1873. @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.
  1874. **/
  1875. EFI_STATUS
  1876. EFIAPI
  1877. RootBridgeIoGetAttributes (
  1878. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  1879. OUT UINT64 *Supported,
  1880. OUT UINT64 *Attributes
  1881. )
  1882. {
  1883. PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
  1884. PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
  1885. if (Attributes == NULL && Supported == NULL) {
  1886. return EFI_INVALID_PARAMETER;
  1887. }
  1888. //
  1889. // Set the return value for Supported and Attributes
  1890. //
  1891. if (Supported != NULL) {
  1892. *Supported = PrivateData->Supports;
  1893. }
  1894. if (Attributes != NULL) {
  1895. *Attributes = PrivateData->Attributes;
  1896. }
  1897. return EFI_SUCCESS;
  1898. }
  1899. /**
  1900. Sets attributes for a resource range on a PCI root bridge.
  1901. The SetAttributes() function sets the attributes specified in Attributes for the PCI root
  1902. bridge on the resource range specified by ResourceBase and ResourceLength. Since the
  1903. granularity of setting these attributes may vary from resource type to resource type, and from
  1904. platform to platform, the actual resource range and the one passed in by the caller may differ. As a
  1905. result, this function may set the attributes specified by Attributes on a larger resource range
  1906. than the caller requested. The actual range is returned in ResourceBase and
  1907. ResourceLength. The caller is responsible for verifying that the actual range for which the
  1908. attributes were set is acceptable.
  1909. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  1910. @param[in] Attributes The mask of attributes to set. If the attribute bit
  1911. MEMORY_WRITE_COMBINE, MEMORY_CACHED, or
  1912. MEMORY_DISABLE is set, then the resource range is specified by
  1913. ResourceBase and ResourceLength. If
  1914. MEMORY_WRITE_COMBINE, MEMORY_CACHED, and
  1915. MEMORY_DISABLE are not set, then ResourceBase and
  1916. ResourceLength are ignored, and may be NULL.
  1917. @param[in, out] ResourceBase A pointer to the base address of the resource range to be modified
  1918. by the attributes specified by Attributes.
  1919. @param[in, out] ResourceLength A pointer to the length of the resource range to be modified by the
  1920. attributes specified by Attributes.
  1921. @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
  1922. @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
  1923. @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
  1924. **/
  1925. EFI_STATUS
  1926. EFIAPI
  1927. RootBridgeIoSetAttributes (
  1928. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  1929. IN UINT64 Attributes,
  1930. IN OUT UINT64 *ResourceBase,
  1931. IN OUT UINT64 *ResourceLength
  1932. )
  1933. {
  1934. PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
  1935. PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(This);
  1936. if (Attributes != 0) {
  1937. if ((Attributes & (~(PrivateData->Supports))) != 0) {
  1938. return EFI_UNSUPPORTED;
  1939. }
  1940. }
  1941. //
  1942. // This is a generic driver for a PC-AT class system. It does not have any
  1943. // chipset specific knowlegde, so none of the attributes can be set or
  1944. // cleared. Any attempt to set attribute that are already set will succeed,
  1945. // and any attempt to set an attribute that is not supported will fail.
  1946. //
  1947. if (Attributes & (~PrivateData->Attributes)) {
  1948. /* FIXME: */
  1949. return EFI_UNSUPPORTED;
  1950. }
  1951. return EFI_SUCCESS;
  1952. }
  1953. /**
  1954. Retrieves the current resource settings of this PCI root bridge in the form of a set of ACPI 2.0
  1955. resource descriptors.
  1956. There are only two resource descriptor types from the ACPI Specification that may be used to
  1957. describe the current resources allocated to a PCI root bridge. These are the QWORD Address
  1958. Space Descriptor (ACPI 2.0 Section 6.4.3.5.1), and the End Tag (ACPI 2.0 Section 6.4.2.8). The
  1959. QWORD Address Space Descriptor can describe memory, I/O, and bus number ranges for dynamic
  1960. or fixed resources. The configuration of a PCI root bridge is described with one or more QWORD
  1961. Address Space Descriptors followed by an End Tag.
  1962. @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.
  1963. @param[out] Resources A pointer to the ACPI 2.0 resource descriptors that describe the
  1964. current configuration of this PCI root bridge. The storage for the
  1965. ACPI 2.0 resource descriptors is allocated by this function. The
  1966. caller must treat the return buffer as read-only data, and the buffer
  1967. must not be freed by the caller.
  1968. @retval EFI_SUCCESS The current configuration of this PCI root bridge was returned in Resources.
  1969. @retval EFI_UNSUPPORTED The current configuration of this PCI root bridge could not be retrieved.
  1970. @retval EFI_INVALID_PARAMETER Invalid pointer of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
  1971. **/
  1972. EFI_STATUS
  1973. EFIAPI
  1974. RootBridgeIoConfiguration (
  1975. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This,
  1976. OUT VOID **Resources
  1977. )
  1978. {
  1979. PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
  1980. UINTN Index;
  1981. PrivateData = DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This);
  1982. for (Index = 0; Index < TypeMax; Index++) {
  1983. if (PrivateData->ResAllocNode[Index].Status == ResAllocated) {
  1984. Configuration.SpaceDesp[Index].AddrRangeMin = PrivateData->ResAllocNode[Index].Base;
  1985. Configuration.SpaceDesp[Index].AddrRangeMax = PrivateData->ResAllocNode[Index].Base + PrivateData->ResAllocNode[Index].Length - 1;
  1986. Configuration.SpaceDesp[Index].AddrLen = PrivateData->ResAllocNode[Index].Length;
  1987. }
  1988. }
  1989. *Resources = &Configuration;
  1990. return EFI_SUCCESS;
  1991. }