PciHostBridge.h 25 KB

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  1. /**
  2. * Copyright (c) 2014, AppliedMicro Corp. All rights reserved.
  3. * Copyright (c) 2016, Hisilicon Limited. All rights reserved.
  4. * Copyright (c) 2016, Linaro Limited. All rights reserved.
  5. *
  6. * This program and the accompanying materials
  7. * are licensed and made available under the terms and conditions of the BSD License
  8. * which accompanies this distribution. The full text of the license may be found at
  9. * http://opensource.org/licenses/bsd-license.php
  10. *
  11. * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12. * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13. *
  14. **/
  15. #ifndef _PCI_HOST_BRIDGE_H_
  16. #define _PCI_HOST_BRIDGE_H_
  17. #include <PiDxe.h>
  18. #include <IndustryStandard/Pci.h>
  19. #include <IndustryStandard/Acpi.h>
  20. #include <Protocol/PciHostBridgeResourceAllocation.h>
  21. #include <Protocol/PciRootBridgeIo.h>
  22. #include <Protocol/Metronome.h>
  23. #include <Protocol/DevicePath.h>
  24. #include <Protocol/PciIo.h>
  25. #include <Protocol/CpuIo2.h>
  26. #include <Library/BaseLib.h>
  27. #include <Library/DebugLib.h>
  28. #include <Library/BaseMemoryLib.h>
  29. #include <Library/MemoryAllocationLib.h>
  30. #include <Library/UefiLib.h>
  31. #include <Library/UefiBootServicesTableLib.h>
  32. #include <Library/DxeServicesTableLib.h>
  33. #include <Library/DevicePathLib.h>
  34. #include <Library/IoLib.h>
  35. #include <Library/PciLib.h>
  36. #include <Library/PcdLib.h>
  37. #include <Library/PlatformPciLib.h>
  38. // Enable below statments to enable PCIE debug
  39. //#define PCIE_DEBUG_ENABLE
  40. //#define PCIE_VDEBUG_ENABLE
  41. //#define PCIE_CDEBUG_ENABLE
  42. #ifdef PCIE_CDEBUG_ENABLE
  43. # define PCIE_CSR_DEBUG(arg...) DEBUG((EFI_D_VERBOSE,## arg))
  44. #else
  45. # define PCIE_CSR_DEBUG(arg...)
  46. #endif
  47. #ifdef PCIE_VDEBUG_ENABLE
  48. # define PCIE_VDEBUG(arg...) DEBUG((EFI_D_VERBOSE,## arg))
  49. #else
  50. # define PCIE_VDEBUG(arg...)
  51. #endif
  52. #ifdef PCIE_DEBUG_ENABLE
  53. # define PCIE_DEBUG(arg...) DEBUG((EFI_D_VERBOSE,## arg))
  54. #else
  55. # define PCIE_DEBUG(arg...)
  56. #endif
  57. #define PCIE_WARN(arg...) DEBUG((EFI_D_WARN,## arg))
  58. #define PCIE_ERR(arg...) DEBUG((EFI_D_ERROR,## arg))
  59. #define PCIE_INFO(arg...) DEBUG((EFI_D_INFO,## arg))
  60. #define MAX_PCI_DEVICE_NUMBER 31
  61. #define MAX_PCI_FUNCTION_NUMBER 7
  62. #define MAX_PCI_REG_ADDRESS 0xFFFF
  63. typedef enum {
  64. IoOperation,
  65. MemOperation,
  66. PciOperation
  67. } OPERATION_TYPE;
  68. #define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32('e', 'h', 's', 't')
  69. typedef struct {
  70. UINTN Signature;
  71. EFI_HANDLE HostBridgeHandle;
  72. UINTN RootBridgeNumber;
  73. LIST_ENTRY Head;
  74. BOOLEAN ResourceSubmited;
  75. BOOLEAN CanRestarted;
  76. EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc;
  77. } PCI_HOST_BRIDGE_INSTANCE;
  78. #define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) \
  79. CR(a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE)
  80. //
  81. // HostBridge Resource Allocation interface
  82. //
  83. /**
  84. These are the notifications from the PCI bus driver that it is about to enter a certain
  85. phase of the PCI enumeration process.
  86. This member function can be used to notify the host bridge driver to perform specific actions,
  87. including any chipset-specific initialization, so that the chipset is ready to enter the next phase.
  88. Eight notification points are defined at this time. See belows:
  89. EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data
  90. structures. The PCI enumerator should issue this notification
  91. before starting a fresh enumeration process. Enumeration cannot
  92. be restarted after sending any other notification such as
  93. EfiPciHostBridgeBeginBusAllocation.
  94. EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is
  95. required here. This notification can be used to perform any
  96. chipset-specific programming.
  97. EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No
  98. specific action is required here. This notification can be used to
  99. perform any chipset-specific programming.
  100. EfiPciHostBridgeBeginResourceAllocation
  101. The resource allocation phase is about to begin. No specific
  102. action is required here. This notification can be used to perform
  103. any chipset-specific programming.
  104. EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI
  105. root bridges. These resource settings are returned on the next call to
  106. GetProposedResources(). Before calling NotifyPhase() with a Phase of
  107. EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible
  108. for gathering I/O and memory requests for
  109. all the PCI root bridges and submitting these requests using
  110. SubmitResources(). This function pads the resource amount
  111. to suit the root bridge hardware, takes care of dependencies between
  112. the PCI root bridges, and calls the Global Coherency Domain (GCD)
  113. with the allocation request. In the case of padding, the allocated range
  114. could be bigger than what was requested.
  115. EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated
  116. resources (proposed resources) for all the PCI root bridges. After the
  117. hardware is programmed, reassigning resources will not be supported.
  118. The bus settings are not affected.
  119. EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI
  120. root bridges and resets the I/O and memory apertures to their initial
  121. state. The bus settings are not affected. If the request to allocate
  122. resources fails, the PCI enumerator can use this notification to
  123. deallocate previous resources, adjust the requests, and retry
  124. allocation.
  125. EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is
  126. required here. This notification can be used to perform any chipsetspecific
  127. programming.
  128. @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
  129. @param[in] Phase The phase during enumeration
  130. @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error
  131. is valid for a Phase of EfiPciHostBridgeAllocateResources if
  132. SubmitResources() has not been called for one or more
  133. PCI root bridges before this call
  134. @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid
  135. for a Phase of EfiPciHostBridgeSetResources.
  136. @retval EFI_INVALID_PARAMETER Invalid phase parameter
  137. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  138. This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the
  139. previously submitted resource requests cannot be fulfilled or
  140. were only partially fulfilled.
  141. @retval EFI_SUCCESS The notification was accepted without any errors.
  142. **/
  143. EFI_STATUS
  144. EFIAPI
  145. NotifyPhase(
  146. IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
  147. IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
  148. );
  149. /**
  150. Return the device handle of the next PCI root bridge that is associated with this Host Bridge.
  151. This function is called multiple times to retrieve the device handles of all the PCI root bridges that
  152. are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI
  153. root bridges. On each call, the handle that was returned by the previous call is passed into the
  154. interface, and on output the interface returns the device handle of the next PCI root bridge. The
  155. caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
  156. for that root bridge. When there are no more PCI root bridges to report, the interface returns
  157. EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they
  158. are returned by this function.
  159. For D945 implementation, there is only one root bridge in PCI host bridge.
  160. @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
  161. @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge.
  162. @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the
  163. specific Host bridge and return EFI_SUCCESS.
  164. @retval EFI_NOT_FOUND Can not find the any more root bridge in specific host bridge.
  165. @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was
  166. returned on a previous call to GetNextRootBridge().
  167. **/
  168. EFI_STATUS
  169. EFIAPI
  170. GetNextRootBridge(
  171. IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
  172. IN OUT EFI_HANDLE *RootBridgeHandle
  173. );
  174. /**
  175. Returns the allocation attributes of a PCI root bridge.
  176. The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary
  177. from one PCI root bridge to another. These attributes are different from the decode-related
  178. attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The
  179. RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device
  180. handles of all the root bridges that are associated with this host bridge must be obtained by calling
  181. GetNextRootBridge(). The attributes are static in the sense that they do not change during or
  182. after the enumeration process. The hardware may provide mechanisms to change the attributes on
  183. the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is
  184. installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in
  185. "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.
  186. For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to
  187. include requests for the prefetchable memory in the nonprefetchable memory pool and not request any
  188. prefetchable memory.
  189. Attribute Description
  190. ------------------------------------ ----------------------------------------------------------------------
  191. EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root bridge does not support separate
  192. windows for nonprefetchable and prefetchable memory. A PCI bus
  193. driver needs to include requests for prefetchable memory in the
  194. nonprefetchable memory pool.
  195. EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root bridge supports 64-bit memory
  196. windows. If this bit is not set, the PCI bus driver needs to include
  197. requests for a 64-bit memory address in the corresponding 32-bit
  198. memory pool.
  199. @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
  200. @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested. Type
  201. EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
  202. @param[out] Attributes The pointer to attribte of root bridge, it is output parameter
  203. @retval EFI_INVALID_PARAMETER Attribute pointer is NULL
  204. @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.
  205. @retval EFI_SUCCESS Success to get attribute of interested root bridge.
  206. **/
  207. EFI_STATUS
  208. EFIAPI
  209. GetAttributes(
  210. IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
  211. IN EFI_HANDLE RootBridgeHandle,
  212. OUT UINT64 *Attributes
  213. );
  214. /**
  215. Sets up the specified PCI root bridge for the bus enumeration process.
  216. This member function sets up the root bridge for bus enumeration and returns the PCI bus range
  217. over which the search should be performed in ACPI 2.0 resource descriptor format.
  218. @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.
  219. @param[in] RootBridgeHandle The PCI Root Bridge to be set up.
  220. @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor.
  221. @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle
  222. @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.
  223. @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.
  224. **/
  225. EFI_STATUS
  226. EFIAPI
  227. StartBusEnumeration(
  228. IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
  229. IN EFI_HANDLE RootBridgeHandle,
  230. OUT VOID **Configuration
  231. );
  232. /**
  233. Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.
  234. This member function programs the specified PCI root bridge to decode the bus range that is
  235. specified by the input parameter Configuration.
  236. The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.
  237. @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
  238. @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be programmed
  239. @param[in] Configuration The pointer to the PCI bus resource descriptor
  240. @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
  241. @retval EFI_INVALID_PARAMETER Configuration is NULL.
  242. @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.
  243. @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource descriptor.
  244. @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than
  245. bus descriptors.
  246. @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource descriptors.
  247. @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.
  248. @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.
  249. @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
  250. @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.
  251. **/
  252. EFI_STATUS
  253. EFIAPI
  254. SetBusNumbers(
  255. IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
  256. IN EFI_HANDLE RootBridgeHandle,
  257. IN VOID *Configuration
  258. );
  259. /**
  260. Submits the I/O and memory resource requirements for the specified PCI root bridge.
  261. This function is used to submit all the I/O and memory resources that are required by the specified
  262. PCI root bridge. The input parameter Configuration is used to specify the following:
  263. - The various types of resources that are required
  264. - The associated lengths in terms of ACPI 2.0 resource descriptor format
  265. @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
  266. @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being submitted.
  267. @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor.
  268. @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were accepted.
  269. @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
  270. @retval EFI_INVALID_PARAMETER Configuration is NULL.
  271. @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.
  272. @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are
  273. not supported by this PCI root bridge. This error will happen if the caller
  274. did not combine resources according to Attributes that were returned by
  275. GetAllocAttributes().
  276. @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.
  277. @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.
  278. @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.
  279. **/
  280. EFI_STATUS
  281. EFIAPI
  282. SubmitResources(
  283. IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
  284. IN EFI_HANDLE RootBridgeHandle,
  285. IN VOID *Configuration
  286. );
  287. /**
  288. Returns the proposed resource settings for the specified PCI root bridge.
  289. This member function returns the proposed resource settings for the specified PCI root bridge. The
  290. proposed resource settings are prepared when NotifyPhase() is called with a Phase of
  291. EfiPciHostBridgeAllocateResources. The output parameter Configuration
  292. specifies the following:
  293. - The various types of resources, excluding bus resources, that are allocated
  294. - The associated lengths in terms of ACPI 2.0 resource descriptor format
  295. @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
  296. @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
  297. @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.
  298. @retval EFI_SUCCESS The requested parameters were returned.
  299. @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
  300. @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
  301. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  302. **/
  303. EFI_STATUS
  304. EFIAPI
  305. GetProposedResources(
  306. IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
  307. IN EFI_HANDLE RootBridgeHandle,
  308. OUT VOID **Configuration
  309. );
  310. /**
  311. Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various
  312. stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual
  313. PCI controllers before enumeration.
  314. This function is called during the PCI enumeration process. No specific action is expected from this
  315. member function. It allows the host bridge driver to preinitialize individual PCI controllers before
  316. enumeration.
  317. @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
  318. @param RootBridgeHandle The associated PCI root bridge handle. Type EFI_HANDLE is defined in
  319. InstallProtocolInterface() in the UEFI 2.0 Specification.
  320. @param PciAddress The address of the PCI device on the PCI bus. This address can be passed to the
  321. EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI
  322. configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for
  323. the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.
  324. @param Phase The phase of the PCI device enumeration.
  325. @retval EFI_SUCCESS The requested parameters were returned.
  326. @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
  327. @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in
  328. EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
  329. @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should
  330. not enumerate this device, including its child devices if it is a PCI-to-PCI
  331. bridge.
  332. **/
  333. EFI_STATUS
  334. EFIAPI
  335. PreprocessController (
  336. IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
  337. IN EFI_HANDLE RootBridgeHandle,
  338. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
  339. IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
  340. );
  341. //
  342. // Define resource status constant
  343. //
  344. #define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL
  345. #define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
  346. //
  347. // Driver Instance Data Prototypes
  348. //
  349. typedef struct {
  350. EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation;
  351. UINTN NumberOfBytes;
  352. UINTN NumberOfPages;
  353. EFI_PHYSICAL_ADDRESS HostAddress;
  354. EFI_PHYSICAL_ADDRESS MappedHostAddress;
  355. } MAP_INFO;
  356. typedef struct {
  357. ACPI_HID_DEVICE_PATH AcpiDevicePath;
  358. EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
  359. } EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
  360. typedef enum {
  361. TypeIo = 0,
  362. TypeMem32,
  363. TypePMem32,
  364. TypeMem64,
  365. TypePMem64,
  366. TypeBus,
  367. TypeMax
  368. } PCI_RESOURCE_TYPE;
  369. typedef enum {
  370. ResNone = 0,
  371. ResSubmitted,
  372. ResRequested,
  373. ResAllocated,
  374. ResStatusMax
  375. } RES_STATUS;
  376. typedef struct {
  377. PCI_RESOURCE_TYPE Type;
  378. UINT64 Base;
  379. UINT64 Length;
  380. UINT64 Alignment;
  381. RES_STATUS Status;
  382. } PCI_RES_NODE;
  383. #define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32('e', '2', 'p', 'b')
  384. typedef struct {
  385. UINT32 Signature;
  386. LIST_ENTRY Link;
  387. EFI_HANDLE Handle;
  388. UINT64 RootBridgeAttrib;
  389. UINT64 Attributes;
  390. UINT64 Supports;
  391. //
  392. // Specific for this memory controller: Bus, I/O, Mem
  393. //
  394. PCI_RES_NODE ResAllocNode[6];
  395. //
  396. // Addressing for Memory and I/O and Bus arrange
  397. //
  398. UINT64 BusBase;
  399. UINT64 MemBase;
  400. UINT64 IoBase;
  401. UINT64 BusLimit;
  402. UINT64 MemLimit;
  403. UINT64 IoLimit;
  404. UINT64 RbPciBar;
  405. UINT64 Ecam;
  406. UINTN PciAddress;
  407. UINTN PciData;
  408. UINTN Port;
  409. UINT32 SocType;
  410. UINT64 CpuMemRegionBase;
  411. UINT64 CpuIoRegionBase;
  412. UINT64 PciRegionBase;
  413. UINT64 PciRegionLimit;
  414. EFI_DEVICE_PATH_PROTOCOL *DevicePath;
  415. EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io;
  416. } PCI_ROOT_BRIDGE_INSTANCE;
  417. //
  418. // Driver Instance Data Macros
  419. //
  420. #define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \
  421. CR(a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE)
  422. #define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) \
  423. CR(a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE)
  424. /**
  425. Construct the Pci Root Bridge Io protocol
  426. @param Protocol Point to protocol instance
  427. @param HostBridgeHandle Handle of host bridge
  428. @param Attri Attribute of host bridge
  429. @param ResAppeture ResourceAppeture for host bridge
  430. @retval EFI_SUCCESS Success to initialize the Pci Root Bridge.
  431. **/
  432. EFI_STATUS
  433. RootBridgeConstructor (
  434. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol,
  435. IN EFI_HANDLE HostBridgeHandle,
  436. IN UINT64 Attri,
  437. IN PCI_ROOT_BRIDGE_RESOURCE_APPETURE *ResAppeture,
  438. IN UINT32 Seg
  439. );
  440. #endif