PciHostBridge.c 58 KB

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  1. /**
  2. * Copyright (c) 2014, AppliedMicro Corp. All rights reserved.
  3. * Copyright (c) 2016, Hisilicon Limited. All rights reserved.
  4. * Copyright (c) 2016, Linaro Limited. All rights reserved.
  5. *
  6. * This program and the accompanying materials
  7. * are licensed and made available under the terms and conditions of the BSD License
  8. * which accompanies this distribution. The full text of the license may be found at
  9. * http://opensource.org/licenses/bsd-license.php
  10. *
  11. * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12. * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13. *
  14. **/
  15. #include <Uefi.h>
  16. #include <Protocol/EmbeddedGpio.h>
  17. #include <Guid/EventGroup.h>
  18. #include <Library/UefiBootServicesTableLib.h>
  19. #include <Library/UefiRuntimeServicesTableLib.h>
  20. #include <Library/OemMiscLib.h>
  21. #include "PciHostBridge.h"
  22. UINTN RootBridgeNumber[PCIE_MAX_HOSTBRIDGE] = { PCIE_MAX_ROOTBRIDGE,PCIE_MAX_ROOTBRIDGE };
  23. UINT64 RootBridgeAttribute[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
  24. { //Host Bridge0
  25. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  26. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  27. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  28. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  29. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  30. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  31. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  32. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  33. },
  34. { //Host Bridge1
  35. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  36. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  37. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  38. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  39. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  40. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  41. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  42. EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
  43. }
  44. };
  45. EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
  46. { //Host Bridge0
  47. /* Port 0 */
  48. {
  49. {
  50. {
  51. ACPI_DEVICE_PATH,
  52. ACPI_DP,
  53. {
  54. (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  55. (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  56. }
  57. },
  58. EISA_PNP_ID(0x0A03),
  59. 0
  60. },
  61. {
  62. END_DEVICE_PATH_TYPE,
  63. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  64. {
  65. END_DEVICE_PATH_LENGTH,
  66. 0
  67. }
  68. }
  69. },
  70. /* Port 1 */
  71. {
  72. {
  73. {
  74. ACPI_DEVICE_PATH,
  75. ACPI_DP,
  76. {
  77. (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  78. (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  79. }
  80. },
  81. EISA_PNP_ID(0x0A04),
  82. 0
  83. },
  84. {
  85. END_DEVICE_PATH_TYPE,
  86. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  87. {
  88. END_DEVICE_PATH_LENGTH,
  89. 0
  90. }
  91. }
  92. },
  93. /* Port 2 */
  94. {
  95. {
  96. {
  97. ACPI_DEVICE_PATH,
  98. ACPI_DP,
  99. {
  100. (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  101. (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  102. }
  103. },
  104. EISA_PNP_ID(0x0A05),
  105. 0
  106. },
  107. {
  108. END_DEVICE_PATH_TYPE,
  109. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  110. {
  111. END_DEVICE_PATH_LENGTH,
  112. 0
  113. }
  114. }
  115. },
  116. /* Port 3 */
  117. {
  118. {
  119. {
  120. ACPI_DEVICE_PATH,
  121. ACPI_DP,
  122. {
  123. (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  124. (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  125. }
  126. },
  127. EISA_PNP_ID(0x0A06),
  128. 0
  129. },
  130. {
  131. END_DEVICE_PATH_TYPE,
  132. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  133. {
  134. END_DEVICE_PATH_LENGTH,
  135. 0
  136. }
  137. }
  138. },
  139. /* Port 4 */
  140. {
  141. {
  142. {
  143. ACPI_DEVICE_PATH,
  144. ACPI_DP,
  145. {
  146. (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  147. (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  148. }
  149. },
  150. EISA_PNP_ID(0x0A07),
  151. 0
  152. },
  153. {
  154. END_DEVICE_PATH_TYPE,
  155. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  156. {
  157. END_DEVICE_PATH_LENGTH,
  158. 0
  159. }
  160. }
  161. },
  162. /* Port 5 */
  163. {
  164. {
  165. {
  166. ACPI_DEVICE_PATH,
  167. ACPI_DP,
  168. {
  169. (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  170. (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  171. }
  172. },
  173. EISA_PNP_ID(0x0A08),
  174. 0
  175. },
  176. {
  177. END_DEVICE_PATH_TYPE,
  178. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  179. {
  180. END_DEVICE_PATH_LENGTH,
  181. 0
  182. }
  183. }
  184. },
  185. /* Port 6 */
  186. {
  187. {
  188. {
  189. ACPI_DEVICE_PATH,
  190. ACPI_DP,
  191. {
  192. (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  193. (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  194. }
  195. },
  196. EISA_PNP_ID(0x0A09),
  197. 0
  198. },
  199. {
  200. END_DEVICE_PATH_TYPE,
  201. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  202. {
  203. END_DEVICE_PATH_LENGTH,
  204. 0
  205. }
  206. }
  207. },
  208. /* Port 7 */
  209. {
  210. {
  211. {
  212. ACPI_DEVICE_PATH,
  213. ACPI_DP,
  214. {
  215. (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  216. (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  217. }
  218. },
  219. EISA_PNP_ID(0x0A0A),
  220. 0
  221. },
  222. {
  223. END_DEVICE_PATH_TYPE,
  224. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  225. {
  226. END_DEVICE_PATH_LENGTH,
  227. 0
  228. }
  229. }
  230. }
  231. },
  232. { // Host Bridge1
  233. /* Port 0 */
  234. {
  235. {
  236. {
  237. ACPI_DEVICE_PATH,
  238. ACPI_DP,
  239. {
  240. (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  241. (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  242. }
  243. },
  244. EISA_PNP_ID(0x0A0B),
  245. 0
  246. },
  247. {
  248. END_DEVICE_PATH_TYPE,
  249. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  250. {
  251. END_DEVICE_PATH_LENGTH,
  252. 0
  253. }
  254. }
  255. },
  256. /* Port 1 */
  257. {
  258. {
  259. {
  260. ACPI_DEVICE_PATH,
  261. ACPI_DP,
  262. {
  263. (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  264. (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  265. }
  266. },
  267. EISA_PNP_ID(0x0A0C),
  268. 0
  269. },
  270. {
  271. END_DEVICE_PATH_TYPE,
  272. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  273. {
  274. END_DEVICE_PATH_LENGTH,
  275. 0
  276. }
  277. }
  278. },
  279. /* Port 2 */
  280. {
  281. {
  282. {
  283. ACPI_DEVICE_PATH,
  284. ACPI_DP,
  285. {
  286. (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  287. (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  288. }
  289. },
  290. EISA_PNP_ID(0x0A0D),
  291. 0
  292. },
  293. {
  294. END_DEVICE_PATH_TYPE,
  295. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  296. {
  297. END_DEVICE_PATH_LENGTH,
  298. 0
  299. }
  300. }
  301. },
  302. /* Port 3 */
  303. {
  304. {
  305. {
  306. ACPI_DEVICE_PATH,
  307. ACPI_DP,
  308. {
  309. (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  310. (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  311. }
  312. },
  313. EISA_PNP_ID(0x0A0E),
  314. 0
  315. },
  316. {
  317. END_DEVICE_PATH_TYPE,
  318. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  319. {
  320. END_DEVICE_PATH_LENGTH,
  321. 0
  322. }
  323. }
  324. },
  325. /* Port 4 */
  326. {
  327. {
  328. {
  329. ACPI_DEVICE_PATH,
  330. ACPI_DP,
  331. {
  332. (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  333. (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  334. }
  335. },
  336. EISA_PNP_ID(0x0A0F),
  337. 0
  338. },
  339. {
  340. END_DEVICE_PATH_TYPE,
  341. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  342. {
  343. END_DEVICE_PATH_LENGTH,
  344. 0
  345. }
  346. }
  347. },
  348. /* Port 5 */
  349. {
  350. {
  351. {
  352. ACPI_DEVICE_PATH,
  353. ACPI_DP,
  354. {
  355. (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  356. (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  357. }
  358. },
  359. EISA_PNP_ID(0x0A10),
  360. 0
  361. },
  362. {
  363. END_DEVICE_PATH_TYPE,
  364. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  365. {
  366. END_DEVICE_PATH_LENGTH,
  367. 0
  368. }
  369. }
  370. },
  371. /* Port 6 */
  372. {
  373. {
  374. {
  375. ACPI_DEVICE_PATH,
  376. ACPI_DP,
  377. {
  378. (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  379. (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  380. }
  381. },
  382. EISA_PNP_ID(0x0A11),
  383. 0
  384. },
  385. {
  386. END_DEVICE_PATH_TYPE,
  387. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  388. {
  389. END_DEVICE_PATH_LENGTH,
  390. 0
  391. }
  392. }
  393. },
  394. /* Port 7 */
  395. {
  396. {
  397. {
  398. ACPI_DEVICE_PATH,
  399. ACPI_DP,
  400. {
  401. (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
  402. (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
  403. }
  404. },
  405. EISA_PNP_ID(0x0A12),
  406. 0
  407. },
  408. {
  409. END_DEVICE_PATH_TYPE,
  410. END_ENTIRE_DEVICE_PATH_SUBTYPE,
  411. {
  412. END_DEVICE_PATH_LENGTH,
  413. 0
  414. }
  415. }
  416. }
  417. }
  418. };
  419. EFI_HANDLE mDriverImageHandle;
  420. PCI_HOST_BRIDGE_INSTANCE mPciHostBridgeInstanceTemplate = {
  421. PCI_HOST_BRIDGE_SIGNATURE, // Signature
  422. NULL, // HostBridgeHandle
  423. 0, // RootBridgeNumber
  424. {NULL, NULL}, // Head
  425. FALSE, // ResourceSubiteed
  426. TRUE, // CanRestarted
  427. {
  428. NotifyPhase,
  429. GetNextRootBridge,
  430. GetAttributes,
  431. StartBusEnumeration,
  432. SetBusNumbers,
  433. SubmitResources,
  434. GetProposedResources,
  435. PreprocessController
  436. }
  437. };
  438. /**
  439. Entry point of this driver
  440. @param ImageHandle Handle of driver image
  441. @param SystemTable Point to EFI_SYSTEM_TABLE
  442. @retval EFI_OUT_OF_RESOURCES Can not allocate memory resource
  443. @retval EFI_DEVICE_ERROR Can not install the protocol instance
  444. @retval EFI_SUCCESS Success to initialize the Pci host bridge.
  445. **/
  446. EFI_STATUS
  447. EFIAPI
  448. InitializePciHostBridge (
  449. IN EFI_HANDLE ImageHandle,
  450. IN EFI_SYSTEM_TABLE *SystemTable
  451. )
  452. {
  453. EFI_STATUS Status;
  454. UINTN Loop1;
  455. UINTN Loop2;
  456. PCI_HOST_BRIDGE_INSTANCE *HostBridge = NULL;
  457. PCI_ROOT_BRIDGE_INSTANCE *PrivateData;
  458. UINT32 PcieRootBridgeMask;
  459. if (!OemIsMpBoot())
  460. {
  461. PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask);
  462. }
  463. else
  464. {
  465. PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask2P);
  466. }
  467. mDriverImageHandle = ImageHandle;
  468. //
  469. // Create Host Bridge Device Handle
  470. //
  471. //Each Host Bridge have 8 Root Bridges max, every bits of 0xFF(8 bit) stands for the according PCIe Port
  472. //is enable or not
  473. for (Loop1 = 0; Loop1 < PCIE_MAX_HOSTBRIDGE; Loop1++) {
  474. if (((PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * Loop1)) & 0xFF ) == 0) {
  475. continue;
  476. }
  477. HostBridge = AllocateCopyPool (sizeof(PCI_HOST_BRIDGE_INSTANCE), &mPciHostBridgeInstanceTemplate);
  478. if (HostBridge == NULL) {
  479. return EFI_OUT_OF_RESOURCES;
  480. }
  481. HostBridge->RootBridgeNumber = RootBridgeNumber[Loop1];
  482. InitializeListHead (&HostBridge->Head);
  483. Status = gBS->InstallMultipleProtocolInterfaces (
  484. &HostBridge->HostBridgeHandle,
  485. &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc,
  486. NULL
  487. );
  488. if (EFI_ERROR (Status)) {
  489. FreePool (HostBridge);
  490. return EFI_DEVICE_ERROR;
  491. }
  492. //
  493. // Create Root Bridge Device Handle in this Host Bridge
  494. //
  495. for (Loop2 = 0; Loop2 < HostBridge->RootBridgeNumber; Loop2++) {
  496. if (!(((PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * Loop1)) >> Loop2 ) & 0x01)) {
  497. continue;
  498. }
  499. PrivateData = AllocateZeroPool (sizeof(PCI_ROOT_BRIDGE_INSTANCE));
  500. if (PrivateData == NULL) {
  501. FreePool (HostBridge);
  502. return EFI_OUT_OF_RESOURCES;
  503. }
  504. PrivateData->Port = Loop2;
  505. PrivateData->SocType = PcdGet32(Pcdsoctype);
  506. PrivateData->Signature = PCI_ROOT_BRIDGE_SIGNATURE;
  507. PrivateData->DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[Loop1][Loop2];
  508. (VOID)RootBridgeConstructor (
  509. &PrivateData->Io,
  510. HostBridge->HostBridgeHandle,
  511. RootBridgeAttribute[Loop1][Loop2],
  512. &mResAppeture[Loop1][Loop2],
  513. Loop1
  514. );
  515. Status = gBS->InstallMultipleProtocolInterfaces(
  516. &PrivateData->Handle,
  517. &gEfiDevicePathProtocolGuid, PrivateData->DevicePath,
  518. &gEfiPciRootBridgeIoProtocolGuid, &PrivateData->Io,
  519. NULL
  520. );
  521. if (EFI_ERROR (Status)) {
  522. (VOID)gBS->UninstallMultipleProtocolInterfaces (
  523. HostBridge->HostBridgeHandle,
  524. &gEfiPciHostBridgeResourceAllocationProtocolGuid, &HostBridge->ResAlloc,
  525. NULL
  526. );
  527. FreePool(PrivateData);
  528. FreePool (HostBridge);
  529. return EFI_DEVICE_ERROR;
  530. }
  531. // PCI Memory Space
  532. Status = gDS->AddMemorySpace (
  533. EfiGcdMemoryTypeMemoryMappedIo,
  534. mResAppeture[Loop1][Loop2] .MemBase,
  535. mResAppeture[Loop1][Loop2] .MemLimit -mResAppeture[Loop1][Loop2] .MemBase + 1,
  536. 0
  537. );
  538. if (EFI_ERROR (Status)) {
  539. DEBUG((EFI_D_ERROR,"PCIE AddMemorySpace Error\n"));
  540. }
  541. InsertTailList (&HostBridge->Head, &PrivateData->Link);
  542. }
  543. }
  544. return EFI_SUCCESS;
  545. }
  546. EFI_STATUS
  547. EFIAPI
  548. NotifyAllocateMemResources(
  549. IN PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance,
  550. IN PCI_RESOURCE_TYPE Index,
  551. IN OUT UINT64 *AllocatedLenMem
  552. )
  553. {
  554. EFI_PHYSICAL_ADDRESS BaseAddress;
  555. EFI_STATUS ReturnStatus;
  556. UINT64 AddrLen;
  557. UINTN BitsOfAlignment;
  558. AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
  559. PCIE_DEBUG("Addrlen:%llx\n", AddrLen);
  560. // Get the number of '1' in Alignment.
  561. BitsOfAlignment = (UINTN) (HighBitSet64 (RootBridgeInstance->ResAllocNode[Index].Alignment) + 1);
  562. BaseAddress = (RootBridgeInstance->MemBase + *AllocatedLenMem +
  563. RootBridgeInstance->ResAllocNode[Index].Alignment)
  564. & ~(RootBridgeInstance->ResAllocNode[Index].Alignment);
  565. if ((BaseAddress + AddrLen - 1) > RootBridgeInstance->MemLimit) {
  566. ReturnStatus = EFI_OUT_OF_RESOURCES;
  567. RootBridgeInstance->ResAllocNode[Index].Length = 0;
  568. return ReturnStatus;
  569. }
  570. PCIE_DEBUG("(P)Mem32/64 request memory at:%llx\n", BaseAddress);
  571. ReturnStatus = gDS->AllocateMemorySpace (
  572. EfiGcdAllocateAddress,
  573. EfiGcdMemoryTypeMemoryMappedIo,
  574. BitsOfAlignment,
  575. AddrLen,
  576. &BaseAddress,
  577. mDriverImageHandle,
  578. NULL
  579. );
  580. if (!EFI_ERROR (ReturnStatus)) {
  581. // We were able to allocate the PCI memory
  582. RootBridgeInstance->ResAllocNode[Index].Base = (UINTN)BaseAddress;
  583. RootBridgeInstance->ResAllocNode[Index].Status = ResAllocated;
  584. *AllocatedLenMem += AddrLen;
  585. PCIE_DEBUG("(P)Mem32/64 resource allocated:%llx\n", BaseAddress);
  586. } else {
  587. // Not able to allocate enough PCI memory
  588. if (ReturnStatus != EFI_OUT_OF_RESOURCES) {
  589. RootBridgeInstance->ResAllocNode[Index].Length = 0;
  590. }
  591. }
  592. return ReturnStatus;
  593. }
  594. EFI_STATUS
  595. EFIAPI
  596. NotifyAllocateResources(
  597. IN PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance
  598. )
  599. {
  600. EFI_STATUS ReturnStatus;
  601. LIST_ENTRY *List;
  602. PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
  603. PCI_RESOURCE_TYPE Index;
  604. ReturnStatus = EFI_SUCCESS;
  605. List = HostBridgeInstance->Head.ForwardLink;
  606. while (List != &HostBridgeInstance->Head) {
  607. RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
  608. UINT64 AllocatedLenMem = 0;
  609. for (Index = TypeIo; Index < TypeBus; Index++) {
  610. if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
  611. if(Index == TypeIo) {
  612. PCIE_DEBUG("NOT SUPPOER IO RESOURCES ON THIS PLATFORM\n");
  613. } else if ((Index >= TypeMem32) && (Index <= TypePMem64)) {
  614. ReturnStatus = NotifyAllocateMemResources(RootBridgeInstance,Index,&AllocatedLenMem);
  615. } else {
  616. ASSERT (FALSE);
  617. }
  618. }
  619. }
  620. List = List->ForwardLink;
  621. }
  622. return ReturnStatus;
  623. }
  624. EFI_STATUS
  625. EFIAPI
  626. NotifyFreeResources(
  627. IN PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance
  628. )
  629. {
  630. EFI_STATUS ReturnStatus;
  631. LIST_ENTRY *List;
  632. PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
  633. PCI_RESOURCE_TYPE Index;
  634. UINT64 AddrLen;
  635. EFI_PHYSICAL_ADDRESS BaseAddress;
  636. ReturnStatus = EFI_SUCCESS;
  637. List = HostBridgeInstance->Head.ForwardLink;
  638. while (List != &HostBridgeInstance->Head) {
  639. RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
  640. for (Index = TypeIo; Index < TypeBus; Index++) {
  641. if (RootBridgeInstance->ResAllocNode[Index].Status == ResAllocated) {
  642. AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
  643. BaseAddress = RootBridgeInstance->ResAllocNode[Index].Base;
  644. if(Index <= TypePMem64){
  645. ReturnStatus = gDS->FreeMemorySpace (BaseAddress, AddrLen);
  646. }else{
  647. ASSERT (FALSE);
  648. }
  649. RootBridgeInstance->ResAllocNode[Index].Type = Index;
  650. RootBridgeInstance->ResAllocNode[Index].Base = 0;
  651. RootBridgeInstance->ResAllocNode[Index].Length = 0;
  652. RootBridgeInstance->ResAllocNode[Index].Status = ResNone;
  653. }
  654. }
  655. List = List->ForwardLink;
  656. }
  657. HostBridgeInstance->ResourceSubmited = FALSE;
  658. HostBridgeInstance->CanRestarted = TRUE;
  659. return ReturnStatus;
  660. }
  661. VOID
  662. EFIAPI
  663. NotifyBeginEnumeration(
  664. IN PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance
  665. )
  666. {
  667. LIST_ENTRY *List;
  668. PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
  669. PCI_RESOURCE_TYPE Index;
  670. //
  671. // Reset the Each Root Bridge
  672. //
  673. List = HostBridgeInstance->Head.ForwardLink;
  674. while (List != &HostBridgeInstance->Head) {
  675. RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
  676. for (Index = TypeIo; Index < TypeMax; Index++) {
  677. RootBridgeInstance->ResAllocNode[Index].Type = Index;
  678. RootBridgeInstance->ResAllocNode[Index].Base = 0;
  679. RootBridgeInstance->ResAllocNode[Index].Length = 0;
  680. RootBridgeInstance->ResAllocNode[Index].Status = ResNone;
  681. }
  682. List = List->ForwardLink;
  683. }
  684. HostBridgeInstance->ResourceSubmited = FALSE;
  685. HostBridgeInstance->CanRestarted = TRUE;
  686. }
  687. /**
  688. These are the notifications from the PCI bus driver that it is about to enter a certain
  689. phase of the PCI enumeration process.
  690. This member function can be used to notify the host bridge driver to perform specific actions,
  691. including any chipset-specific initialization, so that the chipset is ready to enter the next phase.
  692. Eight notification points are defined at this time. See belows:
  693. EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertures and internal data
  694. structures. The PCI enumerator should issue this notification
  695. before starting a fresh enumeration process. Enumeration cannot
  696. be restarted after sending any other notification such as
  697. EfiPciHostBridgeBeginBusAllocation.
  698. EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about to begin. No specific action is
  699. required here. This notification can be used to perform any
  700. chipset-specific programming.
  701. EfiPciHostBridgeEndBusAllocation The bus allocation and bus programming phase is complete. No
  702. specific action is required here. This notification can be used to
  703. perform any chipset-specific programming.
  704. EfiPciHostBridgeBeginResourceAllocation
  705. The resource allocation phase is about to begin. No specific
  706. action is required here. This notification can be used to perform
  707. any chipset-specific programming.
  708. EfiPciHostBridgeAllocateResources Allocates resources per previously submitted requests for all the PCI
  709. root bridges. These resource settings are returned on the next call to
  710. GetProposedResources(). Before calling NotifyPhase() with a Phase of
  711. EfiPciHostBridgeAllocateResource, the PCI bus enumerator is responsible
  712. for gathering I/O and memory requests for
  713. all the PCI root bridges and submitting these requests using
  714. SubmitResources(). This function pads the resource amount
  715. to suit the root bridge hardware, takes care of dependencies between
  716. the PCI root bridges, and calls the Global Coherency Domain (GCD)
  717. with the allocation request. In the case of padding, the allocated range
  718. could be bigger than what was requested.
  719. EfiPciHostBridgeSetResources Programs the host bridge hardware to decode previously allocated
  720. resources (proposed resources) for all the PCI root bridges. After the
  721. hardware is programmed, reassigning resources will not be supported.
  722. The bus settings are not affected.
  723. EfiPciHostBridgeFreeResources Deallocates resources that were previously allocated for all the PCI
  724. root bridges and resets the I/O and memory apertures to their initial
  725. state. The bus settings are not affected. If the request to allocate
  726. resources fails, the PCI enumerator can use this notification to
  727. deallocate previous resources, adjust the requests, and retry
  728. allocation.
  729. EfiPciHostBridgeEndResourceAllocation The resource allocation phase is completed. No specific action is
  730. required here. This notification can be used to perform any chipsetspecific
  731. programming.
  732. @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
  733. @param[in] Phase The phase during enumeration
  734. @retval EFI_NOT_READY This phase cannot be entered at this time. For example, this error
  735. is valid for a Phase of EfiPciHostBridgeAllocateResources if
  736. SubmitResources() has not been called for one or more
  737. PCI root bridges before this call
  738. @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. This error is valid
  739. for a Phase of EfiPciHostBridgeSetResources.
  740. @retval EFI_INVALID_PARAMETER Invalid phase parameter
  741. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  742. This error is valid for a Phase of EfiPciHostBridgeAllocateResources if the
  743. previously submitted resource requests cannot be fulfilled or
  744. were only partially fulfilled.
  745. @retval EFI_SUCCESS The notification was accepted without any errors.
  746. **/
  747. EFI_STATUS
  748. EFIAPI
  749. NotifyPhase(
  750. IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
  751. IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase
  752. )
  753. {
  754. PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
  755. EFI_STATUS ReturnStatus;
  756. HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
  757. ReturnStatus = EFI_SUCCESS;
  758. switch (Phase) {
  759. case EfiPciHostBridgeBeginEnumeration:
  760. PCIE_DEBUG("Case EfiPciHostBridgeBeginEnumeration\n");
  761. if (HostBridgeInstance->CanRestarted) {
  762. NotifyBeginEnumeration(HostBridgeInstance);
  763. } else {
  764. //
  765. // Can not restart
  766. //
  767. return EFI_NOT_READY;
  768. }
  769. break;
  770. case EfiPciHostBridgeEndEnumeration:
  771. PCIE_DEBUG("Case EfiPciHostBridgeEndEnumeration\n");
  772. break;
  773. case EfiPciHostBridgeBeginBusAllocation:
  774. PCIE_DEBUG("Case EfiPciHostBridgeBeginBusAllocation\n");
  775. //
  776. // No specific action is required here, can perform any chipset specific programing
  777. //
  778. HostBridgeInstance->CanRestarted = FALSE;
  779. break;
  780. case EfiPciHostBridgeEndBusAllocation:
  781. PCIE_DEBUG("Case EfiPciHostBridgeEndBusAllocation\n");
  782. //
  783. // No specific action is required here, can perform any chipset specific programing
  784. //
  785. break;
  786. case EfiPciHostBridgeBeginResourceAllocation:
  787. PCIE_DEBUG("Case EfiPciHostBridgeBeginResourceAllocation\n");
  788. //
  789. // No specific action is required here, can perform any chipset specific programing
  790. //
  791. break;
  792. case EfiPciHostBridgeAllocateResources:
  793. PCIE_DEBUG("Case EfiPciHostBridgeAllocateResources\n");
  794. if (HostBridgeInstance->ResourceSubmited) {
  795. //
  796. // Take care of the resource dependencies between the root bridges
  797. //
  798. ReturnStatus = NotifyAllocateResources(HostBridgeInstance);
  799. } else {
  800. return EFI_NOT_READY;
  801. }
  802. //break;
  803. case EfiPciHostBridgeSetResources:
  804. PCIE_DEBUG("Case EfiPciHostBridgeSetResources\n");
  805. break;
  806. case EfiPciHostBridgeFreeResources:
  807. PCIE_DEBUG("Case EfiPciHostBridgeFreeResources\n");
  808. ReturnStatus = NotifyFreeResources(HostBridgeInstance);
  809. break;
  810. case EfiPciHostBridgeEndResourceAllocation:
  811. PCIE_DEBUG("Case EfiPciHostBridgeEndResourceAllocation\n");
  812. HostBridgeInstance->CanRestarted = FALSE;
  813. break;
  814. default:
  815. return EFI_INVALID_PARAMETER;
  816. }
  817. return ReturnStatus;
  818. }
  819. /**
  820. Return the device handle of the next PCI root bridge that is associated with this Host Bridge.
  821. This function is called multiple times to retrieve the device handles of all the PCI root bridges that
  822. are associated with this PCI host bridge. Each PCI host bridge is associated with one or more PCI
  823. root bridges. On each call, the handle that was returned by the previous call is passed into the
  824. interface, and on output the interface returns the device handle of the next PCI root bridge. The
  825. caller can use the handle to obtain the instance of the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL
  826. for that root bridge. When there are no more PCI root bridges to report, the interface returns
  827. EFI_NOT_FOUND. A PCI enumerator must enumerate the PCI root bridges in the order that they
  828. are returned by this function.
  829. For D945 implementation, there is only one root bridge in PCI host bridge.
  830. @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
  831. @param[in, out] RootBridgeHandle Returns the device handle of the next PCI root bridge.
  832. @retval EFI_SUCCESS If parameter RootBridgeHandle = NULL, then return the first Rootbridge handle of the
  833. specific Host bridge and return EFI_SUCCESS.
  834. @retval EFI_NOT_FOUND Can not find the any more root bridge in specific host bridge.
  835. @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE that was
  836. returned on a previous call to GetNextRootBridge().
  837. **/
  838. EFI_STATUS
  839. EFIAPI
  840. GetNextRootBridge(
  841. IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
  842. IN OUT EFI_HANDLE *RootBridgeHandle
  843. )
  844. {
  845. BOOLEAN NoRootBridge;
  846. LIST_ENTRY *List;
  847. PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
  848. PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
  849. NoRootBridge = TRUE;
  850. HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
  851. List = HostBridgeInstance->Head.ForwardLink;
  852. while (List != &HostBridgeInstance->Head) {
  853. NoRootBridge = FALSE;
  854. RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
  855. if (*RootBridgeHandle == NULL) {
  856. //
  857. // Return the first Root Bridge Handle of the Host Bridge
  858. //
  859. *RootBridgeHandle = RootBridgeInstance->Handle;
  860. return EFI_SUCCESS;
  861. } else {
  862. if (*RootBridgeHandle == RootBridgeInstance->Handle) {
  863. //
  864. // Get next if have
  865. //
  866. List = List->ForwardLink;
  867. if (List!=&HostBridgeInstance->Head) {
  868. RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
  869. *RootBridgeHandle = RootBridgeInstance->Handle;
  870. return EFI_SUCCESS;
  871. } else {
  872. return EFI_NOT_FOUND;
  873. }
  874. }
  875. }
  876. List = List->ForwardLink;
  877. } //end while
  878. if (NoRootBridge) {
  879. return EFI_NOT_FOUND;
  880. } else {
  881. return EFI_INVALID_PARAMETER;
  882. }
  883. }
  884. /**
  885. Returns the allocation attributes of a PCI root bridge.
  886. The function returns the allocation attributes of a specific PCI root bridge. The attributes can vary
  887. from one PCI root bridge to another. These attributes are different from the decode-related
  888. attributes that are returned by the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The
  889. RootBridgeHandle parameter is used to specify the instance of the PCI root bridge. The device
  890. handles of all the root bridges that are associated with this host bridge must be obtained by calling
  891. GetNextRootBridge(). The attributes are static in the sense that they do not change during or
  892. after the enumeration process. The hardware may provide mechanisms to change the attributes on
  893. the fly, but such changes must be completed before EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is
  894. installed. The permitted values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined in
  895. "Related Definitions" below. The caller uses these attributes to combine multiple resource requests.
  896. For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, the PCI bus enumerator needs to
  897. include requests for the prefetchable memory in the nonprefetchable memory pool and not request any
  898. prefetchable memory.
  899. Attribute Description
  900. ------------------------------------ ----------------------------------------------------------------------
  901. EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI root bridge does not support separate
  902. windows for nonprefetchable and prefetchable memory. A PCI bus
  903. driver needs to include requests for prefetchable memory in the
  904. nonprefetchable memory pool.
  905. EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI root bridge supports 64-bit memory
  906. windows. If this bit is not set, the PCI bus driver needs to include
  907. requests for a 64-bit memory address in the corresponding 32-bit
  908. memory pool.
  909. @param[in] This The instance pointer of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
  910. @param[in] RootBridgeHandle The device handle of the PCI root bridge in which the caller is interested. Type
  911. EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
  912. @param[out] Attributes The pointer to attribte of root bridge, it is output parameter
  913. @retval EFI_INVALID_PARAMETER Attribute pointer is NULL
  914. @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid.
  915. @retval EFI_SUCCESS Success to get attribute of interested root bridge.
  916. **/
  917. EFI_STATUS
  918. EFIAPI
  919. GetAttributes(
  920. IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
  921. IN EFI_HANDLE RootBridgeHandle,
  922. OUT UINT64 *Attributes
  923. )
  924. {
  925. LIST_ENTRY *List;
  926. PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
  927. PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
  928. if (Attributes == NULL) {
  929. return EFI_INVALID_PARAMETER;
  930. }
  931. HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
  932. List = HostBridgeInstance->Head.ForwardLink;
  933. while (List != &HostBridgeInstance->Head) {
  934. RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
  935. if (RootBridgeHandle == RootBridgeInstance->Handle) {
  936. *Attributes = RootBridgeInstance->RootBridgeAttrib;
  937. return EFI_SUCCESS;
  938. }
  939. List = List->ForwardLink;
  940. }
  941. //
  942. // RootBridgeHandle is not an EFI_HANDLE
  943. // that was returned on a previous call to GetNextRootBridge()
  944. //
  945. return EFI_INVALID_PARAMETER;
  946. }
  947. /**
  948. Sets up the specified PCI root bridge for the bus enumeration process.
  949. This member function sets up the root bridge for bus enumeration and returns the PCI bus range
  950. over which the search should be performed in ACPI 2.0 resource descriptor format.
  951. @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance.
  952. @param[in] RootBridgeHandle The PCI Root Bridge to be set up.
  953. @param[out] Configuration Pointer to the pointer to the PCI bus resource descriptor.
  954. @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle
  955. @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor tag.
  956. @retval EFI_SUCCESS Sucess to allocate ACPI resource descriptor.
  957. **/
  958. EFI_STATUS
  959. EFIAPI
  960. StartBusEnumeration(
  961. IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
  962. IN EFI_HANDLE RootBridgeHandle,
  963. OUT VOID **Configuration
  964. )
  965. {
  966. LIST_ENTRY *List;
  967. PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
  968. PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
  969. VOID *Buffer;
  970. UINT8 *Temp;
  971. UINT64 BusStart;
  972. UINT64 BusEnd;
  973. HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
  974. List = HostBridgeInstance->Head.ForwardLink;
  975. while (List != &HostBridgeInstance->Head) {
  976. RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
  977. if (RootBridgeHandle == RootBridgeInstance->Handle) {
  978. //
  979. // Set up the Root Bridge for Bus Enumeration
  980. //
  981. BusStart = RootBridgeInstance->BusBase;
  982. BusEnd = RootBridgeInstance->BusLimit;
  983. //
  984. // Program the Hardware(if needed) if error return EFI_DEVICE_ERROR
  985. //
  986. Buffer = AllocatePool (sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));
  987. if (Buffer == NULL) {
  988. return EFI_OUT_OF_RESOURCES;
  989. }
  990. Temp = (UINT8 *)Buffer;
  991. ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Desc = 0x8A;
  992. ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Len = 0x2B;
  993. ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->ResType = 2;
  994. ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->GenFlag = 0;
  995. ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->SpecificFlag = 0;
  996. ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrSpaceGranularity = 0;
  997. ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMin = BusStart;
  998. ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMax = 0;
  999. ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrTranslationOffset = 0;
  1000. ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrLen = BusEnd - BusStart + 1;
  1001. Temp = Temp + sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
  1002. ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;
  1003. ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;
  1004. *Configuration = Buffer;
  1005. return EFI_SUCCESS;
  1006. }
  1007. List = List->ForwardLink;
  1008. }
  1009. return EFI_INVALID_PARAMETER;
  1010. }
  1011. /**
  1012. Programs the PCI root bridge hardware so that it decodes the specified PCI bus range.
  1013. This member function programs the specified PCI root bridge to decode the bus range that is
  1014. specified by the input parameter Configuration.
  1015. The bus range information is specified in terms of the ACPI 2.0 resource descriptor format.
  1016. @param[in] This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ PROTOCOL instance
  1017. @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be programmed
  1018. @param[in] Configuration The pointer to the PCI bus resource descriptor
  1019. @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
  1020. @retval EFI_INVALID_PARAMETER Configuration is NULL.
  1021. @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.
  1022. @retval EFI_INVALID_PARAMETER Configuration does not include a valid ACPI 2.0 bus resource descriptor.
  1023. @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 resource descriptors other than
  1024. bus descriptors.
  1025. @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid ACPI resource descriptors.
  1026. @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for this root bridge.
  1027. @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this root bridge.
  1028. @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
  1029. @retval EFI_SUCCESS The bus range for the PCI root bridge was programmed.
  1030. **/
  1031. EFI_STATUS
  1032. EFIAPI
  1033. SetBusNumbers(
  1034. IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
  1035. IN EFI_HANDLE RootBridgeHandle,
  1036. IN VOID *Configuration
  1037. )
  1038. {
  1039. LIST_ENTRY *List;
  1040. PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
  1041. PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
  1042. UINT8 *Ptr;
  1043. UINTN BusStart;
  1044. UINTN BusEnd;
  1045. UINTN BusLen;
  1046. if (Configuration == NULL) {
  1047. return EFI_INVALID_PARAMETER;
  1048. }
  1049. Ptr = Configuration;
  1050. //
  1051. // Check the Configuration is valid
  1052. //
  1053. if(*Ptr != ACPI_ADDRESS_SPACE_DESCRIPTOR) {
  1054. return EFI_INVALID_PARAMETER;
  1055. }
  1056. if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->ResType != 2) {
  1057. return EFI_INVALID_PARAMETER;
  1058. }
  1059. Ptr += sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
  1060. if (*Ptr != ACPI_END_TAG_DESCRIPTOR) {
  1061. return EFI_INVALID_PARAMETER;
  1062. }
  1063. HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
  1064. List = HostBridgeInstance->Head.ForwardLink;
  1065. Ptr = Configuration;
  1066. while (List != &HostBridgeInstance->Head) {
  1067. RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
  1068. if (RootBridgeHandle == RootBridgeInstance->Handle) {
  1069. BusStart = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrRangeMin;
  1070. BusLen = (UINTN)((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->AddrLen;
  1071. BusEnd = BusStart + BusLen - 1;
  1072. if (BusStart > BusEnd) {
  1073. return EFI_INVALID_PARAMETER;
  1074. }
  1075. if ((BusStart < RootBridgeInstance->BusBase) || (BusEnd > RootBridgeInstance->BusLimit)) {
  1076. return EFI_INVALID_PARAMETER;
  1077. }
  1078. //
  1079. // Update the Bus Range
  1080. //
  1081. RootBridgeInstance->ResAllocNode[TypeBus].Base = BusStart;
  1082. RootBridgeInstance->ResAllocNode[TypeBus].Length = BusLen;
  1083. RootBridgeInstance->ResAllocNode[TypeBus].Status = ResAllocated;
  1084. //
  1085. // Program the Root Bridge Hardware
  1086. //
  1087. return EFI_SUCCESS;
  1088. }
  1089. List = List->ForwardLink;
  1090. }
  1091. return EFI_INVALID_PARAMETER;
  1092. }
  1093. VOID
  1094. EFIAPI
  1095. SubmitGetResourceType(
  1096. IN EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr,
  1097. OUT UINT64* Index
  1098. )
  1099. {
  1100. switch (Ptr->ResType) {
  1101. case 0:
  1102. if (Ptr->AddrSpaceGranularity == 32) {
  1103. if (Ptr->SpecificFlag == 0x06)
  1104. *Index = TypePMem32;
  1105. else
  1106. *Index = TypeMem32;
  1107. }
  1108. if (Ptr->AddrSpaceGranularity == 64) {
  1109. if (Ptr->SpecificFlag == 0x06)
  1110. *Index = TypePMem64;
  1111. else
  1112. *Index = TypeMem64;
  1113. }
  1114. break;
  1115. case 1:
  1116. *Index = TypeIo;
  1117. break;
  1118. default:
  1119. break;
  1120. };
  1121. }
  1122. /**
  1123. Submits the I/O and memory resource requirements for the specified PCI root bridge.
  1124. This function is used to submit all the I/O and memory resources that are required by the specified
  1125. PCI root bridge. The input parameter Configuration is used to specify the following:
  1126. - The various types of resources that are required
  1127. - The associated lengths in terms of ACPI 2.0 resource descriptor format
  1128. @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
  1129. @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory resource requirements are being submitted.
  1130. @param[in] Configuration The pointer to the PCI I/O and PCI memory resource descriptor.
  1131. @retval EFI_SUCCESS The I/O and memory resource requests for a PCI root bridge were accepted.
  1132. @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
  1133. @retval EFI_INVALID_PARAMETER Configuration is NULL.
  1134. @retval EFI_INVALID_PARAMETER Configuration does not point to a valid ACPI 2.0 resource descriptor.
  1135. @retval EFI_INVALID_PARAMETER Configuration includes requests for one or more resource types that are
  1136. not supported by this PCI root bridge. This error will happen if the caller
  1137. did not combine resources according to Attributes that were returned by
  1138. GetAllocAttributes().
  1139. @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid.
  1140. @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this PCI root bridge.
  1141. @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for this PCI root bridge.
  1142. **/
  1143. EFI_STATUS
  1144. EFIAPI
  1145. SubmitResources(
  1146. IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
  1147. IN EFI_HANDLE RootBridgeHandle,
  1148. IN VOID *Configuration
  1149. )
  1150. {
  1151. LIST_ENTRY *List;
  1152. PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
  1153. PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
  1154. UINT8 *Temp;
  1155. EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
  1156. UINT64 AddrLen;
  1157. UINT64 Alignment;
  1158. UINTN Index;
  1159. PCIE_DEBUG("In SubmitResources\n");
  1160. //
  1161. // Check the input parameter: Configuration
  1162. //
  1163. if (Configuration == NULL)
  1164. return EFI_INVALID_PARAMETER;
  1165. HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
  1166. List = HostBridgeInstance->Head.ForwardLink;
  1167. Temp = (UINT8 *)Configuration;
  1168. while ( *Temp == 0x8A)
  1169. Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ;
  1170. if (*Temp != 0x79)
  1171. return EFI_INVALID_PARAMETER;
  1172. Temp = (UINT8 *)Configuration;
  1173. while (List != &HostBridgeInstance->Head) {
  1174. RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
  1175. if (RootBridgeHandle == RootBridgeInstance->Handle) {
  1176. while ( *Temp == 0x8A) {
  1177. Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;
  1178. PCIE_DEBUG("Ptr->ResType:%d\n", Ptr->ResType);
  1179. PCIE_DEBUG("Ptr->Addrlen:%llx\n", Ptr->AddrLen);
  1180. PCIE_DEBUG("Ptr->AddrRangeMax:%llx\n", Ptr->AddrRangeMax);
  1181. PCIE_DEBUG("Ptr->AddrRangeMin:%llx\n", Ptr->AddrRangeMin);
  1182. PCIE_DEBUG("Ptr->SpecificFlag:%llx\n", Ptr->SpecificFlag);
  1183. PCIE_DEBUG("Ptr->AddrSpaceGranularity:%d\n", Ptr->AddrSpaceGranularity);
  1184. PCIE_DEBUG("RootBridgeInstance->RootBridgeAttrib:%llx\n", RootBridgeInstance->RootBridgeAttrib);
  1185. //
  1186. // Check address range alignment
  1187. //
  1188. if (Ptr->AddrRangeMax != (GetPowerOfTwo64 (Ptr->AddrRangeMax + 1) - 1)) {
  1189. return EFI_INVALID_PARAMETER;
  1190. }
  1191. Index = 0;
  1192. SubmitGetResourceType(Ptr,&Index);
  1193. AddrLen = (UINTN) Ptr->AddrLen;
  1194. Alignment = (UINTN) Ptr->AddrRangeMax;
  1195. RootBridgeInstance->ResAllocNode[Index].Length = AddrLen;
  1196. RootBridgeInstance->ResAllocNode[Index].Alignment = Alignment;
  1197. RootBridgeInstance->ResAllocNode[Index].Status = ResRequested;
  1198. HostBridgeInstance->ResourceSubmited = TRUE;
  1199. Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) ;
  1200. }
  1201. return EFI_SUCCESS;
  1202. }
  1203. List = List->ForwardLink;
  1204. }
  1205. return EFI_INVALID_PARAMETER;
  1206. }
  1207. /**
  1208. Returns the proposed resource settings for the specified PCI root bridge.
  1209. This member function returns the proposed resource settings for the specified PCI root bridge. The
  1210. proposed resource settings are prepared when NotifyPhase() is called with a Phase of
  1211. EfiPciHostBridgeAllocateResources. The output parameter Configuration
  1212. specifies the following:
  1213. - The various types of resources, excluding bus resources, that are allocated
  1214. - The associated lengths in terms of ACPI 2.0 resource descriptor format
  1215. @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
  1216. @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
  1217. @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.
  1218. @retval EFI_SUCCESS The requested parameters were returned.
  1219. @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
  1220. @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
  1221. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  1222. **/
  1223. EFI_STATUS
  1224. EFIAPI
  1225. SetResource(
  1226. PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance,
  1227. VOID *Buffer
  1228. )
  1229. {
  1230. UINTN Index;
  1231. UINT8 *Temp;
  1232. EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr;
  1233. UINT64 ResStatus;
  1234. Temp = Buffer;
  1235. for (Index = 0; Index < TypeBus; Index ++)
  1236. {
  1237. if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
  1238. Ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp ;
  1239. ResStatus = RootBridgeInstance->ResAllocNode[Index].Status;
  1240. switch (Index) {
  1241. case TypeIo:
  1242. //
  1243. // Io
  1244. //
  1245. Ptr->Desc = 0x8A;
  1246. Ptr->Len = 0x2B;
  1247. Ptr->ResType = 1;
  1248. Ptr->GenFlag = 0;
  1249. Ptr->SpecificFlag = 0;
  1250. /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
  1251. Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
  1252. (RootBridgeInstance->MemBase & 0xFFFFFFFF);
  1253. Ptr->AddrRangeMax = 0;
  1254. Ptr->AddrTranslationOffset = \
  1255. (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
  1256. Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
  1257. break;
  1258. case TypeMem32:
  1259. //
  1260. // Memory 32
  1261. //
  1262. Ptr->Desc = 0x8A;
  1263. Ptr->Len = 0x2B;
  1264. Ptr->ResType = 0;
  1265. Ptr->GenFlag = 0;
  1266. Ptr->SpecificFlag = 0;
  1267. Ptr->AddrSpaceGranularity = 32;
  1268. /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
  1269. Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
  1270. (RootBridgeInstance->MemBase & 0xFFFFFFFF);
  1271. Ptr->AddrRangeMax = 0;
  1272. Ptr->AddrTranslationOffset = \
  1273. (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
  1274. Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
  1275. break;
  1276. case TypePMem32:
  1277. //
  1278. // Prefetch memory 32
  1279. //
  1280. Ptr->Desc = 0x8A;
  1281. Ptr->Len = 0x2B;
  1282. Ptr->ResType = 0;
  1283. Ptr->GenFlag = 0;
  1284. Ptr->SpecificFlag = 6;
  1285. Ptr->AddrSpaceGranularity = 32;
  1286. /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
  1287. Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
  1288. (RootBridgeInstance->MemBase & 0xFFFFFFFF);
  1289. Ptr->AddrRangeMax = 0;
  1290. Ptr->AddrTranslationOffset = \
  1291. (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
  1292. Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
  1293. break;
  1294. case TypeMem64:
  1295. //
  1296. // Memory 64
  1297. //
  1298. Ptr->Desc = 0x8A;
  1299. Ptr->Len = 0x2B;
  1300. Ptr->ResType = 0;
  1301. Ptr->GenFlag = 0;
  1302. Ptr->SpecificFlag = 0;
  1303. Ptr->AddrSpaceGranularity = 64;
  1304. /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
  1305. Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
  1306. (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF);
  1307. Ptr->AddrRangeMax = 0;
  1308. Ptr->AddrTranslationOffset = \
  1309. (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
  1310. Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
  1311. break;
  1312. case TypePMem64:
  1313. //
  1314. // Prefetch memory 64
  1315. //
  1316. Ptr->Desc = 0x8A;
  1317. Ptr->Len = 0x2B;
  1318. Ptr->ResType = 0;
  1319. Ptr->GenFlag = 0;
  1320. Ptr->SpecificFlag = 6;
  1321. Ptr->AddrSpaceGranularity = 64;
  1322. /* This is PCIE Device Bus which start address is the low 32bit of mem base*/
  1323. Ptr->AddrRangeMin = (RootBridgeInstance->ResAllocNode[Index].Base - RootBridgeInstance->MemBase) +
  1324. (RootBridgeInstance->MemBase & 0xFFFFFFFFFFFFFFFF);
  1325. Ptr->AddrRangeMax = 0;
  1326. Ptr->AddrTranslationOffset = \
  1327. (ResStatus == ResAllocated) ? EFI_RESOURCE_SATISFIED : EFI_RESOURCE_LESS;
  1328. Ptr->AddrLen = RootBridgeInstance->ResAllocNode[Index].Length;
  1329. break;
  1330. };
  1331. PCIE_DEBUG("Ptr->ResType:%d\n", Ptr->ResType);
  1332. PCIE_DEBUG("Ptr->Addrlen:%llx\n", Ptr->AddrLen);
  1333. PCIE_DEBUG("Ptr->AddrRangeMax:%llx\n", Ptr->AddrRangeMax);
  1334. PCIE_DEBUG("Ptr->AddrRangeMin:%llx\n", Ptr->AddrRangeMin);
  1335. PCIE_DEBUG("Ptr->SpecificFlag:%llx\n", Ptr->SpecificFlag);
  1336. PCIE_DEBUG("Ptr->AddrTranslationOffset:%d\n", Ptr->AddrTranslationOffset);
  1337. PCIE_DEBUG("Ptr->AddrSpaceGranularity:%d\n", Ptr->AddrSpaceGranularity);
  1338. Temp += sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR);
  1339. }
  1340. }
  1341. ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc = 0x79;
  1342. ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum = 0x0;
  1343. return EFI_SUCCESS;
  1344. }
  1345. /**
  1346. Returns the proposed resource settings for the specified PCI root bridge.
  1347. This member function returns the proposed resource settings for the specified PCI root bridge. The
  1348. proposed resource settings are prepared when NotifyPhase() is called with a Phase of
  1349. EfiPciHostBridgeAllocateResources. The output parameter Configuration
  1350. specifies the following:
  1351. - The various types of resources, excluding bus resources, that are allocated
  1352. - The associated lengths in terms of ACPI 2.0 resource descriptor format
  1353. @param[in] This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
  1354. @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HANDLE is defined in InstallProtocolInterface() in the UEFI 2.0 Specification.
  1355. @param[out] Configuration The pointer to the pointer to the PCI I/O and memory resource descriptor.
  1356. @retval EFI_SUCCESS The requested parameters were returned.
  1357. @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
  1358. @retval EFI_DEVICE_ERROR Programming failed due to a hardware error.
  1359. @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
  1360. **/
  1361. EFI_STATUS
  1362. EFIAPI
  1363. GetProposedResources(
  1364. IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
  1365. IN EFI_HANDLE RootBridgeHandle,
  1366. OUT VOID **Configuration
  1367. )
  1368. {
  1369. LIST_ENTRY *List;
  1370. PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
  1371. PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
  1372. UINTN Index;
  1373. UINTN Number;
  1374. VOID *Buffer;
  1375. Buffer = NULL;
  1376. Number = 0;
  1377. PCIE_DEBUG("In GetProposedResources\n");
  1378. //
  1379. // Get the Host Bridge Instance from the resource allocation protocol
  1380. //
  1381. HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
  1382. List = HostBridgeInstance->Head.ForwardLink;
  1383. //
  1384. // Enumerate the root bridges in this host bridge
  1385. //
  1386. while (List != &HostBridgeInstance->Head) {
  1387. RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
  1388. if (RootBridgeHandle == RootBridgeInstance->Handle) {
  1389. for (Index = 0; Index < TypeBus; Index ++) {
  1390. if (RootBridgeInstance->ResAllocNode[Index].Status != ResNone) {
  1391. Number ++;
  1392. }
  1393. }
  1394. Buffer = AllocateZeroPool (Number * sizeof(EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + sizeof(EFI_ACPI_END_TAG_DESCRIPTOR));
  1395. if (Buffer == NULL) {
  1396. return EFI_OUT_OF_RESOURCES;
  1397. }
  1398. (VOID)SetResource(RootBridgeInstance,Buffer);
  1399. *Configuration = Buffer;
  1400. return EFI_SUCCESS;
  1401. }
  1402. List = List->ForwardLink;
  1403. }
  1404. return EFI_INVALID_PARAMETER;
  1405. }
  1406. /**
  1407. Provides the hooks from the PCI bus driver to every PCI controller (device/function) at various
  1408. stages of the PCI enumeration process that allow the host bridge driver to preinitialize individual
  1409. PCI controllers before enumeration.
  1410. This function is called during the PCI enumeration process. No specific action is expected from this
  1411. member function. It allows the host bridge driver to preinitialize individual PCI controllers before
  1412. enumeration.
  1413. @param This Pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL instance.
  1414. @param RootBridgeHandle The associated PCI root bridge handle. Type EFI_HANDLE is defined in
  1415. InstallProtocolInterface() in the UEFI 2.0 Specification.
  1416. @param PciAddress The address of the PCI device on the PCI bus. This address can be passed to the
  1417. EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member functions to access the PCI
  1418. configuration space of the device. See Table 12-1 in the UEFI 2.0 Specification for
  1419. the definition of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS.
  1420. @param Phase The phase of the PCI device enumeration.
  1421. @retval EFI_SUCCESS The requested parameters were returned.
  1422. @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bridge handle.
  1423. @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defined in
  1424. EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE.
  1425. @retval EFI_DEVICE_ERROR Programming failed due to a hardware error. The PCI enumerator should
  1426. not enumerate this device, including its child devices if it is a PCI-to-PCI
  1427. bridge.
  1428. **/
  1429. EFI_STATUS
  1430. EFIAPI
  1431. PreprocessController (
  1432. IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This,
  1433. IN EFI_HANDLE RootBridgeHandle,
  1434. IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress,
  1435. IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase
  1436. )
  1437. {
  1438. PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance;
  1439. PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance;
  1440. LIST_ENTRY *List;
  1441. HostBridgeInstance = INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This);
  1442. List = HostBridgeInstance->Head.ForwardLink;
  1443. //
  1444. // Enumerate the root bridges in this host bridge
  1445. //
  1446. while (List != &HostBridgeInstance->Head) {
  1447. RootBridgeInstance = DRIVER_INSTANCE_FROM_LIST_ENTRY (List);
  1448. if (RootBridgeHandle == RootBridgeInstance->Handle) {
  1449. break;
  1450. }
  1451. List = List->ForwardLink;
  1452. }
  1453. if (List == &HostBridgeInstance->Head) {
  1454. return EFI_INVALID_PARAMETER;
  1455. }
  1456. if ((UINT32)Phase > EfiPciBeforeResourceCollection) {
  1457. return EFI_INVALID_PARAMETER;
  1458. }
  1459. return EFI_SUCCESS;
  1460. }