PlatformPciLib.c 12 KB

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  1. /** @file
  2. Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
  3. Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
  4. This program and the accompanying materials
  5. are licensed and made available under the terms and conditions of the BSD License
  6. which accompanies this distribution. The full text of the license may be found at
  7. http://opensource.org/licenses/bsd-license.php
  8. THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  9. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  10. **/
  11. #include <Library/PcdLib.h>
  12. #include <Library/PlatformPciLib.h>
  13. UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0x8a0000000,0x8a0000000,0x8a0000000,0x8a0000000},
  14. {0x600a0000000,0x600a0000000,0x600a0000000,0x600a0000000, 0x700a0000000,0x700a0000000,0x700a0000000,0x700a0000000}};
  15. UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000, 0x8a0090000, 0x8a0200000, 0x8a00a0000, 0x8a00b0000},
  16. {0x600a0090000, 0x600a0200000, 0x600a00a0000, 0x600a00b0000, 0x700a0090000, 0x700a0200000, 0x700a00a0000, 0x700a00b0000}};
  17. UINT64 PCIE_PHY_BASE_1610 [PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000, 0x8a00c0000, 0x8a00d0000, 0x8a00e0000, 0x8a00f0000},
  18. {0x600a00c0000, 0x600a00d0000, 0x600a00e0000, 0x600a00f0000, 0x700a00c0000, 0x700a00d0000, 0x700a00e0000, 0x700a00f0000}};
  19. UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040, 0x8c6010040},
  20. {0x400C6010040, 0x400C6010040, 0x400C6010040, 0x400C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040, 0x408C6010040}};
  21. PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
  22. {// HostBridge 0
  23. /* Port 0 */
  24. {
  25. PCI_HB0RB0_ECAM_BASE, //ecam
  26. 0x80, //BusBase
  27. 0x87, //BusLimit
  28. PCI_HB0RB0_PCIREGION_BASE, //Membase
  29. PCI_HB0RB0_CPUMEMREGIONBASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //Memlimit
  30. PCI_HB0RB0_IO_BASE, //IoBase
  31. (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
  32. PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
  33. PCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase
  34. (PCI_HB0RB0_PCI_BASE),//RbPciBar
  35. PCI_HB0RB0_PCIREGION_BASE, //PciRegionbase
  36. PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1 //PciRegionlimit
  37. },
  38. /* Port 1 */
  39. {
  40. PCI_HB0RB1_ECAM_BASE,//ecam
  41. 0x90, //BusBase
  42. 0x97, //BusLimit
  43. PCI_HB0RB1_PCIREGION_BASE, //Membase
  44. PCI_HB0RB1_CPUMEMREGIONBASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit
  45. (PCI_HB0RB1_IO_BASE), //IoBase
  46. (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit
  47. PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
  48. PCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase
  49. (PCI_HB0RB1_PCI_BASE), //RbPciBar
  50. PCI_HB0RB1_PCIREGION_BASE, //PciRegionbase
  51. PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1 //PciRegionlimit
  52. },
  53. /* Port 2 */
  54. {
  55. PCI_HB0RB2_ECAM_BASE,
  56. 0x80, //BusBase
  57. 0x87, //BusLimit
  58. PCI_HB0RB2_CPUMEMREGIONBASE ,//MemBase
  59. PCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit
  60. (PCI_HB0RB2_IO_BASE), //IOBase
  61. (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit
  62. PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
  63. PCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase
  64. (PCI_HB0RB2_PCI_BASE), //RbPciBar
  65. PCI_HB0RB2_PCIREGION_BASE, //PciRegionbase
  66. PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1 //PciRegionlimit
  67. },
  68. /* Port 3 */
  69. {
  70. PCI_HB0RB3_ECAM_BASE,
  71. 0xb0, //BusBase
  72. 0xb7, //BusLimit
  73. (PCI_HB0RB3_ECAM_BASE), //MemBase
  74. (PCI_HB0RB3_CPUMEMREGIONBASE + PCI_HB0RB3_PCIREGION_SIZE - 1), //MemLimit
  75. (PCI_HB0RB3_IO_BASE), //IoBase
  76. (PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB3_IO_SIZE - 1), //IoLimit
  77. PCI_HB0RB3_CPUMEMREGIONBASE,
  78. PCI_HB0RB3_CPUIOREGIONBASE,
  79. (PCI_HB0RB3_PCI_BASE), //RbPciBar
  80. PCI_HB0RB3_PCIREGION_BASE, //PciRegionbase
  81. PCI_HB0RB3_PCIREGION_BASE + PCI_HB0RB3_PCIREGION_SIZE - 1 //PciRegionlimit
  82. },
  83. /* Port 4 */
  84. {
  85. PCI_HB0RB4_ECAM_BASE, //ecam
  86. 0x88, //BusBase
  87. 0x8f, //BusLimit
  88. PCI_HB0RB4_CPUMEMREGIONBASE, //Membase
  89. PCI_HB0RB4_CPUMEMREGIONBASE + PCI_HB0RB4_PCIREGION_SIZE - 1, //Memlimit
  90. PCI_HB0RB4_IO_BASE, //IoBase
  91. (PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB4_IO_SIZE - 1), //IoLimit
  92. PCI_HB0RB4_CPUMEMREGIONBASE, //CpuMemRegionBase
  93. PCI_HB0RB4_CPUIOREGIONBASE, //CpuIoRegionBase
  94. (PCI_HB0RB4_PCI_BASE), //RbPciBar
  95. PCI_HB0RB4_PCIREGION_BASE, //PciRegionbase
  96. PCI_HB0RB4_PCIREGION_BASE + PCI_HB0RB4_PCIREGION_SIZE - 1 //PciRegionlimit
  97. },
  98. /* Port 5 */
  99. {
  100. PCI_HB0RB5_ECAM_BASE,//ecam
  101. 0x0, //BusBase
  102. 0x7, //BusLimit
  103. PCI_HB0RB5_CPUMEMREGIONBASE, //Membase
  104. PCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit
  105. (PCI_HB0RB5_IO_BASE), //IoBase
  106. (PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB5_IO_SIZE - 1), //IoLimit
  107. PCI_HB0RB5_CPUMEMREGIONBASE, //CpuMemRegionBase
  108. PCI_HB0RB5_CPUIOREGIONBASE, //CpuIoRegionBase
  109. (PCI_HB0RB5_PCI_BASE), //RbPciBar
  110. PCI_HB0RB5_PCIREGION_BASE, //PciRegionbase
  111. PCI_HB0RB5_PCIREGION_BASE + PCI_HB0RB5_PCIREGION_SIZE - 1 //PciRegionlimit
  112. },
  113. /* Port 6 */
  114. {
  115. PCI_HB0RB6_ECAM_BASE,
  116. 0xC0, //BusBase
  117. 0xC7, //BusLimit
  118. PCI_HB0RB6_PCIREGION_BASE ,//MemBase
  119. PCI_HB0RB6_CPUMEMREGIONBASE + PCI_HB0RB6_PCIREGION_SIZE - 1, //MemLimit
  120. (PCI_HB0RB6_IO_BASE), //IOBase
  121. (PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB6_IO_SIZE - 1), //IoLimit
  122. PCI_HB0RB6_CPUMEMREGIONBASE, //CpuMemRegionBase
  123. PCI_HB0RB6_CPUIOREGIONBASE, //CpuIoRegionBase
  124. (PCI_HB0RB6_PCI_BASE), //RbPciBar
  125. PCI_HB0RB6_PCIREGION_BASE, //PciRegionbase
  126. PCI_HB0RB6_PCIREGION_BASE + PCI_HB0RB6_PCIREGION_SIZE - 1 //PciRegionlimit
  127. },
  128. /* Port 7 */
  129. {
  130. PCI_HB0RB7_ECAM_BASE,
  131. 0x90, //BusBase
  132. 0x97, //BusLimit
  133. PCI_HB0RB7_CPUMEMREGIONBASE, //MemBase
  134. PCI_HB0RB7_CPUMEMREGIONBASE + PCI_HB0RB7_PCIREGION_SIZE - 1, //MemLimit
  135. (PCI_HB0RB7_IO_BASE), //IoBase
  136. (PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB7_IO_SIZE - 1), //IoLimit
  137. PCI_HB0RB7_CPUMEMREGIONBASE,
  138. PCI_HB0RB7_CPUIOREGIONBASE,
  139. (PCI_HB0RB7_PCI_BASE), //RbPciBar
  140. PCI_HB0RB7_PCIREGION_BASE, //PciRegionbase
  141. PCI_HB0RB7_PCIREGION_BASE + PCI_HB0RB7_PCIREGION_SIZE - 1 //PciRegionlimit
  142. }
  143. },
  144. {// HostBridge 1
  145. /* Port 0 */
  146. {
  147. PCI_HB1RB0_ECAM_BASE,
  148. 0x80, //BusBase
  149. 0x87, //BusLimit
  150. (PCI_HB1RB0_ECAM_BASE), //MemBase
  151. (PCI_HB1RB0_CPUMEMREGIONBASE + PCI_HB1RB0_PCIREGION_SIZE - 1), //MemLimit
  152. PCI_HB1RB0_IO_BASE, //IoBase
  153. (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
  154. PCI_HB1RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
  155. PCI_HB1RB0_CPUIOREGIONBASE, //CpuIoRegionBase
  156. (PCI_HB1RB0_PCI_BASE), //RbPciBar
  157. PCI_HB1RB0_PCIREGION_BASE, //PciRegionbase
  158. PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit
  159. },
  160. /* Port 1 */
  161. {
  162. PCI_HB1RB1_ECAM_BASE,
  163. 0x90, //BusBase
  164. 0x97, //BusLimit
  165. (PCI_HB1RB1_ECAM_BASE), //MemBase
  166. (PCI_HB1RB1_CPUMEMREGIONBASE + PCI_HB1RB1_PCIREGION_SIZE - 1), //MemLimit
  167. PCI_HB1RB1_IO_BASE, //IoBase
  168. (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
  169. PCI_HB1RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
  170. PCI_HB1RB1_CPUIOREGIONBASE, //CpuIoRegionBase
  171. (PCI_HB1RB1_PCI_BASE), //RbPciBar
  172. PCI_HB1RB1_PCIREGION_BASE, //PciRegionbase
  173. PCI_HB1RB1_PCIREGION_BASE + PCI_HB1RB1_PCIREGION_SIZE - 1 //PciRegionlimit
  174. },
  175. /* Port 2 */
  176. {
  177. PCI_HB1RB2_ECAM_BASE,
  178. 0x10, //BusBase
  179. 0x1f, //BusLimit
  180. PCI_HB1RB2_CPUMEMREGIONBASE, //MemBase
  181. PCI_HB1RB2_CPUMEMREGIONBASE + PCI_HB1RB2_PCIREGION_SIZE - 1, //MemLimit
  182. PCI_HB1RB2_IO_BASE, //IoBase
  183. (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
  184. PCI_HB1RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
  185. PCI_HB1RB2_CPUIOREGIONBASE, //CpuIoRegionBase
  186. (PCI_HB1RB2_PCI_BASE), //RbPciBar
  187. PCI_HB1RB2_PCIREGION_BASE, //PciRegionbase
  188. PCI_HB1RB2_PCIREGION_BASE + PCI_HB1RB2_PCIREGION_SIZE - 1 //PciRegionlimit
  189. },
  190. /* Port 3 */
  191. {
  192. PCI_HB1RB3_ECAM_BASE,
  193. 0xb0, //BusBase
  194. 0xb7, //BusLimit
  195. (PCI_HB1RB3_ECAM_BASE), //MemBase
  196. (PCI_HB1RB3_CPUMEMREGIONBASE + PCI_HB1RB3_PCIREGION_SIZE - 1), //MemLimit
  197. PCI_HB1RB3_IO_BASE, //IoBase
  198. (PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
  199. PCI_HB1RB3_CPUMEMREGIONBASE, //CpuMemRegionBase
  200. PCI_HB1RB3_CPUIOREGIONBASE, //CpuIoRegionBase
  201. (PCI_HB1RB3_PCI_BASE), //RbPciBar
  202. PCI_HB1RB3_PCIREGION_BASE, //PciRegionbase
  203. PCI_HB1RB3_PCIREGION_BASE + PCI_HB1RB3_PCIREGION_SIZE - 1 //PciRegionlimit
  204. },
  205. /* Port 4 */
  206. {
  207. PCI_HB1RB4_ECAM_BASE,
  208. 0x20, //BusBase
  209. 0x2f, //BusLimit
  210. PCI_HB1RB4_CPUMEMREGIONBASE, //MemBase
  211. PCI_HB1RB4_CPUMEMREGIONBASE + PCI_HB1RB4_PCIREGION_SIZE - 1, //MemLimit
  212. PCI_HB1RB4_IO_BASE, //IoBase
  213. (PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
  214. PCI_HB1RB4_CPUMEMREGIONBASE, //CpuMemRegionBase
  215. PCI_HB1RB4_CPUIOREGIONBASE, //CpuIoRegionBase
  216. (PCI_HB1RB4_PCI_BASE), //RbPciBar
  217. PCI_HB1RB4_PCIREGION_BASE, //PciRegionbase
  218. PCI_HB1RB4_PCIREGION_BASE + PCI_HB1RB4_PCIREGION_SIZE - 1 //PciRegionlimit
  219. },
  220. /* Port 5 */
  221. {
  222. PCI_HB1RB5_ECAM_BASE,
  223. 0x30, //BusBase
  224. 0x3f, //BusLimit
  225. PCI_HB1RB5_CPUMEMREGIONBASE, //MemBase
  226. PCI_HB1RB5_CPUMEMREGIONBASE + PCI_HB1RB5_PCIREGION_SIZE - 1, //MemLimit
  227. PCI_HB1RB5_IO_BASE, //IoBase
  228. (PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
  229. PCI_HB1RB5_CPUMEMREGIONBASE, //CpuMemRegionBase
  230. PCI_HB1RB5_CPUIOREGIONBASE, //CpuIoRegionBase
  231. (PCI_HB1RB5_PCI_BASE), //RbPciBar
  232. PCI_HB1RB5_PCIREGION_BASE, //PciRegionbase
  233. PCI_HB1RB5_PCIREGION_BASE + PCI_HB1RB5_PCIREGION_SIZE - 1 //PciRegionlimit
  234. },
  235. /* Port 6 */
  236. {
  237. PCI_HB1RB6_ECAM_BASE,
  238. 0xa8, //BusBase
  239. 0xaf, //BusLimit
  240. (PCI_HB1RB6_ECAM_BASE), //MemBase
  241. PCI_HB1RB6_CPUMEMREGIONBASE + PCI_HB1RB6_PCIREGION_SIZE - 1, //MemLimit
  242. PCI_HB1RB6_IO_BASE, //IoBase
  243. (PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
  244. PCI_HB1RB6_CPUMEMREGIONBASE, //CpuMemRegionBase
  245. PCI_HB1RB6_CPUIOREGIONBASE, //CpuIoRegionBase
  246. (PCI_HB1RB6_PCI_BASE), //RbPciBar
  247. PCI_HB1RB6_PCIREGION_BASE, //PciRegionbase
  248. PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit
  249. },
  250. /* Port 7 */
  251. {
  252. PCI_HB1RB7_ECAM_BASE,
  253. 0xb8, //BusBase
  254. 0xbf, //BusLimit
  255. (PCI_HB1RB7_ECAM_BASE), //MemBase
  256. PCI_HB1RB7_CPUMEMREGIONBASE + PCI_HB1RB7_PCIREGION_SIZE - 1, //MemLimit
  257. PCI_HB1RB7_IO_BASE, //IoBase
  258. (PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
  259. PCI_HB1RB7_CPUMEMREGIONBASE, //CpuMemRegionBase
  260. PCI_HB1RB7_CPUIOREGIONBASE, //CpuIoRegionBase
  261. (PCI_HB1RB7_PCI_BASE), //RbPciBar
  262. PCI_HB1RB7_PCIREGION_BASE, //PciRegionbase
  263. PCI_HB1RB7_PCIREGION_BASE + PCI_HB1RB7_PCIREGION_SIZE - 1 //PciRegionlimit
  264. }
  265. }
  266. };