PlatformPciLib.c 5.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156
  1. /** @file
  2. Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
  3. Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
  4. This program and the accompanying materials
  5. are licensed and made available under the terms and conditions of the BSD License
  6. which accompanies this distribution. The full text of the license may be found at
  7. http://opensource.org/licenses/bsd-license.php
  8. THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  9. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  10. **/
  11. #include <Library/PcdLib.h>
  12. #include <Library/PlatformPciLib.h>
  13. UINT64 pcie_subctrl_base_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0000000, 0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000,0xa0000000},
  14. {0xb0000000,0xb0000000,0xb0000000,0xb0000000, 0xb0000000,0xb0000000,0xb0000000,0xb0000000}};
  15. UINT64 PCIE_APB_SLAVE_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa0090000, 0xa0200000, 0xa00a0000, 0xa00b0000},
  16. {0xb0090000, 0xb0200000, 0xb00a0000, 0xb00b0000}};
  17. UINT64 PCIE_PHY_BASE_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xa00c0000, 0xa00d0000, 0xa00e0000, 0xa00f0000},
  18. {0xb00c0000,0xb00d0000, 0xb00e0000, 0xb00f0000}};
  19. UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {{0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040},
  20. {0xc6010040, 0xc6010040, 0xc6010040, 0xc6010040}};
  21. PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
  22. {// HostBridge 0
  23. /* Port 0 */
  24. {
  25. PCI_HB0RB0_ECAM_BASE, //ecam
  26. 0, //BusBase
  27. 31, //BusLimit
  28. PCI_HB0RB0_PCIREGION_BASE, //Membase
  29. PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //Memlimit
  30. PCI_HB0RB0_IO_BASE, //IoBase
  31. (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
  32. PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
  33. PCI_HB0RB0_CPUIOREGIONBASE, //CpuIoRegionBase
  34. (PCI_HB0RB0_PCI_BASE), //RbPciBar
  35. PCI_HB0RB0_PCIREGION_BASE, //PciRegionBase
  36. PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //PciRegionLimit
  37. },
  38. /* Port 1 */
  39. {
  40. PCI_HB0RB1_ECAM_BASE,//ecam
  41. 224, //BusBase
  42. 254, //BusLimit
  43. PCI_HB0RB1_PCIREGION_BASE, //Membase
  44. PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit
  45. (PCI_HB0RB1_IO_BASE), //IoBase
  46. (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit
  47. PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
  48. PCI_HB0RB1_CPUIOREGIONBASE, //CpuIoRegionBase
  49. (PCI_HB0RB1_PCI_BASE), //RbPciBar
  50. PCI_HB0RB1_PCIREGION_BASE, //PciRegionBase
  51. PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //PciRegionLimit
  52. },
  53. /* Port 2 */
  54. {
  55. PCI_HB0RB2_ECAM_BASE,
  56. 128, //BusBase
  57. 159, //BusLimit
  58. PCI_HB0RB2_PCIREGION_BASE ,//MemBase
  59. PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit
  60. (PCI_HB0RB2_IO_BASE), //IOBase
  61. (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit
  62. PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
  63. PCI_HB0RB2_CPUIOREGIONBASE, //CpuIoRegionBase
  64. (PCI_HB0RB2_PCI_BASE), //RbPciBar
  65. PCI_HB0RB2_PCIREGION_BASE, //PciRegionBase
  66. PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //PciRegionLimit
  67. },
  68. /* Port 3 */
  69. {
  70. PCI_HB0RB3_ECAM_BASE,
  71. 96, //BusBase
  72. 127, //BusLimit
  73. (PCI_HB0RB3_ECAM_BASE), //MemBase
  74. (PCI_HB0RB3_ECAM_BASE + PCI_HB0RB3_ECAM_SIZE - 1), //MemLimit
  75. (0), //IoBase
  76. (0), //IoLimit
  77. 0,
  78. 0,
  79. (PCI_HB0RB3_PCI_BASE), //RbPciBar
  80. 0,
  81. 0
  82. }
  83. },
  84. {// HostBridge 1
  85. /* Port 0 */
  86. {
  87. PCI_HB1RB0_ECAM_BASE,
  88. 128, //BusBase
  89. 159, //BusLimit
  90. (PCI_HB1RB0_ECAM_BASE), //MemBase
  91. (PCI_HB1RB0_ECAM_BASE + PCI_HB1RB0_ECAM_SIZE - 1), //MemLimit
  92. (0), //IoBase
  93. (0), //IoLimit
  94. 0,
  95. 0,
  96. (PCI_HB1RB0_PCI_BASE), //RbPciBar
  97. 0,
  98. 0
  99. },
  100. /* Port 1 */
  101. {
  102. PCI_HB1RB1_ECAM_BASE,
  103. 160, //BusBase
  104. 191, //BusLimit
  105. (PCI_HB1RB1_ECAM_BASE), //MemBase
  106. (PCI_HB1RB1_ECAM_BASE + PCI_HB1RB1_ECAM_SIZE - 1), //MemLimit
  107. (0), //IoBase
  108. (0), //IoLimit
  109. 0,
  110. 0,
  111. (PCI_HB1RB1_PCI_BASE), //RbPciBar
  112. 0,
  113. 0
  114. },
  115. /* Port 2 */
  116. {
  117. PCI_HB1RB2_ECAM_BASE,
  118. 192, //BusBase
  119. 223, //BusLimit
  120. (PCI_HB1RB2_ECAM_BASE), //MemBase
  121. (PCI_HB1RB2_ECAM_BASE + PCI_HB1RB2_ECAM_SIZE - 1), //MemLimit
  122. (0), //IoBase
  123. (0), //IoLimit
  124. 0,
  125. 0,
  126. (PCI_HB1RB2_PCI_BASE), //RbPciBar
  127. 0,
  128. 0
  129. },
  130. /* Port 3 */
  131. {
  132. PCI_HB1RB3_ECAM_BASE,
  133. 224, //BusBase
  134. 255, //BusLimit
  135. (PCI_HB1RB3_ECAM_BASE), //MemBase
  136. (PCI_HB1RB3_ECAM_BASE + PCI_HB1RB3_ECAM_SIZE - 1), //MemLimit
  137. (0), //IoBase
  138. (0), //IoLimit
  139. 0,
  140. 0,
  141. (PCI_HB1RB3_PCI_BASE), //RbPciBar
  142. 0,
  143. 0
  144. }
  145. }
  146. };