EarlyConfigPeimD03.c 9.0 KB

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  1. /** @file
  2. *
  3. * Copyright (c) 2016, Hisilicon Limited. All rights reserved.
  4. * Copyright (c) 2016, Linaro Limited. All rights reserved.
  5. *
  6. * This program and the accompanying materials
  7. * are licensed and made available under the terms and conditions of the BSD License
  8. * which accompanies this distribution. The full text of the license may be found at
  9. * http://opensource.org/licenses/bsd-license.php
  10. *
  11. * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  12. * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  13. *
  14. **/
  15. #include <Uefi.h>
  16. #include <PiPei.h>
  17. #include <Library/DebugLib.h>
  18. #include <Library/PcdLib.h>
  19. #include <Library/IoLib.h>
  20. #include <Library/CacheMaintenanceLib.h>
  21. #include <PlatformArch.h>
  22. #include <Library/PlatformSysCtrlLib.h>
  23. #include <Library/OemMiscLib.h>
  24. #include <Library/OemAddressMapLib.h>
  25. #include <Library/ArmLib.h>
  26. #define PERI_SUBCTRL_BASE (0x40000000)
  27. #define MDIO_SUBCTRL_BASE (0x60000000)
  28. #define PCIE2_SUBCTRL_BASE (0xA0000000)
  29. #define PCIE0_SUBCTRL_BASE (0xB0000000)
  30. #define ALG_BASE (0xD0000000)
  31. #define SC_BROADCAST_EN_REG (0x16220)
  32. #define SC_BROADCAST_SCL1_ADDR0_REG (0x16230)
  33. #define SC_BROADCAST_SCL1_ADDR1_REG (0x16234)
  34. #define SC_BROADCAST_SCL2_ADDR0_REG (0x16238)
  35. #define SC_BROADCAST_SCL2_ADDR1_REG (0x1623C)
  36. #define SC_BROADCAST_SCL3_ADDR0_REG (0x16240)
  37. #define SC_BROADCAST_SCL3_ADDR1_REG (0x16244)
  38. #define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG (0x1000)
  39. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG (0x1010)
  40. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG (0x1014)
  41. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG (0x1018)
  42. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG (0x101C)
  43. #define PCIE_SUBCTRL_SC_REMAP_CTRL_REG (0x1200)
  44. #define SC_ITS_M3_INT_MUX_SEL_REG (0x21F0)
  45. #define SC_TM_CLKEN0_REG (0x2050)
  46. #define SC_TM_CLKEN0_REG_VALUE (0x3)
  47. #define SC_BROADCAST_EN_REG_VALUE (0x7)
  48. #define SC_BROADCAST_SCLx_ADDRx_REG_VALUE0 (0x0)
  49. #define SC_BROADCAST_SCLx_ADDRx_REG_VALUE1 (0x40016260)
  50. #define SC_BROADCAST_SCLx_ADDRx_REG_VALUE2 (0x60016260)
  51. #define SC_BROADCAST_SCLx_ADDRx_REG_VALUE3 (0x400)
  52. #define SC_ITS_M3_INT_MUX_SEL_REG_VALUE (0x7)
  53. #define PCIE_SUBCTRL_SC_REMAP_CTRL_REG_VALUE0 (0x0)
  54. #define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE0 (0x27)
  55. #define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE1 (0x2F)
  56. #define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE2 (0x77)
  57. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG_VALUE0 (0x178033)
  58. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG_VALUE0 (0x17003c)
  59. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0 (0x15003d)
  60. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE1 (0x170035)
  61. #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG_VALUE0 (0x16003e)
  62. VOID PlatformTimerStart (VOID)
  63. {
  64. // Timer0 clock enable
  65. MmioWrite32 (PERI_SUBCTRL_BASE + SC_TM_CLKEN0_REG, SC_TM_CLKEN0_REG_VALUE);
  66. }
  67. void QResetAp(VOID)
  68. {
  69. MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0);
  70. (void)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8);
  71. ArmDataSynchronizationBarrier ();
  72. ArmInstructionSynchronizationBarrier ();
  73. //SCCL A
  74. if (!PcdGet64 (PcdTrustedFirmwareEnable))
  75. {
  76. StartupAp();
  77. }
  78. }
  79. EFI_STATUS
  80. EFIAPI
  81. EarlyConfigEntry (
  82. IN EFI_PEI_FILE_HANDLE FileHandle,
  83. IN CONST EFI_PEI_SERVICES **PeiServices
  84. )
  85. {
  86. DEBUG((EFI_D_INFO,"SMMU CONFIG........."));
  87. (VOID)SmmuConfigForOS();
  88. DEBUG((EFI_D_INFO,"Done\n"));
  89. DEBUG((EFI_D_INFO,"AP CONFIG........."));
  90. (VOID)QResetAp();
  91. DEBUG((EFI_D_INFO,"Done\n"));
  92. DEBUG((EFI_D_INFO,"MN CONFIG........."));
  93. (VOID)MN_CONFIG();
  94. DEBUG((EFI_D_INFO,"Done\n"));
  95. if(OemIsMpBoot())
  96. {
  97. DEBUG((EFI_D_INFO,"Event Broadcast CONFIG........."));
  98. //EVENT broadcast
  99. MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
  100. MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
  101. MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
  102. MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
  103. MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
  104. MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
  105. MmioWrite32 (MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
  106. MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
  107. MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
  108. MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
  109. MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
  110. MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
  111. MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
  112. MmioWrite32 (PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
  113. MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
  114. MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
  115. MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
  116. MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
  117. MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
  118. MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
  119. MmioWrite32 (S1_BASE + MDIO_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
  120. MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_EN_REG, SC_BROADCAST_EN_REG_VALUE);
  121. MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
  122. MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL1_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
  123. MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE2);
  124. MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL2_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE3);
  125. MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR0_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE1);
  126. MmioWrite32 (S1_BASE + PERI_SUBCTRL_BASE + SC_BROADCAST_SCL3_ADDR1_REG, SC_BROADCAST_SCLx_ADDRx_REG_VALUE0);
  127. DEBUG((EFI_D_INFO,"Done\n"));
  128. }
  129. DEBUG((EFI_D_INFO,"PCIE RAM Address CONFIG........."));
  130. if(OemIsMpBoot())
  131. {
  132. MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE0);
  133. MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0);
  134. MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE1);
  135. MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG_VALUE0);
  136. MmioWrite32 (PCIE0_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE1);
  137. }
  138. else
  139. {
  140. MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_REMAP_CTRL_REG, PCIE_SUBCTRL_SC_REMAP_CTRL_REG_VALUE0);
  141. MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISP_DAW_EN_REG, PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE2);
  142. MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG_VALUE0);
  143. MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0);
  144. MmioWrite32 (PCIE2_SUBCTRL_BASE + PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG, PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG_VALUE0);
  145. }
  146. DEBUG((EFI_D_INFO,"Done\n"));
  147. MmioWrite32(ALG_BASE + SC_ITS_M3_INT_MUX_SEL_REG, SC_ITS_M3_INT_MUX_SEL_REG_VALUE);
  148. DEBUG((EFI_D_INFO,"Timer CONFIG........."));
  149. PlatformTimerStart ();
  150. DEBUG((EFI_D_INFO,"Done\n"));
  151. return EFI_SUCCESS;
  152. }