PlatformPciLib.c 3.8 KB

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  1. /** @file
  2. Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
  3. Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
  4. This program and the accompanying materials
  5. are licensed and made available under the terms and conditions of the BSD License
  6. which accompanies this distribution. The full text of the license may be found at
  7. http://opensource.org/licenses/bsd-license.php
  8. THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
  9. WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
  10. **/
  11. #include <Library/PcdLib.h>
  12. #include <Library/PlatformPciLib.h>
  13. PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
  14. {// HostBridge 0
  15. /* Port 0 */
  16. {
  17. PCI_HB0RB0_ECAM_BASE,
  18. 0, //BusBase
  19. 63, //BusLimit
  20. (PCI_HB0RB0_ECAM_BASE + SIZE_64MB), //MemBase
  21. (PCI_HB0RB0_ECAM_BASE + PCI_HB0RB0_ECAM_SIZE - 1), //MemLimit
  22. (0), //IoBase
  23. (0), //IoLimit
  24. 0,
  25. 0,
  26. (PCI_HB0RB0_PCI_BASE), //RbPciBar
  27. 0,
  28. 0
  29. },
  30. /* Port 1 */
  31. {
  32. PCI_HB0RB1_ECAM_BASE,
  33. 64, //BusBase
  34. 127, //BusLimit
  35. PCI_HB0RB1_PCIREGION_BASE,
  36. PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1,
  37. PCI_HB0RB1_IO_BASE, //IoBase
  38. PCI_HB0RB1_IO_BASE + PCI_HB0RB1_IO_SIZE - 1, //IoLimit
  39. PCI_HB0RB1_CPUMEMREGIONBASE,
  40. PCI_HB0RB2_CPUIOREGIONBASE,
  41. (PCI_HB0RB1_PCI_BASE), //RbPciBar
  42. PCI_HB0RB1_PCIREGION_BASE,
  43. PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1
  44. },
  45. /* Port 2 */
  46. {
  47. PCI_HB0RB2_ECAM_BASE,
  48. 128, //BusBase
  49. 191, //BusLimit
  50. PCI_HB0RB2_PCIREGION_BASE ,
  51. PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1,
  52. PCI_HB0RB2_IO_BASE, //IoBase
  53. PCI_HB0RB2_IO_BASE + PCI_HB0RB2_IO_SIZE - 1, //IoLimit
  54. PCI_HB0RB2_CPUMEMREGIONBASE,
  55. PCI_HB0RB2_CPUIOREGIONBASE,
  56. (PCI_HB0RB2_PCI_BASE), //RbPciBar
  57. PCI_HB0RB2_PCIREGION_BASE ,
  58. PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1
  59. },
  60. /* Port 3 */
  61. {
  62. PCI_HB0RB3_ECAM_BASE,
  63. 192, //BusBase
  64. 255, //BusLimit
  65. (PCI_HB0RB3_ECAM_BASE), //MemBase
  66. (PCI_HB0RB3_ECAM_BASE + PCI_HB0RB3_ECAM_SIZE - 1), //MemLimit
  67. (0), //IoBase
  68. (0), //IoLimit
  69. 0,
  70. 0,
  71. (PCI_HB0RB3_PCI_BASE), //RbPciBar
  72. 0,
  73. 0
  74. }
  75. },
  76. {// HostBridge 1
  77. /* Port 0 */
  78. {
  79. PCI_HB1RB0_ECAM_BASE,
  80. 0, //BusBase
  81. 0x1, //BusLimit
  82. (PCI_HB1RB0_ECAM_BASE), //MemBase
  83. (PCI_HB1RB0_ECAM_BASE + PCI_HB1RB0_ECAM_SIZE - 1), //MemLimit
  84. (0), //IoBase
  85. (0), //IoLimit
  86. 0,
  87. 0,
  88. (PCI_HB1RB0_PCI_BASE), //RbPciBar
  89. 0,
  90. 0
  91. },
  92. /* Port 1 */
  93. {
  94. PCI_HB1RB1_ECAM_BASE,
  95. 0x2, //BusBase
  96. 0x3, //BusLimit
  97. (PCI_HB1RB1_ECAM_BASE), //MemBase
  98. (PCI_HB1RB1_ECAM_BASE + PCI_HB1RB1_ECAM_SIZE - 1), //MemLimit
  99. (0), //IoBase
  100. (0), //IoLimit
  101. 0,
  102. 0,
  103. (PCI_HB1RB1_PCI_BASE), //RbPciBar
  104. 0,
  105. 0
  106. },
  107. /* Port 2 */
  108. {
  109. PCI_HB1RB2_ECAM_BASE,
  110. 0x4, //BusBase
  111. 0x5, //BusLimit
  112. (PCI_HB1RB2_ECAM_BASE), //MemBase
  113. (PCI_HB1RB2_ECAM_BASE + PCI_HB1RB2_ECAM_SIZE - 1), //MemLimit
  114. (0), //IoBase
  115. (0), //IoLimit
  116. 0,
  117. 0,
  118. (PCI_HB1RB2_PCI_BASE), //RbPciBar
  119. 0,
  120. 0
  121. },
  122. /* Port 3 */
  123. {
  124. PCI_HB1RB3_ECAM_BASE,
  125. 0x6, //BusBase
  126. 0x7, //BusLimit
  127. (PCI_HB1RB3_ECAM_BASE), //MemBase
  128. (PCI_HB1RB3_ECAM_BASE + PCI_HB1RB3_ECAM_SIZE - 1), //MemLimit
  129. (0), //IoBase
  130. (0), //IoLimit
  131. 0,
  132. 0,
  133. (PCI_HB1RB3_PCI_BASE), //RbPciBar
  134. 0,
  135. 0
  136. }
  137. }
  138. };