PeiPchPolicyUpdate.c 21 KB

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  1. /** @file
  2. This file is SampleCode of the library for Intel PCH PEI Policy initialization.
  3. Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. #include "PeiPchPolicyUpdate.h"
  7. #include <Library/BaseMemoryLib.h>
  8. #include <Library/HdaVerbTableLib.h>
  9. #include <Library/MemoryAllocationLib.h>
  10. #include <Library/HobLib.h>
  11. #include <Library/PchGbeLib.h>
  12. #include <Library/PchInfoLib.h>
  13. #include <Library/SataLib.h>
  14. #include <Library/PchPcrLib.h>
  15. #include <Library/PchSerialIoLib.h>
  16. #include <Library/PchPcieRpLib.h>
  17. #include <GpioConfig.h>
  18. #include <Library/DebugLib.h>
  19. #include <Library/PchGbeLib.h>
  20. #include <PlatformBoardConfig.h>
  21. #include <Library/CnviLib.h>
  22. #include <Register/PchRegsLpcCnl.h>
  23. #include <PcieDeviceOverrideTable.h>
  24. #include <Library/ConfigBlockLib.h>
  25. VOID
  26. UpdatePcieClockInfo (
  27. PCH_PCIE_CONFIG *PcieRpConfig,
  28. UINTN Index,
  29. UINT64 Data
  30. )
  31. {
  32. PCD64_BLOB Pcd64;
  33. Pcd64.Blob = Data;
  34. DEBUG ((DEBUG_INFO, "UpdatePcieClockInfo ClkIndex %x ClkUsage %x, Supported %x\n", Index, Pcd64.PcieClock.ClockUsage, Pcd64.PcieClock.ClkReqSupported));
  35. PcieRpConfig->PcieClock[Index].Usage = (UINT8)Pcd64.PcieClock.ClockUsage;
  36. if (Pcd64.PcieClock.ClkReqSupported) {
  37. PcieRpConfig->PcieClock[Index].ClkReq = (UINT8)Index;
  38. } else {
  39. PcieRpConfig->PcieClock[Index].ClkReq = 0xFF;
  40. }
  41. }
  42. /**
  43. This is helper function for getting I2C Pads Internal Termination settings from Pcd
  44. @param[in] Index I2C Controller Index
  45. **/
  46. UINT8
  47. GetSerialIoI2cPadsTerminationFromPcd (
  48. IN UINT8 Index
  49. )
  50. {
  51. switch (Index) {
  52. case 0:
  53. return PcdGet8 (PcdPchSerialIoI2c0PadInternalTerm);
  54. case 1:
  55. return PcdGet8 (PcdPchSerialIoI2c1PadInternalTerm);
  56. case 2:
  57. return PcdGet8 (PcdPchSerialIoI2c2PadInternalTerm);
  58. case 3:
  59. return PcdGet8 (PcdPchSerialIoI2c3PadInternalTerm);
  60. case 4:
  61. return PcdGet8 (PcdPchSerialIoI2c4PadInternalTerm);
  62. case 5:
  63. return PcdGet8 (PcdPchSerialIoI2c5PadInternalTerm);
  64. default:
  65. ASSERT (FALSE); // Invalid I2C Controller Index
  66. }
  67. return 0;
  68. }
  69. /**
  70. This is a helper function for updating USB Policy according to Blob data
  71. @param[in] UsbConfig Pointer to USB_CONFIG data buffer
  72. @param[in] PortIndex USB Port index
  73. @param[in] Data32 Blob containing USB2 Afe (PCD32_BLOB) data
  74. **/
  75. VOID
  76. UpdateUsb20AfePolicy (
  77. IN USB_CONFIG *UsbConfig,
  78. IN UINT8 PortIndex,
  79. UINT32 Data32
  80. )
  81. {
  82. PCD32_BLOB Pcd32;
  83. Pcd32.Blob = Data32;
  84. if (PortIndex < MAX_USB2_PORTS && Pcd32.Info.Petxiset != 0) {
  85. UsbConfig->PortUsb20[PortIndex].Afe.Petxiset = Pcd32.Info.Petxiset;
  86. UsbConfig->PortUsb20[PortIndex].Afe.Txiset = Pcd32.Info.Txiset;
  87. UsbConfig->PortUsb20[PortIndex].Afe.Predeemp = Pcd32.Info.Predeemp;
  88. UsbConfig->PortUsb20[PortIndex].Afe.Pehalfbit = Pcd32.Info.Pehalfbit;
  89. }
  90. }
  91. /**
  92. This function updates USB Policy per port OC Pin number
  93. @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer
  94. @param[in] PortIndex USB Port index
  95. @param[in] Pin OverCurrent pin number
  96. **/
  97. VOID
  98. UpdateUsb20OverCurrentPolicy (
  99. IN USB_CONFIG *UsbConfig,
  100. IN UINT8 PortIndex,
  101. UINT8 Pin
  102. )
  103. {
  104. if (PortIndex < MAX_USB2_PORTS && ((Pin < UsbOverCurrentPinMax) || (Pin == UsbOverCurrentPinSkip))) {
  105. UsbConfig->PortUsb20[PortIndex].OverCurrentPin = Pin;
  106. } else {
  107. if (PortIndex >= MAX_USB2_PORTS) {
  108. DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: USB2 port number %d is not a valid USB2 port number\n", PortIndex));
  109. } else {
  110. DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: Invalid OverCurrent pin specified USB2 port %d\n", PortIndex));
  111. }
  112. }
  113. }
  114. /**
  115. This function updates USB Policy per port OC Pin number
  116. @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer
  117. @param[in] PortIndex USB Port index
  118. @param[in] Pin OverCurrent pin number
  119. **/
  120. VOID
  121. UpdateUsb30OverCurrentPolicy (
  122. IN USB_CONFIG *UsbConfig,
  123. IN UINT8 PortIndex,
  124. UINT8 Pin
  125. )
  126. {
  127. if (PortIndex < MAX_USB3_PORTS && ((Pin < UsbOverCurrentPinMax) || (Pin == UsbOverCurrentPinSkip))) {
  128. UsbConfig->PortUsb30[PortIndex].OverCurrentPin = Pin;
  129. } else {
  130. if (PortIndex >= MAX_USB2_PORTS) {
  131. DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: USB3 port number %d is not a valid USB3 port number\n", PortIndex));
  132. } else {
  133. DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: Invalid OverCurrent pin specified USB3 port %d\n", PortIndex));
  134. }
  135. }
  136. }
  137. /**
  138. This function performs PCH USB Platform Policy initialization
  139. @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer
  140. @param[in] PchSetup Pointer to PCH_SETUP data buffer
  141. **/
  142. VOID
  143. UpdatePchUsbConfig (
  144. IN USB_CONFIG *UsbConfig
  145. )
  146. {
  147. UINTN PortIndex;
  148. UsbConfig->OverCurrentEnable = TRUE;
  149. for (PortIndex = 0; PortIndex < GetPchUsb2MaxPhysicalPortNum (); PortIndex++) {
  150. UsbConfig->PortUsb20[PortIndex].Enable = TRUE;
  151. }
  152. for (PortIndex = 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex++) {
  153. UsbConfig->PortUsb30[PortIndex].Enable = TRUE;
  154. }
  155. UsbConfig->XdciConfig.Enable = FALSE;
  156. //
  157. // USB2 AFE settings.
  158. //
  159. UpdateUsb20AfePolicy (UsbConfig, 0, PcdGet32 (PcdUsb20Port0Afe));
  160. UpdateUsb20AfePolicy (UsbConfig, 1, PcdGet32 (PcdUsb20Port1Afe));
  161. UpdateUsb20AfePolicy (UsbConfig, 2, PcdGet32 (PcdUsb20Port2Afe));
  162. UpdateUsb20AfePolicy (UsbConfig, 3, PcdGet32 (PcdUsb20Port3Afe));
  163. UpdateUsb20AfePolicy (UsbConfig, 4, PcdGet32 (PcdUsb20Port4Afe));
  164. UpdateUsb20AfePolicy (UsbConfig, 5, PcdGet32 (PcdUsb20Port5Afe));
  165. UpdateUsb20AfePolicy (UsbConfig, 6, PcdGet32 (PcdUsb20Port6Afe));
  166. UpdateUsb20AfePolicy (UsbConfig, 7, PcdGet32 (PcdUsb20Port7Afe));
  167. UpdateUsb20AfePolicy (UsbConfig, 8, PcdGet32 (PcdUsb20Port8Afe));
  168. UpdateUsb20AfePolicy (UsbConfig, 9, PcdGet32 (PcdUsb20Port9Afe));
  169. UpdateUsb20AfePolicy (UsbConfig,10, PcdGet32 (PcdUsb20Port10Afe));
  170. UpdateUsb20AfePolicy (UsbConfig,11, PcdGet32 (PcdUsb20Port11Afe));
  171. UpdateUsb20AfePolicy (UsbConfig,12, PcdGet32 (PcdUsb20Port12Afe));
  172. UpdateUsb20AfePolicy (UsbConfig,13, PcdGet32 (PcdUsb20Port13Afe));
  173. UpdateUsb20AfePolicy (UsbConfig,14, PcdGet32 (PcdUsb20Port14Afe));
  174. UpdateUsb20AfePolicy (UsbConfig,15, PcdGet32 (PcdUsb20Port15Afe));
  175. //
  176. // Platform Board programming per the layout of each port.
  177. //
  178. UpdateUsb20OverCurrentPolicy (UsbConfig, 0, PcdGet8 (PcdUsb20OverCurrentPinPort0));
  179. UpdateUsb20OverCurrentPolicy (UsbConfig, 1, PcdGet8 (PcdUsb20OverCurrentPinPort1));
  180. UpdateUsb20OverCurrentPolicy (UsbConfig, 2, PcdGet8 (PcdUsb20OverCurrentPinPort2));
  181. UpdateUsb20OverCurrentPolicy (UsbConfig, 3, PcdGet8 (PcdUsb20OverCurrentPinPort3));
  182. UpdateUsb20OverCurrentPolicy (UsbConfig, 4, PcdGet8 (PcdUsb20OverCurrentPinPort4));
  183. UpdateUsb20OverCurrentPolicy (UsbConfig, 5, PcdGet8 (PcdUsb20OverCurrentPinPort5));
  184. UpdateUsb20OverCurrentPolicy (UsbConfig, 6, PcdGet8 (PcdUsb20OverCurrentPinPort6));
  185. UpdateUsb20OverCurrentPolicy (UsbConfig, 7, PcdGet8 (PcdUsb20OverCurrentPinPort7));
  186. UpdateUsb20OverCurrentPolicy (UsbConfig, 8, PcdGet8 (PcdUsb20OverCurrentPinPort8));
  187. UpdateUsb20OverCurrentPolicy (UsbConfig, 9, PcdGet8 (PcdUsb20OverCurrentPinPort9));
  188. UpdateUsb20OverCurrentPolicy (UsbConfig,10, PcdGet8 (PcdUsb20OverCurrentPinPort10));
  189. UpdateUsb20OverCurrentPolicy (UsbConfig,11, PcdGet8 (PcdUsb20OverCurrentPinPort11));
  190. UpdateUsb20OverCurrentPolicy (UsbConfig,12, PcdGet8 (PcdUsb20OverCurrentPinPort12));
  191. UpdateUsb20OverCurrentPolicy (UsbConfig,13, PcdGet8 (PcdUsb20OverCurrentPinPort13));
  192. UpdateUsb20OverCurrentPolicy (UsbConfig,14, PcdGet8 (PcdUsb20OverCurrentPinPort14));
  193. UpdateUsb20OverCurrentPolicy (UsbConfig,15, PcdGet8 (PcdUsb20OverCurrentPinPort15));
  194. UpdateUsb30OverCurrentPolicy (UsbConfig, 0, PcdGet8 (PcdUsb30OverCurrentPinPort0));
  195. UpdateUsb30OverCurrentPolicy (UsbConfig, 1, PcdGet8 (PcdUsb30OverCurrentPinPort1));
  196. UpdateUsb30OverCurrentPolicy (UsbConfig, 2, PcdGet8 (PcdUsb30OverCurrentPinPort2));
  197. UpdateUsb30OverCurrentPolicy (UsbConfig, 3, PcdGet8 (PcdUsb30OverCurrentPinPort3));
  198. UpdateUsb30OverCurrentPolicy (UsbConfig, 4, PcdGet8 (PcdUsb30OverCurrentPinPort4));
  199. UpdateUsb30OverCurrentPolicy (UsbConfig, 5, PcdGet8 (PcdUsb30OverCurrentPinPort5));
  200. UpdateUsb30OverCurrentPolicy (UsbConfig, 6, PcdGet8 (PcdUsb30OverCurrentPinPort6));
  201. UpdateUsb30OverCurrentPolicy (UsbConfig, 7, PcdGet8 (PcdUsb30OverCurrentPinPort7));
  202. UpdateUsb30OverCurrentPolicy (UsbConfig, 8, PcdGet8 (PcdUsb30OverCurrentPinPort8));
  203. UpdateUsb30OverCurrentPolicy (UsbConfig, 9, PcdGet8 (PcdUsb30OverCurrentPinPort9));
  204. }
  205. /**
  206. Return if input ImageGuid belongs to system FMP GUID list.
  207. @param[in] ImageGuid A pointer to GUID
  208. @retval TRUE ImageGuid is in the list of PcdSystemFmpCapsuleImageTypeIdGuid
  209. @retval FALSE ImageGuid is not in the list of PcdSystemFmpCapsuleImageTypeIdGuid
  210. **/
  211. BOOLEAN
  212. IsSystemFmpGuid (
  213. IN GUID *ImageGuid
  214. )
  215. {
  216. GUID *Guid;
  217. UINTN Count;
  218. UINTN Index;
  219. Guid = PcdGetPtr (PcdSystemFmpCapsuleImageTypeIdGuid);
  220. Count = PcdGetSize (PcdSystemFmpCapsuleImageTypeIdGuid) / sizeof (GUID);
  221. for (Index = 0; Index < Count; Index++, Guid++) {
  222. if (CompareGuid (ImageGuid, Guid)) {
  223. return TRUE;
  224. }
  225. }
  226. return FALSE;
  227. }
  228. /**
  229. This function performs PCH PEI Policy initialization.
  230. @param[in, out] SiPolicy The SI Policy PPI instance
  231. @retval EFI_SUCCESS The PPI is installed and initialized.
  232. @retval EFI ERRORS The PPI is not successfully installed.
  233. @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize the driver
  234. **/
  235. EFI_STATUS
  236. EFIAPI
  237. UpdatePeiPchPolicy (
  238. IN OUT SI_POLICY_PPI *SiPolicy
  239. )
  240. {
  241. EFI_STATUS Status;
  242. UINT8 Index;
  243. DMI_HW_WIDTH_CONTROL *DmiHaAWC;
  244. PCH_GENERAL_CONFIG *PchGeneralConfig;
  245. PCH_PCIE_CONFIG *PcieRpConfig;
  246. PCH_SATA_CONFIG *SataConfig;
  247. PCH_IOAPIC_CONFIG *IoApicConfig;
  248. PCH_DMI_CONFIG *DmiConfig;
  249. PCH_FLASH_PROTECTION_CONFIG *FlashProtectionConfig;
  250. PCH_HDAUDIO_CONFIG *HdAudioConfig;
  251. PCH_INTERRUPT_CONFIG *InterruptConfig;
  252. PCH_ISH_CONFIG *IshConfig;
  253. PCH_LAN_CONFIG *LanConfig;
  254. PCH_LOCK_DOWN_CONFIG *LockDownConfig;
  255. PCH_PM_CONFIG *PmConfig;
  256. PCH_SCS_CONFIG *ScsConfig;
  257. PCH_SERIAL_IO_CONFIG *SerialIoConfig;
  258. PCH_LPC_SIRQ_CONFIG *SerialIrqConfig;
  259. PCH_THERMAL_CONFIG *ThermalConfig;
  260. USB_CONFIG *UsbConfig;
  261. PCH_ESPI_CONFIG *EspiConfig;
  262. PCH_CNVI_CONFIG *CnviConfig;
  263. SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;
  264. Status = GetConfigBlock ((VOID *) SiPolicy, &gPchGeneralConfigGuid, (VOID *) &PchGeneralConfig);
  265. ASSERT_EFI_ERROR (Status);
  266. Status = GetConfigBlock ((VOID *) SiPolicy, &gPcieRpConfigGuid, (VOID *) &PcieRpConfig);
  267. ASSERT_EFI_ERROR (Status);
  268. Status = GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID *) &SataConfig);
  269. ASSERT_EFI_ERROR (Status);
  270. Status = GetConfigBlock ((VOID *) SiPolicy, &gIoApicConfigGuid, (VOID *) &IoApicConfig);
  271. ASSERT_EFI_ERROR (Status);
  272. Status = GetConfigBlock ((VOID *) SiPolicy, &gDmiConfigGuid, (VOID *) &DmiConfig);
  273. ASSERT_EFI_ERROR (Status);
  274. Status = GetConfigBlock ((VOID *) SiPolicy, &gFlashProtectionConfigGuid, (VOID *) &FlashProtectionConfig);
  275. ASSERT_EFI_ERROR (Status);
  276. Status = GetConfigBlock ((VOID *) SiPolicy, &gHdAudioConfigGuid, (VOID *) &HdAudioConfig);
  277. ASSERT_EFI_ERROR (Status);
  278. Status = GetConfigBlock ((VOID *) SiPolicy, &gInterruptConfigGuid, (VOID *) &InterruptConfig);
  279. ASSERT_EFI_ERROR (Status);
  280. Status = GetConfigBlock ((VOID *) SiPolicy, &gIshConfigGuid, (VOID *) &IshConfig);
  281. ASSERT_EFI_ERROR (Status);
  282. Status = GetConfigBlock ((VOID *) SiPolicy, &gLanConfigGuid, (VOID *) &LanConfig);
  283. ASSERT_EFI_ERROR (Status);
  284. Status = GetConfigBlock ((VOID *) SiPolicy, &gLockDownConfigGuid, (VOID *) &LockDownConfig);
  285. ASSERT_EFI_ERROR (Status);
  286. Status = GetConfigBlock ((VOID *) SiPolicy, &gPmConfigGuid, (VOID *) &PmConfig);
  287. ASSERT_EFI_ERROR (Status);
  288. Status = GetConfigBlock ((VOID *) SiPolicy, &gScsConfigGuid, (VOID *) &ScsConfig);
  289. ASSERT_EFI_ERROR (Status);
  290. Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOID *) &SerialIoConfig);
  291. ASSERT_EFI_ERROR (Status);
  292. Status = GetConfigBlock ((VOID *) SiPolicy, &gSerialIrqConfigGuid, (VOID *) &SerialIrqConfig);
  293. ASSERT_EFI_ERROR (Status);
  294. Status = GetConfigBlock ((VOID *) SiPolicy, &gThermalConfigGuid, (VOID *) &ThermalConfig);
  295. ASSERT_EFI_ERROR (Status);
  296. Status = GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *) &UsbConfig);
  297. ASSERT_EFI_ERROR (Status);
  298. Status = GetConfigBlock ((VOID *) SiPolicy, &gEspiConfigGuid, (VOID *) &EspiConfig);
  299. ASSERT_EFI_ERROR (Status);
  300. Status = GetConfigBlock ((VOID *) SiPolicy, &gCnviConfigGuid, (VOID *) &CnviConfig);
  301. ASSERT_EFI_ERROR (Status);
  302. Status = PeiServicesLocatePpi (
  303. &gSiPreMemPolicyPpiGuid,
  304. 0,
  305. NULL,
  306. (VOID **) &SiPreMemPolicyPpi
  307. );
  308. ASSERT_EFI_ERROR (Status);
  309. DmiConfig->PwrOptEnable = TRUE;
  310. PmConfig->PchSlpS3MinAssert = 0;
  311. PmConfig->PchSlpS4MinAssert = 0;
  312. PmConfig->PchSlpSusMinAssert = 0;
  313. PmConfig->PchSlpAMinAssert = 0;
  314. SataConfig->ThermalThrottling.P1T3M = 3;
  315. SataConfig->ThermalThrottling.P1T2M = 2;
  316. SataConfig->ThermalThrottling.P1T1M = 1;
  317. SataConfig->ThermalThrottling.P0T3M = 3;
  318. SataConfig->ThermalThrottling.P0T2M = 2;
  319. SataConfig->ThermalThrottling.P0T1M = 1;
  320. UpdatePcieClockInfo (PcieRpConfig, 0, PcdGet64 (PcdPcieClock0));
  321. UpdatePcieClockInfo (PcieRpConfig, 1, PcdGet64 (PcdPcieClock1));
  322. UpdatePcieClockInfo (PcieRpConfig, 2, PcdGet64 (PcdPcieClock2));
  323. UpdatePcieClockInfo (PcieRpConfig, 3, PcdGet64 (PcdPcieClock3));
  324. UpdatePcieClockInfo (PcieRpConfig, 4, PcdGet64 (PcdPcieClock4));
  325. UpdatePcieClockInfo (PcieRpConfig, 5, PcdGet64 (PcdPcieClock5));
  326. UpdatePcieClockInfo (PcieRpConfig, 6, PcdGet64 (PcdPcieClock6));
  327. UpdatePcieClockInfo (PcieRpConfig, 7, PcdGet64 (PcdPcieClock7));
  328. UpdatePcieClockInfo (PcieRpConfig, 8, PcdGet64 (PcdPcieClock8));
  329. UpdatePcieClockInfo (PcieRpConfig, 9, PcdGet64 (PcdPcieClock9));
  330. UpdatePcieClockInfo (PcieRpConfig, 10, PcdGet64 (PcdPcieClock10));
  331. UpdatePcieClockInfo (PcieRpConfig, 11, PcdGet64 (PcdPcieClock11));
  332. UpdatePcieClockInfo (PcieRpConfig, 12, PcdGet64 (PcdPcieClock12));
  333. UpdatePcieClockInfo (PcieRpConfig, 13, PcdGet64 (PcdPcieClock13));
  334. UpdatePcieClockInfo (PcieRpConfig, 14, PcdGet64 (PcdPcieClock14));
  335. UpdatePcieClockInfo (PcieRpConfig, 15, PcdGet64 (PcdPcieClock15));
  336. PcieRpConfig->PcieDeviceOverrideTablePtr = (UINT32) mPcieDeviceTable;
  337. PcieRpConfig->RootPort[0].ClkReqDetect = TRUE;
  338. PcieRpConfig->RootPort[1].ClkReqDetect = TRUE;
  339. PcieRpConfig->RootPort[2].ClkReqDetect = TRUE;
  340. PcieRpConfig->RootPort[3].ClkReqDetect = TRUE;
  341. PcieRpConfig->RootPort[4].ClkReqDetect = TRUE;
  342. PcieRpConfig->RootPort[5].ClkReqDetect = TRUE;
  343. PcieRpConfig->RootPort[6].ClkReqDetect = TRUE;
  344. PcieRpConfig->RootPort[7].ClkReqDetect = TRUE;
  345. PcieRpConfig->RootPort[8].ClkReqDetect = TRUE;
  346. PcieRpConfig->RootPort[9].ClkReqDetect = TRUE;
  347. PcieRpConfig->RootPort[10].ClkReqDetect = TRUE;
  348. PcieRpConfig->RootPort[11].ClkReqDetect = TRUE;
  349. PcieRpConfig->RootPort[12].ClkReqDetect = TRUE;
  350. PcieRpConfig->RootPort[13].ClkReqDetect = TRUE;
  351. PcieRpConfig->RootPort[14].ClkReqDetect = TRUE;
  352. PcieRpConfig->RootPort[15].ClkReqDetect = TRUE;
  353. PcieRpConfig->RootPort[0].AdvancedErrorReporting = TRUE;
  354. PcieRpConfig->RootPort[1].AdvancedErrorReporting = TRUE;
  355. PcieRpConfig->RootPort[2].AdvancedErrorReporting = TRUE;
  356. PcieRpConfig->RootPort[3].AdvancedErrorReporting = TRUE;
  357. PcieRpConfig->RootPort[4].AdvancedErrorReporting = TRUE;
  358. PcieRpConfig->RootPort[5].AdvancedErrorReporting = TRUE;
  359. PcieRpConfig->RootPort[6].AdvancedErrorReporting = TRUE;
  360. PcieRpConfig->RootPort[7].AdvancedErrorReporting = TRUE;
  361. PcieRpConfig->RootPort[8].AdvancedErrorReporting = TRUE;
  362. PcieRpConfig->RootPort[9].AdvancedErrorReporting = TRUE;
  363. PcieRpConfig->RootPort[10].AdvancedErrorReporting = TRUE;
  364. PcieRpConfig->RootPort[11].AdvancedErrorReporting = TRUE;
  365. PcieRpConfig->RootPort[12].AdvancedErrorReporting = TRUE;
  366. PcieRpConfig->RootPort[13].AdvancedErrorReporting = TRUE;
  367. PcieRpConfig->RootPort[14].AdvancedErrorReporting = TRUE;
  368. PcieRpConfig->RootPort[15].AdvancedErrorReporting = TRUE;
  369. //
  370. // Install HDA Link/iDisplay Codec Verb Table
  371. //
  372. AddPlatformVerbTables (
  373. PchHdaCodecPlatformOnboard,
  374. &(HdAudioConfig->VerbTableEntryNum),
  375. &(HdAudioConfig->VerbTablePtr)
  376. );
  377. LockDownConfig->BiosLock = FALSE;
  378. LockDownConfig->BiosInterface = FALSE;
  379. //
  380. // IOAPIC Config
  381. //
  382. // IoApicConfig->IoApicEntry24_119 = PchSetup.PchIoApic24119Entries;
  383. //
  384. // To support SLP_S0, it's required to disable 8254 timer.
  385. // Note that CSM may require this option to be disabled for correct operation.
  386. // Once 8254 timer disabled, some legacy OPROM and legacy OS will fail while using 8254 timer.
  387. // For some OS environment that it needs to set 8254CGE in late state it should
  388. // set this policy to FALSE and use PmcSet8254ClockGateState (TRUE) in SMM later.
  389. // This is also required during S3 resume.
  390. //
  391. // The Enable8254ClockGatingOnS3 is only applicable when Enable8254ClockGating is disabled.
  392. // If Enable8254ClockGating is enabled, RC will do 8254 CGE programming on S3 as well.
  393. // else, RC will do the programming on S3 when Enable8254ClockGatingOnS3 is enabled.
  394. // This avoids the SMI requirement for the programming.
  395. //
  396. // If S0ix is not enabled, then disable 8254CGE for leagcy boot case.
  397. //
  398. IoApicConfig->Enable8254ClockGating = FALSE;
  399. IoApicConfig->Enable8254ClockGatingOnS3 = FALSE;
  400. //
  401. // SerialIo Config
  402. //
  403. SerialIoConfig->DevMode[0] = 1;
  404. SerialIoConfig->DevMode[1] = 1;
  405. SerialIoConfig->DevMode[2] = 0;
  406. SerialIoConfig->DevMode[3] = 0;
  407. SerialIoConfig->DevMode[4] = 1;
  408. SerialIoConfig->DevMode[5] = 0;
  409. SerialIoConfig->DevMode[6] = 0;
  410. SerialIoConfig->DevMode[7] = 0;
  411. SerialIoConfig->DevMode[8] = 0;
  412. SerialIoConfig->DevMode[9] = 0;
  413. SerialIoConfig->DevMode[10] = 0;
  414. SerialIoConfig->DevMode[11] = 3;
  415. SerialIoConfig->Uart0PinMuxing = 1;
  416. SerialIoConfig->SpiCsPolarity[0] = 1;
  417. SerialIoConfig->SpiCsPolarity[1] = 0;
  418. SerialIoConfig->SpiCsPolarity[2] = 0;
  419. SerialIoConfig->UartHwFlowCtrl[0] = 1;
  420. SerialIoConfig->UartHwFlowCtrl[1] = 1;
  421. SerialIoConfig->UartHwFlowCtrl[2] = 1;
  422. //
  423. // I2C4 and I2C5 don't exist in SPT-H chipset
  424. //
  425. if (IsPchH ()) {
  426. SerialIoConfig->DevMode[PchSerialIoIndexI2C4] = PchSerialIoDisabled;
  427. SerialIoConfig->DevMode[PchSerialIoIndexI2C5] = PchSerialIoDisabled;
  428. }
  429. for (Index = 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index++) {
  430. SerialIoConfig->I2cPadsTermination[Index] = GetSerialIoI2cPadsTerminationFromPcd (Index);
  431. }
  432. PmConfig->SlpS0Override = 2; //PchSetup.SlpS0Override;
  433. PmConfig->SlpS0DisQForDebug = 3; //PchSetup.SlpS0DisQForDebug;
  434. PmConfig->SlpS0Vm075VSupport = 1; // PcdGetBool(PcdSlpS0Vm075VSupport);
  435. PmConfig->CpuC10GatePinEnable = 1;
  436. //
  437. // Thermal Config
  438. //
  439. ThermalConfig->TsmicLock = TRUE;
  440. ThermalConfig->PchHotEnable = PcdGetBool (PcdPchThermalHotEnable);
  441. DmiHaAWC = &ThermalConfig->DmiHaAWC;
  442. DmiHaAWC->TS3TW = 0;
  443. DmiHaAWC->TS2TW = 1;
  444. DmiHaAWC->TS1TW = 2;
  445. DmiHaAWC->TS0TW = 3;
  446. //
  447. // Update Pch Usb Config
  448. //
  449. UpdatePchUsbConfig (
  450. UsbConfig
  451. );
  452. ScsConfig->ScsUfsEnabled = 0;
  453. ScsConfig->ScsEmmcHs400Enabled = 1;
  454. ScsConfig->ScsEmmcHs400TuningRequired = TRUE;
  455. IshConfig->I2c0GpioAssign = 1;
  456. IshConfig->I2c1GpioAssign = 1;
  457. IshConfig->Gp0GpioAssign = 1;
  458. IshConfig->Gp1GpioAssign = 1;
  459. IshConfig->Gp2GpioAssign = 1;
  460. IshConfig->Gp3GpioAssign = 1;
  461. IshConfig->Gp4GpioAssign = 1;
  462. IshConfig->Gp5GpioAssign = 1;
  463. IshConfig->Gp6GpioAssign = 1;
  464. return Status;
  465. }