Start.S 2.2 KB

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  1. #------------------------------------------------------------------------------
  2. #
  3. # Start for LoongArch
  4. #
  5. # Copyright (c) 2022 Loongson Technology Corporation Limited. All rights reserved.<BR>
  6. #
  7. # SPDX-License-Identifier: BSD-2-Clause-Patent
  8. #
  9. # @par Glossary:
  10. # - CSR - CPU Status Register
  11. # - EBASE - Exception Base Address
  12. #------------------------------------------------------------------------------
  13. #ifndef __ASSEMBLY__
  14. #define __ASSEMBLY__
  15. #endif
  16. #include <Library/Cpu.h>
  17. ASM_GLOBAL ASM_PFX(_ModuleEntryPoint)
  18. ASM_GLOBAL ASM_PFX(DeadLoop)
  19. .text
  20. ASM_PFX(_ModuleEntryPoint):
  21. /* configure reset ebase */
  22. la.pcrel T0, DeadLoop
  23. csrwr T0, LOONGARCH_CSR_EBASE
  24. /*disable interrupt*/
  25. li.d T0, (1 << 2)
  26. csrxchg ZERO, T0, LOONGARCH_CSR_CRMD
  27. /* read physical cpu number id */
  28. csrrd T0, LOONGARCH_CSR_CPUNUM
  29. andi T0, T0, 0x3ff
  30. li.d A0, BOOTCORE_ID //0
  31. bne T0, A0, slave_main
  32. call_centry:
  33. /*call C function make sure parameter true*/
  34. li.d A1, FixedPcdGet64(PcdSecPeiTempRamBase) + FixedPcdGet32(PcdSecPeiTempRamSize) # stack base
  35. li.d A0, FixedPcdGet64(PcdFlashPeiFvBase) # PEI Fv base
  36. move SP, A1
  37. addi.d SP, SP, -0x8
  38. bl SecCoreStartupWithStack
  39. slave_main:
  40. # clear mailbox
  41. li.d T1, LOONGSON_CSR_MAIL_BUF0
  42. iocsrwr.d ZERO, T1
  43. # enable IPI interrupt
  44. li.d T0, (1 << 12)
  45. csrxchg T0, T0, LOONGARCH_CSR_ECFG
  46. addi.d T0, ZERO, -1
  47. li.d T1, LOONGSON_IOCSR_IPI_EN
  48. iocsrwr.w T0, T1
  49. li.d T1, LOONGSON_CSR_MAIL_BUF0
  50. 1:
  51. # wait for wakeup
  52. idle 0
  53. nop
  54. iocsrrd.w T0, T1
  55. beqz T0, 1b
  56. # read and clear ipi interrupt
  57. li.d T1, LOONGSON_IOCSR_IPI_STATUS
  58. iocsrrd.w T0, T1
  59. li.d T1, LOONGSON_IOCSR_IPI_CLEAR
  60. iocsrwr.w T0, T1
  61. # disable IPI interrupt
  62. li.d T0, (1 << 12)
  63. csrxchg ZERO, T0, LOONGARCH_CSR_ECFG
  64. # read mail buf and jump to specified entry
  65. li.d T1, LOONGSON_CSR_MAIL_BUF0
  66. iocsrrd.d T0, T1
  67. or RA, T0, ZERO
  68. jirl ZERO, RA, 0x0
  69. .align 12
  70. ASM_PFX(DeadLoop):
  71. b DeadLoop