CoreInfoHob.c 7.0 KB

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  1. /**@file
  2. Build up platform processor information.
  3. Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
  4. SPDX-License-Identifier: BSD-2-Clause-Patent
  5. **/
  6. //
  7. // The package level header files this module uses
  8. //
  9. #include <PiPei.h>
  10. //
  11. // The Library classes this module consumes
  12. //
  13. #include <Library/DebugLib.h>
  14. #include <Library/HobLib.h>
  15. #include <Library/BaseMemoryLib.h>
  16. #include <SmbiosProcessorSpecificData.h>
  17. #include <ProcessorSpecificHobData.h>
  18. #include <SiFiveU5MCCoreplex.h>
  19. #include <Library/SiFiveU54.h>
  20. /**
  21. Build up processor-specific HOB for U5MC Coreplex
  22. @param UniqueId Unique ID of this U5MC Coreplex processor
  23. @return EFI_SUCCESS The PEIM initialized successfully.
  24. **/
  25. STATIC
  26. EFI_STATUS
  27. EFIAPI
  28. CreateU5MCCoreplexProcessorSpecificDataHob (
  29. IN UINTN UniqueId
  30. )
  31. {
  32. EFI_STATUS Status;
  33. UINT32 HartIdNumber;
  34. RISC_V_PROCESSOR_SPECIFIC_HOB_DATA *GuidHobData;
  35. EFI_GUID *ParentCoreGuid;
  36. BOOLEAN MCSupport;
  37. DEBUG ((DEBUG_INFO, "Building U5 Coreplex processor information HOB\n"));
  38. HartIdNumber = 0;
  39. ParentCoreGuid = PcdGetPtr(PcdSiFiveU5MCCoreplexGuid);
  40. MCSupport = PcdGetBool (PcdE5MCSupported);
  41. if (MCSupport == TRUE) {
  42. Status = CreateU54E51CoreProcessorSpecificDataHob (ParentCoreGuid, UniqueId, HartIdNumber, FALSE, TRUE, &GuidHobData);
  43. if (EFI_ERROR (Status) && Status != EFI_UNSUPPORTED) {
  44. DEBUG ((DEBUG_ERROR, "Faile to build U5MC processor informatino HOB\n"));
  45. ASSERT (FALSE);
  46. } else {
  47. if (!EFI_ERROR (Status)) {
  48. DEBUG((DEBUG_INFO, "Support E5 Monitor core on U5 platform, HOB at address 0x%x\n", GuidHobData));
  49. }
  50. }
  51. HartIdNumber ++;
  52. }
  53. for (; HartIdNumber < (FixedPcdGet32 (PcdNumberofU5Cores) + (UINT32)MCSupport); HartIdNumber ++) {
  54. Status = CreateU54E51CoreProcessorSpecificDataHob (ParentCoreGuid, UniqueId, HartIdNumber, (HartIdNumber == FixedPcdGet32 (PcdBootHartId)), FALSE, &GuidHobData);
  55. if (EFI_ERROR (Status) && Status != EFI_UNSUPPORTED) {
  56. DEBUG ((DEBUG_ERROR, "Faile to build U5MC processor informatino HOB\n"));
  57. ASSERT (FALSE);
  58. } else {
  59. if (!EFI_ERROR (Status)) {
  60. DEBUG ((DEBUG_INFO, "Support U5 application core on U5 platform, HOB Data at address 0x%x\n", GuidHobData));
  61. }
  62. }
  63. }
  64. DEBUG ((DEBUG_INFO, "Support %d U5 application cores on U5 platform\n", HartIdNumber - (UINT32)MCSupport));
  65. if (HartIdNumber != FixedPcdGet32 (PcdHartCount)) {
  66. DEBUG ((DEBUG_ERROR, "Improper core settings...\n"));
  67. DEBUG ((DEBUG_ERROR, " PcdHartCount\n"));
  68. DEBUG ((DEBUG_ERROR, " PcdNumberofU5Cores\n"));
  69. DEBUG ((DEBUG_ERROR, " PcdE5MCSupported\n\n"));
  70. ASSERT (FALSE);
  71. }
  72. return Status;
  73. }
  74. /**
  75. Function to build processor related SMBIOS information. RISC-V SMBIOS DXE driver collect
  76. this information and build SMBIOS Type4 and Type7 record.
  77. @param ProcessorUid Unique ID of physical processor which owns this core.
  78. @param SmbiosHobPtr Pointer to receive RISC_V_PROCESSOR_SMBIOS_HOB_DATA. The pointers
  79. maintained in this structure is only valid before memory is discovered.
  80. Access to those pointers after memory is installed will cause unexpected issues.
  81. @return EFI_SUCCESS The SMBIOS Hobs were created successfully.
  82. **/
  83. STATIC
  84. EFI_STATUS
  85. EFIAPI
  86. CreateU5MCProcessorSmbiosDataHob (
  87. IN UINTN ProcessorUid,
  88. OUT RISC_V_PROCESSOR_SMBIOS_HOB_DATA **SmbiosHobPtr
  89. )
  90. {
  91. EFI_GUID *GuidPtr;
  92. RISC_V_PROCESSOR_TYPE7_HOB_DATA L2CacheDataHob;
  93. RISC_V_PROCESSOR_SMBIOS_HOB_DATA SmbiosDataHob;
  94. RISC_V_PROCESSOR_TYPE4_HOB_DATA *ProcessorDataHobPtr;
  95. RISC_V_PROCESSOR_TYPE7_HOB_DATA *L1CacheDataHobPtr;
  96. RISC_V_PROCESSOR_TYPE7_HOB_DATA *L2CacheDataHobPtr;
  97. RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosDataHobPtr;
  98. DEBUG ((DEBUG_INFO, "%a: Entry\n", __FUNCTION__));
  99. if (SmbiosHobPtr == NULL) {
  100. return EFI_INVALID_PARAMETER;
  101. }
  102. CreateU54SmbiosType7L1DataHob (ProcessorUid, &L1CacheDataHobPtr);
  103. CreateU54SmbiosType4DataHob (ProcessorUid, &ProcessorDataHobPtr);
  104. //
  105. // Build up SMBIOS type 7 L2 cache record.
  106. //
  107. ZeroMem((VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
  108. L2CacheDataHob.PrcessorGuid = *((EFI_GUID *)PcdGetPtr (PcdSiFiveU5MCCoreplexGuid));
  109. L2CacheDataHob.ProcessorUid = ProcessorUid;
  110. L2CacheDataHob.SmbiosType7Cache.SocketDesignation = TO_BE_FILLED_BY_VENDOR;
  111. L2CacheDataHob.SmbiosType7Cache.CacheConfiguration = RISC_V_CACHE_CONFIGURATION_CACHE_LEVEL_2 | \
  112. RISC_V_CACHE_CONFIGURATION_LOCATION_EXTERNAL | \
  113. RISC_V_CACHE_CONFIGURATION_ENABLED | \
  114. RISC_V_CACHE_CONFIGURATION_MODE_UNKNOWN;
  115. L2CacheDataHob.SmbiosType7Cache.MaximumCacheSize = TO_BE_FILLED_BY_VENDOR;
  116. L2CacheDataHob.SmbiosType7Cache.InstalledSize = TO_BE_FILLED_BY_VENDOR;
  117. L2CacheDataHob.SmbiosType7Cache.SupportedSRAMType.Unknown = 1;
  118. L2CacheDataHob.SmbiosType7Cache.CurrentSRAMType.Unknown = 1;
  119. L2CacheDataHob.SmbiosType7Cache.CacheSpeed = TO_BE_FILLED_BY_VENDOR;
  120. L2CacheDataHob.SmbiosType7Cache.ErrorCorrectionType = TO_BE_FILLED_BY_VENDOR;
  121. L2CacheDataHob.SmbiosType7Cache.SystemCacheType = CacheTypeUnified;
  122. L2CacheDataHob.SmbiosType7Cache.Associativity = TO_BE_FILLED_BY_VENDOR;
  123. GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosType7GuidHobGuid);
  124. L2CacheDataHobPtr = (RISC_V_PROCESSOR_TYPE7_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&L2CacheDataHob, sizeof (RISC_V_PROCESSOR_TYPE7_HOB_DATA));
  125. if (L2CacheDataHobPtr == NULL) {
  126. DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5 MC Coreplex L2 cache RISC_V_PROCESSOR_TYPE7_HOB_DATA.\n"));
  127. ASSERT (FALSE);
  128. }
  129. ZeroMem((VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA));
  130. SmbiosDataHob.Processor = ProcessorDataHobPtr;
  131. SmbiosDataHob.L1Cache = L1CacheDataHobPtr;
  132. SmbiosDataHob.L2Cache = L2CacheDataHobPtr;
  133. SmbiosDataHob.L3Cache = NULL;
  134. GuidPtr = (EFI_GUID *)PcdGetPtr (PcdProcessorSmbiosGuidHobGuid);
  135. SmbiosDataHobPtr = (RISC_V_PROCESSOR_SMBIOS_HOB_DATA *)BuildGuidDataHob (GuidPtr, (VOID *)&SmbiosDataHob, sizeof (RISC_V_PROCESSOR_SMBIOS_HOB_DATA));
  136. if (SmbiosDataHobPtr == NULL) {
  137. DEBUG ((DEBUG_ERROR, "Fail to create GUID HOB of SiFive U5MC Coreplex RISC_V_PROCESSOR_SMBIOS_HOB_DATA.\n"));
  138. ASSERT (FALSE);
  139. }
  140. *SmbiosHobPtr = SmbiosDataHobPtr;
  141. DEBUG ((DEBUG_INFO, "%a: Exit\n", __FUNCTION__));
  142. return EFI_SUCCESS;
  143. }
  144. /**
  145. Build processor and platform information for the U5 platform
  146. @return EFI_SUCCESS Status.
  147. **/
  148. EFI_STATUS
  149. BuildRiscVSmbiosHobs (
  150. VOID
  151. )
  152. {
  153. EFI_STATUS Status;
  154. RISC_V_PROCESSOR_SMBIOS_HOB_DATA *SmbiosHobPtr;
  155. Status = CreateU5MCCoreplexProcessorSpecificDataHob (0);
  156. if (EFI_ERROR (Status)) {
  157. ASSERT(FALSE);
  158. }
  159. Status = CreateU5MCProcessorSmbiosDataHob (0, &SmbiosHobPtr);
  160. if (EFI_ERROR (Status)) {
  161. ASSERT(FALSE);
  162. }
  163. DEBUG ((DEBUG_INFO, "U5 MC Coreplex SMBIOS DATA HOB at address 0x%x\n", SmbiosHobPtr));
  164. return EFI_SUCCESS;
  165. }